Cross Reference: /gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.000020 # Number of seconds simulated
4sim_ticks 19778500 # Number of ticks simulated
5final_tick 19778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.000023 # Number of seconds simulated
4sim_ticks 23428500 # Number of ticks simulated
5final_tick 23428500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 52882 # Simulator instruction rate (inst/s)
8host_op_rate 52877 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 72439157 # Simulator tick rate (ticks/s)
10host_mem_usage 223656 # Number of bytes of host memory used

7host_inst_rate 53742 # Simulator instruction rate (inst/s)
8host_op_rate 53738 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 87205048 # Simulator tick rate (ticks/s)
10host_mem_usage 223912 # Number of bytes of host memory used

11host_seconds 0.27 # Real time elapsed on the host
12sim_insts 14436 # Number of instructions simulated
13sim_ops 14436 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory

14system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory

15system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory

16system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory

16system.physmem.bytes_read::total 30848 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory

20system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory

21system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1090477033 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 472432186 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1562909220 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1090477033 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1090477033 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1090477033 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 472432186 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1562909220 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 483 # Total number of read requests seen

21system.physmem.num_reads::total 482 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 917856457 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 398830484 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1316686941 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 917856457 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 917856457 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 917856457 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 398830484 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1316686941 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 482 # Total number of read requests seen

31system.physmem.writeReqs 0 # Total number of write requests seen

32system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 30912 # Total number of bytes read from memory

32system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 30848 # Total number of bytes read from memory

34system.physmem.bytesWritten 0 # Total number of bytes written to memory

35system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize()

35system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize()

36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 70 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 24 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::3 6 # Track reads on a per bank basis

43system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis

43system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis

44system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis
45system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 43 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis

--- 13 unchanged lines hidden (view full) ---

65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry

73system.physmem.totGap 19726000 # Total gap between requests

73system.physmem.totGap 23376000 # Total gap between requests

74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes

80system.physmem.readPktSize::6 483 # Categorize read packet sizes

80system.physmem.readPktSize::6 482 # Categorize read packet sizes

81system.physmem.readPktSize::7 0 # Categorize read packet sizes
82system.physmem.readPktSize::8 0 # Categorize read packet sizes
83system.physmem.writePktSize::0 0 # categorize write packet sizes
84system.physmem.writePktSize::1 0 # categorize write packet sizes
85system.physmem.writePktSize::2 0 # categorize write packet sizes
86system.physmem.writePktSize::3 0 # categorize write packet sizes
87system.physmem.writePktSize::4 0 # categorize write packet sizes
88system.physmem.writePktSize::5 0 # categorize write packet sizes

--- 4 unchanged lines hidden (view full) ---

93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes

101system.physmem.rdQLenPdf::0 271 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see

101system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see

105system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see

107system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see

107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see

108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see

--- 43 unchanged lines hidden (view full) ---

159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see

167system.physmem.totQLat 3361480 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 13231480 # Sum of mem lat for all requests
169system.physmem.totBusLat 1932000 # Total cycles spent in databus access
170system.physmem.totBankLat 7938000 # Total cycles spent in bank access
171system.physmem.avgQLat 6959.59 # Average queueing delay per request
172system.physmem.avgBankLat 16434.78 # Average bank access latency per request

167system.physmem.totQLat 2488982 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 12396982 # Sum of mem lat for all requests
169system.physmem.totBusLat 1928000 # Total cycles spent in databus access
170system.physmem.totBankLat 7980000 # Total cycles spent in bank access
171system.physmem.avgQLat 5163.86 # Average queueing delay per request
172system.physmem.avgBankLat 16556.02 # Average bank access latency per request

173system.physmem.avgBusLat 4000.00 # Average bus latency per request

174system.physmem.avgMemAccLat 27394.37 # Average memory access latency
175system.physmem.avgRdBW 1562.91 # Average achieved read bandwidth in MB/s

174system.physmem.avgMemAccLat 25719.88 # Average memory access latency
175system.physmem.avgRdBW 1316.69 # Average achieved read bandwidth in MB/s

176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s

177system.physmem.avgConsumedRdBW 1562.91 # Average consumed read bandwidth in MB/s

177system.physmem.avgConsumedRdBW 1316.69 # Average consumed read bandwidth in MB/s

178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s

180system.physmem.busUtil 9.77 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.67 # Average read queue length over time

180system.physmem.busUtil 8.23 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.53 # Average read queue length over time

182system.physmem.avgWrQLen 0.00 # Average write queue length over time

183system.physmem.readRowHits 394 # Number of row buffer hits during reads

183system.physmem.readRowHits 393 # Number of row buffer hits during reads

184system.physmem.writeRowHits 0 # Number of row buffer hits during writes

185system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads

185system.physmem.readRowHitRate 81.54 # Row buffer hit rate for reads

186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

187system.physmem.avgGap 40840.58 # Average gap between requests

187system.physmem.avgGap 48497.93 # Average gap between requests

188system.cpu.workload.num_syscalls 18 # Number of system calls

189system.cpu.numCycles 39558 # number of cpu cycles simulated

189system.cpu.numCycles 46858 # number of cpu cycles simulated

190system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
191system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

192system.cpu.BPredUnit.lookups 6961 # Number of BP lookups
193system.cpu.BPredUnit.condPredicted 4635 # Number of conditional branches predicted
194system.cpu.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect
195system.cpu.BPredUnit.BTBLookups 5126 # Number of BTB lookups
196system.cpu.BPredUnit.BTBHits 2626 # Number of BTB hits

192system.cpu.BPredUnit.lookups 6941 # Number of BP lookups
193system.cpu.BPredUnit.condPredicted 4630 # Number of conditional branches predicted
194system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect
195system.cpu.BPredUnit.BTBLookups 5115 # Number of BTB lookups
196system.cpu.BPredUnit.BTBHits 2636 # Number of BTB hits

197system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

198system.cpu.BPredUnit.usedRAS 443 # Number of times the RAS was used to get a target.

198system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target.

199system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.

200system.cpu.fetch.icacheStallCycles 11957 # Number of cycles fetch is stalled on an Icache miss
201system.cpu.fetch.Insts 32537 # Number of instructions fetch has processed
202system.cpu.fetch.Branches 6961 # Number of branches that fetch encountered
203system.cpu.fetch.predictedBranches 3069 # Number of branches that fetch has predicted taken
204system.cpu.fetch.Cycles 9617 # Number of cycles fetch has run and was not squashing or blocked
205system.cpu.fetch.SquashCycles 3192 # Number of cycles fetch has spent squashing
206system.cpu.fetch.BlockedCycles 7429 # Number of cycles fetch has spent blocked

200system.cpu.fetch.icacheStallCycles 12393 # Number of cycles fetch is stalled on an Icache miss
201system.cpu.fetch.Insts 32407 # Number of instructions fetch has processed
202system.cpu.fetch.Branches 6941 # Number of branches that fetch encountered
203system.cpu.fetch.predictedBranches 3078 # Number of branches that fetch has predicted taken
204system.cpu.fetch.Cycles 9616 # Number of cycles fetch has run and was not squashing or blocked
205system.cpu.fetch.SquashCycles 3187 # Number of cycles fetch has spent squashing
206system.cpu.fetch.BlockedCycles 8221 # Number of cycles fetch has spent blocked

207system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

208system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps
209system.cpu.fetch.CacheLines 5561 # Number of cache lines fetched

208system.cpu.fetch.PendingTrapStallCycles 943 # Number of stall cycles due to pending traps
209system.cpu.fetch.CacheLines 5564 # Number of cache lines fetched

210system.cpu.fetch.IcacheSquashes 468 # Number of outstanding Icache misses that were squashed

211system.cpu.fetch.rateDist::samples 31813 # Number of instructions fetched each cycle (Total)
212system.cpu.fetch.rateDist::mean 1.022758 # Number of instructions fetched each cycle (Total)
213system.cpu.fetch.rateDist::stdev 2.197280 # Number of instructions fetched each cycle (Total)

211system.cpu.fetch.rateDist::samples 33142 # Number of instructions fetched each cycle (Total)
212system.cpu.fetch.rateDist::mean 0.977823 # Number of instructions fetched each cycle (Total)
213system.cpu.fetch.rateDist::stdev 2.154937 # Number of instructions fetched each cycle (Total)

214system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

215system.cpu.fetch.rateDist::0 22196 69.77% 69.77% # Number of instructions fetched each cycle (Total)
216system.cpu.fetch.rateDist::1 4753 14.94% 84.71% # Number of instructions fetched each cycle (Total)
217system.cpu.fetch.rateDist::2 498 1.57% 86.28% # Number of instructions fetched each cycle (Total)
218system.cpu.fetch.rateDist::3 475 1.49% 87.77% # Number of instructions fetched each cycle (Total)
219system.cpu.fetch.rateDist::4 708 2.23% 89.99% # Number of instructions fetched each cycle (Total)
220system.cpu.fetch.rateDist::5 718 2.26% 92.25% # Number of instructions fetched each cycle (Total)
221system.cpu.fetch.rateDist::6 247 0.78% 93.03% # Number of instructions fetched each cycle (Total)
222system.cpu.fetch.rateDist::7 285 0.90% 93.92% # Number of instructions fetched each cycle (Total)
223system.cpu.fetch.rateDist::8 1933 6.08% 100.00% # Number of instructions fetched each cycle (Total)

215system.cpu.fetch.rateDist::0 23526 70.99% 70.99% # Number of instructions fetched each cycle (Total)
216system.cpu.fetch.rateDist::1 4767 14.38% 85.37% # Number of instructions fetched each cycle (Total)
217system.cpu.fetch.rateDist::2 497 1.50% 86.87% # Number of instructions fetched each cycle (Total)
218system.cpu.fetch.rateDist::3 473 1.43% 88.30% # Number of instructions fetched each cycle (Total)
219system.cpu.fetch.rateDist::4 713 2.15% 90.45% # Number of instructions fetched each cycle (Total)
220system.cpu.fetch.rateDist::5 723 2.18% 92.63% # Number of instructions fetched each cycle (Total)
221system.cpu.fetch.rateDist::6 250 0.75% 93.38% # Number of instructions fetched each cycle (Total)
222system.cpu.fetch.rateDist::7 284 0.86% 94.24% # Number of instructions fetched each cycle (Total)
223system.cpu.fetch.rateDist::8 1909 5.76% 100.00% # Number of instructions fetched each cycle (Total)

224system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
225system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
226system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

227system.cpu.fetch.rateDist::total 31813 # Number of instructions fetched each cycle (Total)
228system.cpu.fetch.branchRate 0.175969 # Number of branch fetches per cycle
229system.cpu.fetch.rate 0.822514 # Number of inst fetches per cycle
230system.cpu.decode.IdleCycles 12679 # Number of cycles decode is idle
231system.cpu.decode.BlockedCycles 8183 # Number of cycles decode is blocked
232system.cpu.decode.RunCycles 8793 # Number of cycles decode is running
233system.cpu.decode.UnblockCycles 186 # Number of cycles decode is unblocking
234system.cpu.decode.SquashCycles 1972 # Number of cycles decode is squashing
235system.cpu.decode.DecodedInsts 30371 # Number of instructions handled by decode
236system.cpu.rename.SquashCycles 1972 # Number of cycles rename is squashing
237system.cpu.rename.IdleCycles 13365 # Number of cycles rename is idle
238system.cpu.rename.BlockCycles 199 # Number of cycles rename is blocking
239system.cpu.rename.serializeStallCycles 7520 # count of cycles rename stalled for serializing inst
240system.cpu.rename.RunCycles 8338 # Number of cycles rename is running
241system.cpu.rename.UnblockCycles 419 # Number of cycles rename is unblocking
242system.cpu.rename.RenamedInsts 27570 # Number of instructions processed by rename

227system.cpu.fetch.rateDist::total 33142 # Number of instructions fetched each cycle (Total)
228system.cpu.fetch.branchRate 0.148128 # Number of branch fetches per cycle
229system.cpu.fetch.rate 0.691600 # Number of inst fetches per cycle
230system.cpu.decode.IdleCycles 13096 # Number of cycles decode is idle
231system.cpu.decode.BlockedCycles 9104 # Number of cycles decode is blocked
232system.cpu.decode.RunCycles 8780 # Number of cycles decode is running
233system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking
234system.cpu.decode.SquashCycles 1965 # Number of cycles decode is squashing
235system.cpu.decode.DecodedInsts 30240 # Number of instructions handled by decode
236system.cpu.rename.SquashCycles 1965 # Number of cycles rename is squashing
237system.cpu.rename.IdleCycles 13789 # Number of cycles rename is idle
238system.cpu.rename.BlockCycles 355 # Number of cycles rename is blocking
239system.cpu.rename.serializeStallCycles 8257 # count of cycles rename stalled for serializing inst
240system.cpu.rename.RunCycles 8329 # Number of cycles rename is running
241system.cpu.rename.UnblockCycles 447 # Number of cycles rename is unblocking
242system.cpu.rename.RenamedInsts 27456 # Number of instructions processed by rename

243system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full

244system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full
245system.cpu.rename.RenamedOperands 24556 # Number of destination operands rename has renamed
246system.cpu.rename.RenameLookups 51144 # Number of register rename lookups that rename has made
247system.cpu.rename.int_rename_lookups 51144 # Number of integer rename lookups

244system.cpu.rename.LSQFullEvents 134 # Number of times rename has blocked due to LSQ full
245system.cpu.rename.RenamedOperands 24477 # Number of destination operands rename has renamed
246system.cpu.rename.RenameLookups 50943 # Number of register rename lookups that rename has made
247system.cpu.rename.int_rename_lookups 50943 # Number of integer rename lookups

248system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed

249system.cpu.rename.UndoneMaps 10737 # Number of HB maps that are undone due to squashing

249system.cpu.rename.UndoneMaps 10658 # Number of HB maps that are undone due to squashing

250system.cpu.rename.serializingInsts 696 # count of serializing insts renamed
251system.cpu.rename.tempSerializingInsts 697 # count of temporary serializing insts renamed

252system.cpu.rename.skidInsts 2824 # count of insts added to the skid buffer
253system.cpu.memDep0.insertedLoads 3648 # Number of loads inserted to the mem dependence unit.
254system.cpu.memDep0.insertedStores 2459 # Number of stores inserted to the mem dependence unit.

252system.cpu.rename.skidInsts 2830 # count of insts added to the skid buffer
253system.cpu.memDep0.insertedLoads 3653 # Number of loads inserted to the mem dependence unit.
254system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit.

255system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
256system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.

257system.cpu.iq.iqInstsAdded 23227 # Number of instructions added to the IQ (excludes non-spec)
258system.cpu.iq.iqNonSpecInstsAdded 659 # Number of non-speculative instructions added to the IQ
259system.cpu.iq.iqInstsIssued 21740 # Number of instructions issued

257system.cpu.iq.iqInstsAdded 23144 # Number of instructions added to the IQ (excludes non-spec)
258system.cpu.iq.iqNonSpecInstsAdded 660 # Number of non-speculative instructions added to the IQ
259system.cpu.iq.iqInstsIssued 21674 # Number of instructions issued

260system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued

261system.cpu.iq.iqSquashedInstsExamined 8509 # Number of squashed instructions iterated over during squash; mainly for profiling
262system.cpu.iq.iqSquashedOperandsExamined 6060 # Number of squashed operands that are examined and possibly removed from graph
263system.cpu.iq.iqSquashedNonSpecRemoved 184 # Number of squashed non-spec instructions that were removed
264system.cpu.iq.issued_per_cycle::samples 31813 # Number of insts issued each cycle
265system.cpu.iq.issued_per_cycle::mean 0.683368 # Number of insts issued each cycle
266system.cpu.iq.issued_per_cycle::stdev 1.298612 # Number of insts issued each cycle

261system.cpu.iq.iqSquashedInstsExamined 8424 # Number of squashed instructions iterated over during squash; mainly for profiling
262system.cpu.iq.iqSquashedOperandsExamined 6018 # Number of squashed operands that are examined and possibly removed from graph
263system.cpu.iq.iqSquashedNonSpecRemoved 185 # Number of squashed non-spec instructions that were removed
264system.cpu.iq.issued_per_cycle::samples 33142 # Number of insts issued each cycle
265system.cpu.iq.issued_per_cycle::mean 0.653974 # Number of insts issued each cycle
266system.cpu.iq.issued_per_cycle::stdev 1.274325 # Number of insts issued each cycle

267system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

268system.cpu.iq.issued_per_cycle::0 22340 70.22% 70.22% # Number of insts issued each cycle
269system.cpu.iq.issued_per_cycle::1 3583 11.26% 81.49% # Number of insts issued each cycle
270system.cpu.iq.issued_per_cycle::2 2473 7.77% 89.26% # Number of insts issued each cycle
271system.cpu.iq.issued_per_cycle::3 1697 5.33% 94.59% # Number of insts issued each cycle
272system.cpu.iq.issued_per_cycle::4 903 2.84% 97.43% # Number of insts issued each cycle
273system.cpu.iq.issued_per_cycle::5 492 1.55% 98.98% # Number of insts issued each cycle
274system.cpu.iq.issued_per_cycle::6 244 0.77% 99.75% # Number of insts issued each cycle
275system.cpu.iq.issued_per_cycle::7 64 0.20% 99.95% # Number of insts issued each cycle
276system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle

268system.cpu.iq.issued_per_cycle::0 23639 71.33% 71.33% # Number of insts issued each cycle
269system.cpu.iq.issued_per_cycle::1 3658 11.04% 82.36% # Number of insts issued each cycle
270system.cpu.iq.issued_per_cycle::2 2441 7.37% 89.73% # Number of insts issued each cycle
271system.cpu.iq.issued_per_cycle::3 1702 5.14% 94.86% # Number of insts issued each cycle
272system.cpu.iq.issued_per_cycle::4 894 2.70% 97.56% # Number of insts issued each cycle
273system.cpu.iq.issued_per_cycle::5 488 1.47% 99.03% # Number of insts issued each cycle
274system.cpu.iq.issued_per_cycle::6 244 0.74% 99.77% # Number of insts issued each cycle
275system.cpu.iq.issued_per_cycle::7 60 0.18% 99.95% # Number of insts issued each cycle
276system.cpu.iq.issued_per_cycle::8 16 0.05% 100.00% # Number of insts issued each cycle

277system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
278system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
279system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

280system.cpu.iq.issued_per_cycle::total 31813 # Number of insts issued each cycle

280system.cpu.iq.issued_per_cycle::total 33142 # Number of insts issued each cycle

281system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

282system.cpu.iq.fu_full::IntAlu 50 28.09% 28.09% # attempts to use FU when none available
283system.cpu.iq.fu_full::IntMult 0 0.00% 28.09% # attempts to use FU when none available
284system.cpu.iq.fu_full::IntDiv 0 0.00% 28.09% # attempts to use FU when none available
285system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.09% # attempts to use FU when none available
286system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.09% # attempts to use FU when none available
287system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.09% # attempts to use FU when none available
288system.cpu.iq.fu_full::FloatMult 0 0.00% 28.09% # attempts to use FU when none available
289system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.09% # attempts to use FU when none available
290system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.09% # attempts to use FU when none available
291system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.09% # attempts to use FU when none available
292system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.09% # attempts to use FU when none available
293system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.09% # attempts to use FU when none available
294system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.09% # attempts to use FU when none available
295system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.09% # attempts to use FU when none available
296system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.09% # attempts to use FU when none available
297system.cpu.iq.fu_full::SimdMult 0 0.00% 28.09% # attempts to use FU when none available
298system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.09% # attempts to use FU when none available
299system.cpu.iq.fu_full::SimdShift 0 0.00% 28.09% # attempts to use FU when none available
300system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.09% # attempts to use FU when none available
301system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.09% # attempts to use FU when none available
302system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.09% # attempts to use FU when none available
303system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.09% # attempts to use FU when none available
304system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.09% # attempts to use FU when none available
305system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.09% # attempts to use FU when none available
306system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.09% # attempts to use FU when none available
307system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.09% # attempts to use FU when none available
308system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.09% # attempts to use FU when none available
309system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.09% # attempts to use FU when none available
310system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.09% # attempts to use FU when none available
311system.cpu.iq.fu_full::MemRead 26 14.61% 42.70% # attempts to use FU when none available
312system.cpu.iq.fu_full::MemWrite 102 57.30% 100.00% # attempts to use FU when none available

282system.cpu.iq.fu_full::IntAlu 49 28.16% 28.16% # attempts to use FU when none available
283system.cpu.iq.fu_full::IntMult 0 0.00% 28.16% # attempts to use FU when none available
284system.cpu.iq.fu_full::IntDiv 0 0.00% 28.16% # attempts to use FU when none available
285system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.16% # attempts to use FU when none available
286system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.16% # attempts to use FU when none available
287system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.16% # attempts to use FU when none available
288system.cpu.iq.fu_full::FloatMult 0 0.00% 28.16% # attempts to use FU when none available
289system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.16% # attempts to use FU when none available
290system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.16% # attempts to use FU when none available
291system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.16% # attempts to use FU when none available
292system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.16% # attempts to use FU when none available
293system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.16% # attempts to use FU when none available
294system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.16% # attempts to use FU when none available
295system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.16% # attempts to use FU when none available
296system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.16% # attempts to use FU when none available
297system.cpu.iq.fu_full::SimdMult 0 0.00% 28.16% # attempts to use FU when none available
298system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.16% # attempts to use FU when none available
299system.cpu.iq.fu_full::SimdShift 0 0.00% 28.16% # attempts to use FU when none available
300system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.16% # attempts to use FU when none available
301system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.16% # attempts to use FU when none available
302system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.16% # attempts to use FU when none available
303system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.16% # attempts to use FU when none available
304system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.16% # attempts to use FU when none available
305system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.16% # attempts to use FU when none available
306system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.16% # attempts to use FU when none available
307system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.16% # attempts to use FU when none available
308system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.16% # attempts to use FU when none available
309system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.16% # attempts to use FU when none available
310system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.16% # attempts to use FU when none available
311system.cpu.iq.fu_full::MemRead 26 14.94% 43.10% # attempts to use FU when none available
312system.cpu.iq.fu_full::MemWrite 99 56.90% 100.00% # attempts to use FU when none available

313system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
314system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
315system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

316system.cpu.iq.FU_type_0::IntAlu 16052 73.84% 73.84% # Type of FU issued
317system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued
318system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued
319system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued
320system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued
321system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued
322system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued
323system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued
324system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued
325system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued
326system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued
327system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued
328system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued
329system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued
330system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued
331system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued
332system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued
333system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued
334system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued
335system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued
336system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued
337system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued
338system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued
339system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued
340system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued
341system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued
342system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued
343system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued
344system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued
345system.cpu.iq.FU_type_0::MemRead 3424 15.75% 89.59% # Type of FU issued
346system.cpu.iq.FU_type_0::MemWrite 2264 10.41% 100.00% # Type of FU issued

316system.cpu.iq.FU_type_0::IntAlu 16000 73.82% 73.82% # Type of FU issued
317system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.82% # Type of FU issued
318system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.82% # Type of FU issued
319system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.82% # Type of FU issued
320system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.82% # Type of FU issued
321system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.82% # Type of FU issued
322system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.82% # Type of FU issued
323system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.82% # Type of FU issued
324system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.82% # Type of FU issued
325system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.82% # Type of FU issued
326system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.82% # Type of FU issued
327system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.82% # Type of FU issued
328system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.82% # Type of FU issued
329system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.82% # Type of FU issued
330system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.82% # Type of FU issued
331system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.82% # Type of FU issued
332system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.82% # Type of FU issued
333system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.82% # Type of FU issued
334system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.82% # Type of FU issued
335system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.82% # Type of FU issued
336system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.82% # Type of FU issued
337system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.82% # Type of FU issued
338system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.82% # Type of FU issued
339system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.82% # Type of FU issued
340system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.82% # Type of FU issued
341system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.82% # Type of FU issued
342system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.82% # Type of FU issued
343system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.82% # Type of FU issued
344system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.82% # Type of FU issued
345system.cpu.iq.FU_type_0::MemRead 3426 15.81% 89.63% # Type of FU issued
346system.cpu.iq.FU_type_0::MemWrite 2248 10.37% 100.00% # Type of FU issued

347system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
348system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

349system.cpu.iq.FU_type_0::total 21740 # Type of FU issued
350system.cpu.iq.rate 0.549573 # Inst issue rate
351system.cpu.iq.fu_busy_cnt 178 # FU busy when requested
352system.cpu.iq.fu_busy_rate 0.008188 # FU busy rate (busy events/executed inst)
353system.cpu.iq.int_inst_queue_reads 75584 # Number of integer instruction queue reads
354system.cpu.iq.int_inst_queue_writes 32421 # Number of integer instruction queue writes
355system.cpu.iq.int_inst_queue_wakeup_accesses 19938 # Number of integer instruction queue wakeup accesses

349system.cpu.iq.FU_type_0::total 21674 # Type of FU issued
350system.cpu.iq.rate 0.462546 # Inst issue rate
351system.cpu.iq.fu_busy_cnt 174 # FU busy when requested
352system.cpu.iq.fu_busy_rate 0.008028 # FU busy rate (busy events/executed inst)
353system.cpu.iq.int_inst_queue_reads 76777 # Number of integer instruction queue reads
354system.cpu.iq.int_inst_queue_writes 32254 # Number of integer instruction queue writes
355system.cpu.iq.int_inst_queue_wakeup_accesses 19887 # Number of integer instruction queue wakeup accesses

356system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
357system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
358system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

359system.cpu.iq.int_alu_accesses 21918 # Number of integer alu accesses

359system.cpu.iq.int_alu_accesses 21848 # Number of integer alu accesses

360system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
361system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
362system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

363system.cpu.iew.lsq.thread0.squashedLoads 1423 # Number of loads squashed

363system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed

364system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
365system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations

366system.cpu.iew.lsq.thread0.squashedStores 1011 # Number of stores squashed

366system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed

367system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
368system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
369system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled

370system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked

370system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked

371system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

372system.cpu.iew.iewSquashCycles 1972 # Number of cycles IEW is squashing
373system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking
374system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
375system.cpu.iew.iewDispatchedInsts 25068 # Number of instructions dispatched to IQ
376system.cpu.iew.iewDispSquashedInsts 512 # Number of squashed instructions skipped by dispatch
377system.cpu.iew.iewDispLoadInsts 3648 # Number of dispatched load instructions
378system.cpu.iew.iewDispStoreInsts 2459 # Number of dispatched store instructions
379system.cpu.iew.iewDispNonSpecInsts 659 # Number of dispatched non-speculative instructions

372system.cpu.iew.iewSquashCycles 1965 # Number of cycles IEW is squashing
373system.cpu.iew.iewBlockCycles 238 # Number of cycles IEW is blocking
374system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
375system.cpu.iew.iewDispatchedInsts 24981 # Number of instructions dispatched to IQ
376system.cpu.iew.iewDispSquashedInsts 536 # Number of squashed instructions skipped by dispatch
377system.cpu.iew.iewDispLoadInsts 3653 # Number of dispatched load instructions
378system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions
379system.cpu.iew.iewDispNonSpecInsts 660 # Number of dispatched non-speculative instructions

380system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
381system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
382system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations

383system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly
384system.cpu.iew.predictedNotTakenIncorrect 961 # Number of branches that were predicted not taken incorrectly
385system.cpu.iew.branchMispredicts 1257 # Number of branch mispredicts detected at execute
386system.cpu.iew.iewExecutedInsts 20524 # Number of executed instructions
387system.cpu.iew.iewExecLoadInsts 3260 # Number of load instructions executed
388system.cpu.iew.iewExecSquashedInsts 1216 # Number of squashed instructions skipped in execute

383system.cpu.iew.predictedTakenIncorrect 295 # Number of branches that were predicted taken incorrectly
384system.cpu.iew.predictedNotTakenIncorrect 957 # Number of branches that were predicted not taken incorrectly
385system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute
386system.cpu.iew.iewExecutedInsts 20477 # Number of executed instructions
387system.cpu.iew.iewExecLoadInsts 3262 # Number of load instructions executed
388system.cpu.iew.iewExecSquashedInsts 1197 # Number of squashed instructions skipped in execute

389system.cpu.iew.exec_swp 0 # number of swp insts executed

390system.cpu.iew.exec_nop 1182 # number of nop insts executed
391system.cpu.iew.exec_refs 5396 # number of memory reference insts executed
392system.cpu.iew.exec_branches 4297 # Number of branches executed
393system.cpu.iew.exec_stores 2136 # Number of stores executed
394system.cpu.iew.exec_rate 0.518833 # Inst execution rate
395system.cpu.iew.wb_sent 20197 # cumulative count of insts sent to commit
396system.cpu.iew.wb_count 19938 # cumulative count of insts written-back
397system.cpu.iew.wb_producers 9248 # num instructions producing a value
398system.cpu.iew.wb_consumers 11357 # num instructions consuming a value

390system.cpu.iew.exec_nop 1177 # number of nop insts executed
391system.cpu.iew.exec_refs 5386 # number of memory reference insts executed
392system.cpu.iew.exec_branches 4289 # Number of branches executed
393system.cpu.iew.exec_stores 2124 # Number of stores executed
394system.cpu.iew.exec_rate 0.437001 # Inst execution rate
395system.cpu.iew.wb_sent 20145 # cumulative count of insts sent to commit
396system.cpu.iew.wb_count 19887 # cumulative count of insts written-back
397system.cpu.iew.wb_producers 9217 # num instructions producing a value
398system.cpu.iew.wb_consumers 11299 # num instructions consuming a value

399system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

400system.cpu.iew.wb_rate 0.504019 # insts written-back per cycle
401system.cpu.iew.wb_fanout 0.814300 # average fanout of values written-back

400system.cpu.iew.wb_rate 0.424410 # insts written-back per cycle
401system.cpu.iew.wb_fanout 0.815736 # average fanout of values written-back

402system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

403system.cpu.commit.commitSquashedInsts 9816 # The number of squashed insts skipped by commit

403system.cpu.commit.commitSquashedInsts 9729 # The number of squashed insts skipped by commit

404system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards

405system.cpu.commit.branchMispredicts 1124 # The number of times a branch was mispredicted
406system.cpu.commit.committed_per_cycle::samples 29858 # Number of insts commited each cycle
407system.cpu.commit.committed_per_cycle::mean 0.507804 # Number of insts commited each cycle
408system.cpu.commit.committed_per_cycle::stdev 1.195478 # Number of insts commited each cycle

405system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted
406system.cpu.commit.committed_per_cycle::samples 31194 # Number of insts commited each cycle
407system.cpu.commit.committed_per_cycle::mean 0.486055 # Number of insts commited each cycle
408system.cpu.commit.committed_per_cycle::stdev 1.173479 # Number of insts commited each cycle

409system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

410system.cpu.commit.committed_per_cycle::0 22523 75.43% 75.43% # Number of insts commited each cycle
411system.cpu.commit.committed_per_cycle::1 3989 13.36% 88.79% # Number of insts commited each cycle
412system.cpu.commit.committed_per_cycle::2 1473 4.93% 93.73% # Number of insts commited each cycle
413system.cpu.commit.committed_per_cycle::3 787 2.64% 96.36% # Number of insts commited each cycle
414system.cpu.commit.committed_per_cycle::4 343 1.15% 97.51% # Number of insts commited each cycle
415system.cpu.commit.committed_per_cycle::5 245 0.82% 98.33% # Number of insts commited each cycle
416system.cpu.commit.committed_per_cycle::6 323 1.08% 99.41% # Number of insts commited each cycle
417system.cpu.commit.committed_per_cycle::7 69 0.23% 99.64% # Number of insts commited each cycle
418system.cpu.commit.committed_per_cycle::8 106 0.36% 100.00% # Number of insts commited each cycle

410system.cpu.commit.committed_per_cycle::0 23830 76.39% 76.39% # Number of insts commited each cycle
411system.cpu.commit.committed_per_cycle::1 4047 12.97% 89.37% # Number of insts commited each cycle
412system.cpu.commit.committed_per_cycle::2 1444 4.63% 94.00% # Number of insts commited each cycle
413system.cpu.commit.committed_per_cycle::3 788 2.53% 96.52% # Number of insts commited each cycle
414system.cpu.commit.committed_per_cycle::4 343 1.10% 97.62% # Number of insts commited each cycle
415system.cpu.commit.committed_per_cycle::5 244 0.78% 98.40% # Number of insts commited each cycle
416system.cpu.commit.committed_per_cycle::6 322 1.03% 99.44% # Number of insts commited each cycle
417system.cpu.commit.committed_per_cycle::7 69 0.22% 99.66% # Number of insts commited each cycle
418system.cpu.commit.committed_per_cycle::8 107 0.34% 100.00% # Number of insts commited each cycle

419system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
420system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
421system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

422system.cpu.commit.committed_per_cycle::total 29858 # Number of insts commited each cycle

422system.cpu.commit.committed_per_cycle::total 31194 # Number of insts commited each cycle

423system.cpu.commit.committedInsts 15162 # Number of instructions committed
424system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
425system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
426system.cpu.commit.refs 3673 # Number of memory references committed
427system.cpu.commit.loads 2225 # Number of loads committed
428system.cpu.commit.membars 0 # Number of memory barriers committed
429system.cpu.commit.branches 3358 # Number of branches committed
430system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
431system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
432system.cpu.commit.function_calls 187 # Number of function calls committed.

433system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached

433system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached

434system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

435system.cpu.rob.rob_reads 53907 # The number of ROB reads
436system.cpu.rob.rob_writes 51935 # The number of ROB writes
437system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself
438system.cpu.idleCycles 7745 # Total number of cycles that the CPU has spent unscheduled due to idling

435system.cpu.rob.rob_reads 55155 # The number of ROB reads
436system.cpu.rob.rob_writes 51753 # The number of ROB writes
437system.cpu.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself
438system.cpu.idleCycles 13716 # Total number of cycles that the CPU has spent unscheduled due to idling

439system.cpu.committedInsts 14436 # Number of Instructions Simulated
440system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
441system.cpu.committedInsts_total 14436 # Number of Instructions Simulated

442system.cpu.cpi 2.740233 # CPI: Cycles Per Instruction
443system.cpu.cpi_total 2.740233 # CPI: Total CPI of All Threads
444system.cpu.ipc 0.364933 # IPC: Instructions Per Cycle
445system.cpu.ipc_total 0.364933 # IPC: Total IPC of All Threads
446system.cpu.int_regfile_reads 32646 # number of integer regfile reads
447system.cpu.int_regfile_writes 18155 # number of integer regfile writes
448system.cpu.misc_regfile_reads 7050 # number of misc regfile reads

442system.cpu.cpi 3.245913 # CPI: Cycles Per Instruction
443system.cpu.cpi_total 3.245913 # CPI: Total CPI of All Threads
444system.cpu.ipc 0.308080 # IPC: Instructions Per Cycle
445system.cpu.ipc_total 0.308080 # IPC: Total IPC of All Threads
446system.cpu.int_regfile_reads 32584 # number of integer regfile reads
447system.cpu.int_regfile_writes 18115 # number of integer regfile writes
448system.cpu.misc_regfile_reads 7035 # number of misc regfile reads

449system.cpu.misc_regfile_writes 569 # number of misc regfile writes
450system.cpu.icache.replacements 0 # number of replacements

451system.cpu.icache.tagsinuse 200.987114 # Cycle average of tags in use
452system.cpu.icache.total_refs 5096 # Total number of references to valid blocks.
453system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks.
454system.cpu.icache.avg_refs 15.032448 # Average number of references to valid blocks.

451system.cpu.icache.tagsinuse 194.443697 # Cycle average of tags in use
452system.cpu.icache.total_refs 5086 # Total number of references to valid blocks.
453system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks.
454system.cpu.icache.avg_refs 15.047337 # Average number of references to valid blocks.

455system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

456system.cpu.icache.occ_blocks::cpu.inst 200.987114 # Average occupied blocks per requestor
457system.cpu.icache.occ_percent::cpu.inst 0.098138 # Average percentage of cache occupancy
458system.cpu.icache.occ_percent::total 0.098138 # Average percentage of cache occupancy
459system.cpu.icache.ReadReq_hits::cpu.inst 5096 # number of ReadReq hits
460system.cpu.icache.ReadReq_hits::total 5096 # number of ReadReq hits
461system.cpu.icache.demand_hits::cpu.inst 5096 # number of demand (read+write) hits
462system.cpu.icache.demand_hits::total 5096 # number of demand (read+write) hits
463system.cpu.icache.overall_hits::cpu.inst 5096 # number of overall hits
464system.cpu.icache.overall_hits::total 5096 # number of overall hits
465system.cpu.icache.ReadReq_misses::cpu.inst 465 # number of ReadReq misses
466system.cpu.icache.ReadReq_misses::total 465 # number of ReadReq misses
467system.cpu.icache.demand_misses::cpu.inst 465 # number of demand (read+write) misses
468system.cpu.icache.demand_misses::total 465 # number of demand (read+write) misses
469system.cpu.icache.overall_misses::cpu.inst 465 # number of overall misses
470system.cpu.icache.overall_misses::total 465 # number of overall misses
471system.cpu.icache.ReadReq_miss_latency::cpu.inst 14626000 # number of ReadReq miss cycles
472system.cpu.icache.ReadReq_miss_latency::total 14626000 # number of ReadReq miss cycles
473system.cpu.icache.demand_miss_latency::cpu.inst 14626000 # number of demand (read+write) miss cycles
474system.cpu.icache.demand_miss_latency::total 14626000 # number of demand (read+write) miss cycles
475system.cpu.icache.overall_miss_latency::cpu.inst 14626000 # number of overall miss cycles
476system.cpu.icache.overall_miss_latency::total 14626000 # number of overall miss cycles
477system.cpu.icache.ReadReq_accesses::cpu.inst 5561 # number of ReadReq accesses(hits+misses)
478system.cpu.icache.ReadReq_accesses::total 5561 # number of ReadReq accesses(hits+misses)
479system.cpu.icache.demand_accesses::cpu.inst 5561 # number of demand (read+write) accesses
480system.cpu.icache.demand_accesses::total 5561 # number of demand (read+write) accesses
481system.cpu.icache.overall_accesses::cpu.inst 5561 # number of overall (read+write) accesses
482system.cpu.icache.overall_accesses::total 5561 # number of overall (read+write) accesses
483system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.083618 # miss rate for ReadReq accesses
484system.cpu.icache.ReadReq_miss_rate::total 0.083618 # miss rate for ReadReq accesses
485system.cpu.icache.demand_miss_rate::cpu.inst 0.083618 # miss rate for demand accesses
486system.cpu.icache.demand_miss_rate::total 0.083618 # miss rate for demand accesses
487system.cpu.icache.overall_miss_rate::cpu.inst 0.083618 # miss rate for overall accesses
488system.cpu.icache.overall_miss_rate::total 0.083618 # miss rate for overall accesses
489system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31453.763441 # average ReadReq miss latency
490system.cpu.icache.ReadReq_avg_miss_latency::total 31453.763441 # average ReadReq miss latency
491system.cpu.icache.demand_avg_miss_latency::cpu.inst 31453.763441 # average overall miss latency
492system.cpu.icache.demand_avg_miss_latency::total 31453.763441 # average overall miss latency
493system.cpu.icache.overall_avg_miss_latency::cpu.inst 31453.763441 # average overall miss latency
494system.cpu.icache.overall_avg_miss_latency::total 31453.763441 # average overall miss latency

456system.cpu.icache.occ_blocks::cpu.inst 194.443697 # Average occupied blocks per requestor
457system.cpu.icache.occ_percent::cpu.inst 0.094943 # Average percentage of cache occupancy
458system.cpu.icache.occ_percent::total 0.094943 # Average percentage of cache occupancy
459system.cpu.icache.ReadReq_hits::cpu.inst 5086 # number of ReadReq hits
460system.cpu.icache.ReadReq_hits::total 5086 # number of ReadReq hits
461system.cpu.icache.demand_hits::cpu.inst 5086 # number of demand (read+write) hits
462system.cpu.icache.demand_hits::total 5086 # number of demand (read+write) hits
463system.cpu.icache.overall_hits::cpu.inst 5086 # number of overall hits
464system.cpu.icache.overall_hits::total 5086 # number of overall hits
465system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses
466system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses
467system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses
468system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses
469system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses
470system.cpu.icache.overall_misses::total 478 # number of overall misses
471system.cpu.icache.ReadReq_miss_latency::cpu.inst 21903000 # number of ReadReq miss cycles
472system.cpu.icache.ReadReq_miss_latency::total 21903000 # number of ReadReq miss cycles
473system.cpu.icache.demand_miss_latency::cpu.inst 21903000 # number of demand (read+write) miss cycles
474system.cpu.icache.demand_miss_latency::total 21903000 # number of demand (read+write) miss cycles
475system.cpu.icache.overall_miss_latency::cpu.inst 21903000 # number of overall miss cycles
476system.cpu.icache.overall_miss_latency::total 21903000 # number of overall miss cycles
477system.cpu.icache.ReadReq_accesses::cpu.inst 5564 # number of ReadReq accesses(hits+misses)
478system.cpu.icache.ReadReq_accesses::total 5564 # number of ReadReq accesses(hits+misses)
479system.cpu.icache.demand_accesses::cpu.inst 5564 # number of demand (read+write) accesses
480system.cpu.icache.demand_accesses::total 5564 # number of demand (read+write) accesses
481system.cpu.icache.overall_accesses::cpu.inst 5564 # number of overall (read+write) accesses
482system.cpu.icache.overall_accesses::total 5564 # number of overall (read+write) accesses
483system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085909 # miss rate for ReadReq accesses
484system.cpu.icache.ReadReq_miss_rate::total 0.085909 # miss rate for ReadReq accesses
485system.cpu.icache.demand_miss_rate::cpu.inst 0.085909 # miss rate for demand accesses
486system.cpu.icache.demand_miss_rate::total 0.085909 # miss rate for demand accesses
487system.cpu.icache.overall_miss_rate::cpu.inst 0.085909 # miss rate for overall accesses
488system.cpu.icache.overall_miss_rate::total 0.085909 # miss rate for overall accesses
489system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45822.175732 # average ReadReq miss latency
490system.cpu.icache.ReadReq_avg_miss_latency::total 45822.175732 # average ReadReq miss latency
491system.cpu.icache.demand_avg_miss_latency::cpu.inst 45822.175732 # average overall miss latency
492system.cpu.icache.demand_avg_miss_latency::total 45822.175732 # average overall miss latency
493system.cpu.icache.overall_avg_miss_latency::cpu.inst 45822.175732 # average overall miss latency
494system.cpu.icache.overall_avg_miss_latency::total 45822.175732 # average overall miss latency

495system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
496system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
497system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
498system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
499system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
500system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
501system.cpu.icache.fast_writes 0 # number of fast writes performed
502system.cpu.icache.cache_copies 0 # number of cache copies performed

503system.cpu.icache.ReadReq_mshr_hits::cpu.inst 126 # number of ReadReq MSHR hits
504system.cpu.icache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits
505system.cpu.icache.demand_mshr_hits::cpu.inst 126 # number of demand (read+write) MSHR hits
506system.cpu.icache.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits
507system.cpu.icache.overall_mshr_hits::cpu.inst 126 # number of overall MSHR hits
508system.cpu.icache.overall_mshr_hits::total 126 # number of overall MSHR hits
509system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses
510system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses
511system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses
512system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses
513system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses
514system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses
515system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11056500 # number of ReadReq MSHR miss cycles
516system.cpu.icache.ReadReq_mshr_miss_latency::total 11056500 # number of ReadReq MSHR miss cycles
517system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11056500 # number of demand (read+write) MSHR miss cycles
518system.cpu.icache.demand_mshr_miss_latency::total 11056500 # number of demand (read+write) MSHR miss cycles
519system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11056500 # number of overall MSHR miss cycles
520system.cpu.icache.overall_mshr_miss_latency::total 11056500 # number of overall MSHR miss cycles
521system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060960 # mshr miss rate for ReadReq accesses
522system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060960 # mshr miss rate for ReadReq accesses
523system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060960 # mshr miss rate for demand accesses
524system.cpu.icache.demand_mshr_miss_rate::total 0.060960 # mshr miss rate for demand accesses
525system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060960 # mshr miss rate for overall accesses
526system.cpu.icache.overall_mshr_miss_rate::total 0.060960 # mshr miss rate for overall accesses
527system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32615.044248 # average ReadReq mshr miss latency
528system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32615.044248 # average ReadReq mshr miss latency
529system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32615.044248 # average overall mshr miss latency
530system.cpu.icache.demand_avg_mshr_miss_latency::total 32615.044248 # average overall mshr miss latency
531system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32615.044248 # average overall mshr miss latency
532system.cpu.icache.overall_avg_mshr_miss_latency::total 32615.044248 # average overall mshr miss latency

503system.cpu.icache.ReadReq_mshr_hits::cpu.inst 140 # number of ReadReq MSHR hits
504system.cpu.icache.ReadReq_mshr_hits::total 140 # number of ReadReq MSHR hits
505system.cpu.icache.demand_mshr_hits::cpu.inst 140 # number of demand (read+write) MSHR hits
506system.cpu.icache.demand_mshr_hits::total 140 # number of demand (read+write) MSHR hits
507system.cpu.icache.overall_mshr_hits::cpu.inst 140 # number of overall MSHR hits
508system.cpu.icache.overall_mshr_hits::total 140 # number of overall MSHR hits
509system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
510system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
511system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
512system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
513system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
514system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
515system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16530500 # number of ReadReq MSHR miss cycles
516system.cpu.icache.ReadReq_mshr_miss_latency::total 16530500 # number of ReadReq MSHR miss cycles
517system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16530500 # number of demand (read+write) MSHR miss cycles
518system.cpu.icache.demand_mshr_miss_latency::total 16530500 # number of demand (read+write) MSHR miss cycles
519system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16530500 # number of overall MSHR miss cycles
520system.cpu.icache.overall_mshr_miss_latency::total 16530500 # number of overall MSHR miss cycles
521system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060748 # mshr miss rate for ReadReq accesses
522system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060748 # mshr miss rate for ReadReq accesses
523system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060748 # mshr miss rate for demand accesses
524system.cpu.icache.demand_mshr_miss_rate::total 0.060748 # mshr miss rate for demand accesses
525system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060748 # mshr miss rate for overall accesses
526system.cpu.icache.overall_mshr_miss_rate::total 0.060748 # mshr miss rate for overall accesses
527system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48906.804734 # average ReadReq mshr miss latency
528system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48906.804734 # average ReadReq mshr miss latency
529system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48906.804734 # average overall mshr miss latency
530system.cpu.icache.demand_avg_mshr_miss_latency::total 48906.804734 # average overall mshr miss latency
531system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48906.804734 # average overall mshr miss latency
532system.cpu.icache.overall_avg_mshr_miss_latency::total 48906.804734 # average overall mshr miss latency

533system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
534system.cpu.dcache.replacements 0 # number of replacements

535system.cpu.dcache.tagsinuse 102.726852 # Cycle average of tags in use
536system.cpu.dcache.total_refs 4058 # Total number of references to valid blocks.
537system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
538system.cpu.dcache.avg_refs 27.794521 # Average number of references to valid blocks.

535system.cpu.dcache.tagsinuse 100.624732 # Cycle average of tags in use
536system.cpu.dcache.total_refs 4052 # Total number of references to valid blocks.
537system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks.
538system.cpu.dcache.avg_refs 27.944828 # Average number of references to valid blocks.

539system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

540system.cpu.dcache.occ_blocks::cpu.data 102.726852 # Average occupied blocks per requestor
541system.cpu.dcache.occ_percent::cpu.data 0.025080 # Average percentage of cache occupancy
542system.cpu.dcache.occ_percent::total 0.025080 # Average percentage of cache occupancy
543system.cpu.dcache.ReadReq_hits::cpu.data 3017 # number of ReadReq hits
544system.cpu.dcache.ReadReq_hits::total 3017 # number of ReadReq hits
545system.cpu.dcache.WriteReq_hits::cpu.data 1035 # number of WriteReq hits
546system.cpu.dcache.WriteReq_hits::total 1035 # number of WriteReq hits

540system.cpu.dcache.occ_blocks::cpu.data 100.624732 # Average occupied blocks per requestor
541system.cpu.dcache.occ_percent::cpu.data 0.024567 # Average percentage of cache occupancy
542system.cpu.dcache.occ_percent::total 0.024567 # Average percentage of cache occupancy
543system.cpu.dcache.ReadReq_hits::cpu.data 3013 # number of ReadReq hits
544system.cpu.dcache.ReadReq_hits::total 3013 # number of ReadReq hits
545system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
546system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits

547system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
548system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits

549system.cpu.dcache.demand_hits::cpu.data 4052 # number of demand (read+write) hits
550system.cpu.dcache.demand_hits::total 4052 # number of demand (read+write) hits
551system.cpu.dcache.overall_hits::cpu.data 4052 # number of overall hits
552system.cpu.dcache.overall_hits::total 4052 # number of overall hits
553system.cpu.dcache.ReadReq_misses::cpu.data 128 # number of ReadReq misses
554system.cpu.dcache.ReadReq_misses::total 128 # number of ReadReq misses
555system.cpu.dcache.WriteReq_misses::cpu.data 407 # number of WriteReq misses
556system.cpu.dcache.WriteReq_misses::total 407 # number of WriteReq misses
557system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses
558system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses
559system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses
560system.cpu.dcache.overall_misses::total 535 # number of overall misses
561system.cpu.dcache.ReadReq_miss_latency::cpu.data 5512500 # number of ReadReq miss cycles
562system.cpu.dcache.ReadReq_miss_latency::total 5512500 # number of ReadReq miss cycles
563system.cpu.dcache.WriteReq_miss_latency::cpu.data 14390000 # number of WriteReq miss cycles
564system.cpu.dcache.WriteReq_miss_latency::total 14390000 # number of WriteReq miss cycles
565system.cpu.dcache.demand_miss_latency::cpu.data 19902500 # number of demand (read+write) miss cycles
566system.cpu.dcache.demand_miss_latency::total 19902500 # number of demand (read+write) miss cycles
567system.cpu.dcache.overall_miss_latency::cpu.data 19902500 # number of overall miss cycles
568system.cpu.dcache.overall_miss_latency::total 19902500 # number of overall miss cycles
569system.cpu.dcache.ReadReq_accesses::cpu.data 3145 # number of ReadReq accesses(hits+misses)
570system.cpu.dcache.ReadReq_accesses::total 3145 # number of ReadReq accesses(hits+misses)

549system.cpu.dcache.demand_hits::cpu.data 4046 # number of demand (read+write) hits
550system.cpu.dcache.demand_hits::total 4046 # number of demand (read+write) hits
551system.cpu.dcache.overall_hits::cpu.data 4046 # number of overall hits
552system.cpu.dcache.overall_hits::total 4046 # number of overall hits
553system.cpu.dcache.ReadReq_misses::cpu.data 129 # number of ReadReq misses
554system.cpu.dcache.ReadReq_misses::total 129 # number of ReadReq misses
555system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
556system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
557system.cpu.dcache.demand_misses::cpu.data 538 # number of demand (read+write) misses
558system.cpu.dcache.demand_misses::total 538 # number of demand (read+write) misses
559system.cpu.dcache.overall_misses::cpu.data 538 # number of overall misses
560system.cpu.dcache.overall_misses::total 538 # number of overall misses
561system.cpu.dcache.ReadReq_miss_latency::cpu.data 6836500 # number of ReadReq miss cycles
562system.cpu.dcache.ReadReq_miss_latency::total 6836500 # number of ReadReq miss cycles
563system.cpu.dcache.WriteReq_miss_latency::cpu.data 19507474 # number of WriteReq miss cycles
564system.cpu.dcache.WriteReq_miss_latency::total 19507474 # number of WriteReq miss cycles
565system.cpu.dcache.demand_miss_latency::cpu.data 26343974 # number of demand (read+write) miss cycles
566system.cpu.dcache.demand_miss_latency::total 26343974 # number of demand (read+write) miss cycles
567system.cpu.dcache.overall_miss_latency::cpu.data 26343974 # number of overall miss cycles
568system.cpu.dcache.overall_miss_latency::total 26343974 # number of overall miss cycles
569system.cpu.dcache.ReadReq_accesses::cpu.data 3142 # number of ReadReq accesses(hits+misses)
570system.cpu.dcache.ReadReq_accesses::total 3142 # number of ReadReq accesses(hits+misses)

571system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
572system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
573system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
574system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)

575system.cpu.dcache.demand_accesses::cpu.data 4587 # number of demand (read+write) accesses
576system.cpu.dcache.demand_accesses::total 4587 # number of demand (read+write) accesses
577system.cpu.dcache.overall_accesses::cpu.data 4587 # number of overall (read+write) accesses
578system.cpu.dcache.overall_accesses::total 4587 # number of overall (read+write) accesses
579system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040700 # miss rate for ReadReq accesses
580system.cpu.dcache.ReadReq_miss_rate::total 0.040700 # miss rate for ReadReq accesses
581system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282247 # miss rate for WriteReq accesses
582system.cpu.dcache.WriteReq_miss_rate::total 0.282247 # miss rate for WriteReq accesses
583system.cpu.dcache.demand_miss_rate::cpu.data 0.116634 # miss rate for demand accesses
584system.cpu.dcache.demand_miss_rate::total 0.116634 # miss rate for demand accesses
585system.cpu.dcache.overall_miss_rate::cpu.data 0.116634 # miss rate for overall accesses
586system.cpu.dcache.overall_miss_rate::total 0.116634 # miss rate for overall accesses
587system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43066.406250 # average ReadReq miss latency
588system.cpu.dcache.ReadReq_avg_miss_latency::total 43066.406250 # average ReadReq miss latency
589system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35356.265356 # average WriteReq miss latency
590system.cpu.dcache.WriteReq_avg_miss_latency::total 35356.265356 # average WriteReq miss latency
591system.cpu.dcache.demand_avg_miss_latency::cpu.data 37200.934579 # average overall miss latency
592system.cpu.dcache.demand_avg_miss_latency::total 37200.934579 # average overall miss latency
593system.cpu.dcache.overall_avg_miss_latency::cpu.data 37200.934579 # average overall miss latency
594system.cpu.dcache.overall_avg_miss_latency::total 37200.934579 # average overall miss latency
595system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked

575system.cpu.dcache.demand_accesses::cpu.data 4584 # number of demand (read+write) accesses
576system.cpu.dcache.demand_accesses::total 4584 # number of demand (read+write) accesses
577system.cpu.dcache.overall_accesses::cpu.data 4584 # number of overall (read+write) accesses
578system.cpu.dcache.overall_accesses::total 4584 # number of overall (read+write) accesses
579system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041057 # miss rate for ReadReq accesses
580system.cpu.dcache.ReadReq_miss_rate::total 0.041057 # miss rate for ReadReq accesses
581system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
582system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
583system.cpu.dcache.demand_miss_rate::cpu.data 0.117365 # miss rate for demand accesses
584system.cpu.dcache.demand_miss_rate::total 0.117365 # miss rate for demand accesses
585system.cpu.dcache.overall_miss_rate::cpu.data 0.117365 # miss rate for overall accesses
586system.cpu.dcache.overall_miss_rate::total 0.117365 # miss rate for overall accesses
587system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52996.124031 # average ReadReq miss latency
588system.cpu.dcache.ReadReq_avg_miss_latency::total 52996.124031 # average ReadReq miss latency
589system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47695.535452 # average WriteReq miss latency
590system.cpu.dcache.WriteReq_avg_miss_latency::total 47695.535452 # average WriteReq miss latency
591system.cpu.dcache.demand_avg_miss_latency::cpu.data 48966.494424 # average overall miss latency
592system.cpu.dcache.demand_avg_miss_latency::total 48966.494424 # average overall miss latency
593system.cpu.dcache.overall_avg_miss_latency::cpu.data 48966.494424 # average overall miss latency
594system.cpu.dcache.overall_avg_miss_latency::total 48966.494424 # average overall miss latency
595system.cpu.dcache.blocked_cycles::no_mshrs 427 # number of cycles access was blocked

596system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked

597system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked

597system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked

598system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked

599system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked

599system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.724138 # average number of cycles each access was blocked

600system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
601system.cpu.dcache.fast_writes 0 # number of fast writes performed
602system.cpu.dcache.cache_copies 0 # number of cache copies performed

603system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits
604system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits
605system.cpu.dcache.WriteReq_mshr_hits::cpu.data 324 # number of WriteReq MSHR hits
606system.cpu.dcache.WriteReq_mshr_hits::total 324 # number of WriteReq MSHR hits
607system.cpu.dcache.demand_mshr_hits::cpu.data 389 # number of demand (read+write) MSHR hits
608system.cpu.dcache.demand_mshr_hits::total 389 # number of demand (read+write) MSHR hits
609system.cpu.dcache.overall_mshr_hits::cpu.data 389 # number of overall MSHR hits
610system.cpu.dcache.overall_mshr_hits::total 389 # number of overall MSHR hits

603system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits
604system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
605system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
606system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
607system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits
608system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits
609system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits
610system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits

611system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
612system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses
613system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
614system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
615system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
616system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
617system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
618system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses

619system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3018500 # number of ReadReq MSHR miss cycles
620system.cpu.dcache.ReadReq_mshr_miss_latency::total 3018500 # number of ReadReq MSHR miss cycles
621system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3172000 # number of WriteReq MSHR miss cycles
622system.cpu.dcache.WriteReq_mshr_miss_latency::total 3172000 # number of WriteReq MSHR miss cycles
623system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6190500 # number of demand (read+write) MSHR miss cycles
624system.cpu.dcache.demand_mshr_miss_latency::total 6190500 # number of demand (read+write) MSHR miss cycles
625system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6190500 # number of overall MSHR miss cycles
626system.cpu.dcache.overall_mshr_miss_latency::total 6190500 # number of overall MSHR miss cycles
627system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020032 # mshr miss rate for ReadReq accesses
628system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020032 # mshr miss rate for ReadReq accesses

619system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3776500 # number of ReadReq MSHR miss cycles
620system.cpu.dcache.ReadReq_mshr_miss_latency::total 3776500 # number of ReadReq MSHR miss cycles
621system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4497000 # number of WriteReq MSHR miss cycles
622system.cpu.dcache.WriteReq_mshr_miss_latency::total 4497000 # number of WriteReq MSHR miss cycles
623system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8273500 # number of demand (read+write) MSHR miss cycles
624system.cpu.dcache.demand_mshr_miss_latency::total 8273500 # number of demand (read+write) MSHR miss cycles
625system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8273500 # number of overall MSHR miss cycles
626system.cpu.dcache.overall_mshr_miss_latency::total 8273500 # number of overall MSHR miss cycles
627system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020051 # mshr miss rate for ReadReq accesses
628system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020051 # mshr miss rate for ReadReq accesses

629system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
630system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses

631system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031829 # mshr miss rate for demand accesses
632system.cpu.dcache.demand_mshr_miss_rate::total 0.031829 # mshr miss rate for demand accesses
633system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031829 # mshr miss rate for overall accesses
634system.cpu.dcache.overall_mshr_miss_rate::total 0.031829 # mshr miss rate for overall accesses
635system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47912.698413 # average ReadReq mshr miss latency
636system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47912.698413 # average ReadReq mshr miss latency
637system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38216.867470 # average WriteReq mshr miss latency
638system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38216.867470 # average WriteReq mshr miss latency
639system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42400.684932 # average overall mshr miss latency
640system.cpu.dcache.demand_avg_mshr_miss_latency::total 42400.684932 # average overall mshr miss latency
641system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42400.684932 # average overall mshr miss latency
642system.cpu.dcache.overall_avg_mshr_miss_latency::total 42400.684932 # average overall mshr miss latency

631system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031850 # mshr miss rate for demand accesses
632system.cpu.dcache.demand_mshr_miss_rate::total 0.031850 # mshr miss rate for demand accesses
633system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031850 # mshr miss rate for overall accesses
634system.cpu.dcache.overall_mshr_miss_rate::total 0.031850 # mshr miss rate for overall accesses
635system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59944.444444 # average ReadReq mshr miss latency
636system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59944.444444 # average ReadReq mshr miss latency
637system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54180.722892 # average WriteReq mshr miss latency
638system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54180.722892 # average WriteReq mshr miss latency
639system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56667.808219 # average overall mshr miss latency
640system.cpu.dcache.demand_avg_mshr_miss_latency::total 56667.808219 # average overall mshr miss latency
641system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56667.808219 # average overall mshr miss latency
642system.cpu.dcache.overall_avg_mshr_miss_latency::total 56667.808219 # average overall mshr miss latency

643system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
644system.cpu.l2cache.replacements 0 # number of replacements

645system.cpu.l2cache.tagsinuse 236.256243 # Cycle average of tags in use

645system.cpu.l2cache.tagsinuse 229.081422 # Cycle average of tags in use

646system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.

647system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
648system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks.

647system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks.
648system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks.

649system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

650system.cpu.l2cache.occ_blocks::cpu.inst 200.252174 # Average occupied blocks per requestor
651system.cpu.l2cache.occ_blocks::cpu.data 36.004069 # Average occupied blocks per requestor
652system.cpu.l2cache.occ_percent::cpu.inst 0.006111 # Average percentage of cache occupancy
653system.cpu.l2cache.occ_percent::cpu.data 0.001099 # Average percentage of cache occupancy
654system.cpu.l2cache.occ_percent::total 0.007210 # Average percentage of cache occupancy

650system.cpu.l2cache.occ_blocks::cpu.inst 193.844447 # Average occupied blocks per requestor
651system.cpu.l2cache.occ_blocks::cpu.data 35.236975 # Average occupied blocks per requestor
652system.cpu.l2cache.occ_percent::cpu.inst 0.005916 # Average percentage of cache occupancy
653system.cpu.l2cache.occ_percent::cpu.data 0.001075 # Average percentage of cache occupancy
654system.cpu.l2cache.occ_percent::total 0.006991 # Average percentage of cache occupancy

655system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
656system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
657system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
658system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
659system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
660system.cpu.l2cache.overall_hits::total 2 # number of overall hits

661system.cpu.l2cache.ReadReq_misses::cpu.inst 337 # number of ReadReq misses

661system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses

662system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses

663system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses

663system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses

664system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
665system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses

666system.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses

666system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses

667system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses

668system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses
669system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses

668system.cpu.l2cache.demand_misses::total 482 # number of demand (read+write) misses
669system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses

670system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses

671system.cpu.l2cache.overall_misses::total 483 # number of overall misses
672system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10715500 # number of ReadReq miss cycles
673system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2955000 # number of ReadReq miss cycles
674system.cpu.l2cache.ReadReq_miss_latency::total 13670500 # number of ReadReq miss cycles
675system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3088000 # number of ReadExReq miss cycles
676system.cpu.l2cache.ReadExReq_miss_latency::total 3088000 # number of ReadExReq miss cycles
677system.cpu.l2cache.demand_miss_latency::cpu.inst 10715500 # number of demand (read+write) miss cycles
678system.cpu.l2cache.demand_miss_latency::cpu.data 6043000 # number of demand (read+write) miss cycles
679system.cpu.l2cache.demand_miss_latency::total 16758500 # number of demand (read+write) miss cycles
680system.cpu.l2cache.overall_miss_latency::cpu.inst 10715500 # number of overall miss cycles
681system.cpu.l2cache.overall_miss_latency::cpu.data 6043000 # number of overall miss cycles
682system.cpu.l2cache.overall_miss_latency::total 16758500 # number of overall miss cycles
683system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses)

671system.cpu.l2cache.overall_misses::total 482 # number of overall misses
672system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16172000 # number of ReadReq miss cycles
673system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3755000 # number of ReadReq miss cycles
674system.cpu.l2cache.ReadReq_miss_latency::total 19927000 # number of ReadReq miss cycles
675system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4413000 # number of ReadExReq miss cycles
676system.cpu.l2cache.ReadExReq_miss_latency::total 4413000 # number of ReadExReq miss cycles
677system.cpu.l2cache.demand_miss_latency::cpu.inst 16172000 # number of demand (read+write) miss cycles
678system.cpu.l2cache.demand_miss_latency::cpu.data 8168000 # number of demand (read+write) miss cycles
679system.cpu.l2cache.demand_miss_latency::total 24340000 # number of demand (read+write) miss cycles
680system.cpu.l2cache.overall_miss_latency::cpu.inst 16172000 # number of overall miss cycles
681system.cpu.l2cache.overall_miss_latency::cpu.data 8168000 # number of overall miss cycles
682system.cpu.l2cache.overall_miss_latency::total 24340000 # number of overall miss cycles
683system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)

684system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses)

685system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses)

685system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses)

686system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
687system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)

688system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses

688system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses

689system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses

690system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses
691system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses

690system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses
691system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses

692system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses

693system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses
694system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994100 # miss rate for ReadReq accesses

693system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses
694system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994083 # miss rate for ReadReq accesses

695system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses

696system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses

696system.cpu.l2cache.ReadReq_miss_rate::total 0.995012 # miss rate for ReadReq accesses

697system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
698system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses

699system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994100 # miss rate for demand accesses

699system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994083 # miss rate for demand accesses

700system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses

701system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses
702system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994100 # miss rate for overall accesses

701system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses
702system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses

703system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses

704system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses
705system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31796.735905 # average ReadReq miss latency
706system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 46904.761905 # average ReadReq miss latency
707system.cpu.l2cache.ReadReq_avg_miss_latency::total 34176.250000 # average ReadReq miss latency
708system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37204.819277 # average ReadExReq miss latency
709system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37204.819277 # average ReadExReq miss latency
710system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31796.735905 # average overall miss latency
711system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41390.410959 # average overall miss latency
712system.cpu.l2cache.demand_avg_miss_latency::total 34696.687371 # average overall miss latency
713system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31796.735905 # average overall miss latency
714system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41390.410959 # average overall miss latency
715system.cpu.l2cache.overall_avg_miss_latency::total 34696.687371 # average overall miss latency

704system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses
705system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48130.952381 # average ReadReq miss latency
706system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59603.174603 # average ReadReq miss latency
707system.cpu.l2cache.ReadReq_avg_miss_latency::total 49942.355890 # average ReadReq miss latency
708system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53168.674699 # average ReadExReq miss latency
709system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53168.674699 # average ReadExReq miss latency
710system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48130.952381 # average overall miss latency
711system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55945.205479 # average overall miss latency
712system.cpu.l2cache.demand_avg_miss_latency::total 50497.925311 # average overall miss latency
713system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48130.952381 # average overall miss latency
714system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55945.205479 # average overall miss latency
715system.cpu.l2cache.overall_avg_miss_latency::total 50497.925311 # average overall miss latency

716system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
717system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
718system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
719system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
720system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
721system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
722system.cpu.l2cache.fast_writes 0 # number of fast writes performed
723system.cpu.l2cache.cache_copies 0 # number of cache copies performed

724system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses

724system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses

725system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses

726system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses

726system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses

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728system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses

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