Cross Reference: /gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000020 # Number of seconds simulated

4sim_ticks 19806500 # Number of ticks simulated
5final_tick 19806500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 20274500 # Number of ticks simulated
5final_tick 20274500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 96556 # Simulator instruction rate (inst/s)
8host_op_rate 96545 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 132327745 # Simulator tick rate (ticks/s)
10host_mem_usage 221008 # Number of bytes of host memory used
11host_seconds 0.15 # Real time elapsed on the host

7host_inst_rate 55162 # Simulator instruction rate (inst/s)
8host_op_rate 55159 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 77392529 # Simulator tick rate (ticks/s)
10host_mem_usage 220968 # Number of bytes of host memory used
11host_seconds 0.26 # Real time elapsed on the host

12sim_insts 14449 # Number of instructions simulated
13sim_ops 14449 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory

14system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory

15system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory

16system.physmem.bytes_read::total 30976 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory

16system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory

20system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory

21system.physmem.num_reads::total 484 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1092166713 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 471764320 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1563931033 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1092166713 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1092166713 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1092166713 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 471764320 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1563931033 # Total bandwidth to/from this memory (bytes/s)

21system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1063799354 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 460874498 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1524673851 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1063799354 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1063799354 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1063799354 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 460874498 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1524673851 # Total bandwidth to/from this memory (bytes/s)

30system.cpu.workload.num_syscalls 18 # Number of system calls

31system.cpu.numCycles 39614 # number of cpu cycles simulated

31system.cpu.numCycles 40550 # number of cpu cycles simulated

32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

34system.cpu.BPredUnit.lookups 6890 # Number of BP lookups
35system.cpu.BPredUnit.condPredicted 4576 # Number of conditional branches predicted
36system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect
37system.cpu.BPredUnit.BTBLookups 5201 # Number of BTB lookups
38system.cpu.BPredUnit.BTBHits 2595 # Number of BTB hits

34system.cpu.BPredUnit.lookups 6892 # Number of BP lookups
35system.cpu.BPredUnit.condPredicted 4586 # Number of conditional branches predicted
36system.cpu.BPredUnit.condIncorrect 1120 # Number of conditional branches incorrect
37system.cpu.BPredUnit.BTBLookups 5125 # Number of BTB lookups
38system.cpu.BPredUnit.BTBHits 2600 # Number of BTB hits

39system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

40system.cpu.BPredUnit.usedRAS 459 # Number of times the RAS was used to get a target.

40system.cpu.BPredUnit.usedRAS 458 # Number of times the RAS was used to get a target.

41system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.

42system.cpu.fetch.icacheStallCycles 11869 # Number of cycles fetch is stalled on an Icache miss
43system.cpu.fetch.Insts 32300 # Number of instructions fetch has processed
44system.cpu.fetch.Branches 6890 # Number of branches that fetch encountered
45system.cpu.fetch.predictedBranches 3054 # Number of branches that fetch has predicted taken
46system.cpu.fetch.Cycles 9560 # Number of cycles fetch has run and was not squashing or blocked
47system.cpu.fetch.SquashCycles 3188 # Number of cycles fetch has spent squashing
48system.cpu.fetch.BlockedCycles 6935 # Number of cycles fetch has spent blocked

42system.cpu.fetch.icacheStallCycles 12259 # Number of cycles fetch is stalled on an Icache miss
43system.cpu.fetch.Insts 32259 # Number of instructions fetch has processed
44system.cpu.fetch.Branches 6892 # Number of branches that fetch encountered
45system.cpu.fetch.predictedBranches 3058 # Number of branches that fetch has predicted taken
46system.cpu.fetch.Cycles 9557 # Number of cycles fetch has run and was not squashing or blocked
47system.cpu.fetch.SquashCycles 3181 # Number of cycles fetch has spent squashing
48system.cpu.fetch.BlockedCycles 7365 # Number of cycles fetch has spent blocked

49system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

50system.cpu.fetch.PendingTrapStallCycles 726 # Number of stall cycles due to pending traps
51system.cpu.fetch.CacheLines 5516 # Number of cache lines fetched
52system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed
53system.cpu.fetch.rateDist::samples 31065 # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::mean 1.039755 # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::stdev 2.210803 # Number of instructions fetched each cycle (Total)

50system.cpu.fetch.PendingTrapStallCycles 767 # Number of stall cycles due to pending traps
51system.cpu.fetch.CacheLines 5500 # Number of cache lines fetched
52system.cpu.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed
53system.cpu.fetch.rateDist::samples 31917 # Number of instructions fetched each cycle (Total)
54system.cpu.fetch.rateDist::mean 1.010715 # Number of instructions fetched each cycle (Total)
55system.cpu.fetch.rateDist::stdev 2.185460 # Number of instructions fetched each cycle (Total)

56system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

57system.cpu.fetch.rateDist::0 21505 69.23% 69.23% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::1 4746 15.28% 84.50% # Number of instructions fetched each cycle (Total)
59system.cpu.fetch.rateDist::2 494 1.59% 86.09% # Number of instructions fetched each cycle (Total)
60system.cpu.fetch.rateDist::3 444 1.43% 87.52% # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::4 682 2.20% 89.72% # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::5 763 2.46% 92.17% # Number of instructions fetched each cycle (Total)
63system.cpu.fetch.rateDist::6 240 0.77% 92.95% # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.rateDist::7 277 0.89% 93.84% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::8 1914 6.16% 100.00% # Number of instructions fetched each cycle (Total)

57system.cpu.fetch.rateDist::0 22360 70.06% 70.06% # Number of instructions fetched each cycle (Total)
58system.cpu.fetch.rateDist::1 4750 14.88% 84.94% # Number of instructions fetched each cycle (Total)
59system.cpu.fetch.rateDist::2 493 1.54% 86.48% # Number of instructions fetched each cycle (Total)
60system.cpu.fetch.rateDist::3 436 1.37% 87.85% # Number of instructions fetched each cycle (Total)
61system.cpu.fetch.rateDist::4 686 2.15% 90.00% # Number of instructions fetched each cycle (Total)
62system.cpu.fetch.rateDist::5 773 2.42% 92.42% # Number of instructions fetched each cycle (Total)
63system.cpu.fetch.rateDist::6 235 0.74% 93.16% # Number of instructions fetched each cycle (Total)
64system.cpu.fetch.rateDist::7 276 0.86% 94.02% # Number of instructions fetched each cycle (Total)
65system.cpu.fetch.rateDist::8 1908 5.98% 100.00% # Number of instructions fetched each cycle (Total)

66system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
67system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
68system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

69system.cpu.fetch.rateDist::total 31065 # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.branchRate 0.173928 # Number of branch fetches per cycle
71system.cpu.fetch.rate 0.815368 # Number of inst fetches per cycle
72system.cpu.decode.IdleCycles 12513 # Number of cycles decode is idle
73system.cpu.decode.BlockedCycles 7669 # Number of cycles decode is blocked
74system.cpu.decode.RunCycles 8722 # Number of cycles decode is running
75system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking
76system.cpu.decode.SquashCycles 1971 # Number of cycles decode is squashing
77system.cpu.decode.DecodedInsts 30088 # Number of instructions handled by decode
78system.cpu.rename.SquashCycles 1971 # Number of cycles rename is squashing
79system.cpu.rename.IdleCycles 13189 # Number of cycles rename is idle
80system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking
81system.cpu.rename.serializeStallCycles 6922 # count of cycles rename stalled for serializing inst
82system.cpu.rename.RunCycles 8283 # Number of cycles rename is running
83system.cpu.rename.UnblockCycles 452 # Number of cycles rename is unblocking
84system.cpu.rename.RenamedInsts 27408 # Number of instructions processed by rename
85system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full
86system.cpu.rename.LSQFullEvents 125 # Number of times rename has blocked due to LSQ full
87system.cpu.rename.RenamedOperands 24445 # Number of destination operands rename has renamed
88system.cpu.rename.RenameLookups 50953 # Number of register rename lookups that rename has made
89system.cpu.rename.int_rename_lookups 50953 # Number of integer rename lookups

69system.cpu.fetch.rateDist::total 31917 # Number of instructions fetched each cycle (Total)
70system.cpu.fetch.branchRate 0.169963 # Number of branch fetches per cycle
71system.cpu.fetch.rate 0.795536 # Number of inst fetches per cycle
72system.cpu.decode.IdleCycles 12903 # Number of cycles decode is idle
73system.cpu.decode.BlockedCycles 8133 # Number of cycles decode is blocked
74system.cpu.decode.RunCycles 8719 # Number of cycles decode is running
75system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking
76system.cpu.decode.SquashCycles 1965 # Number of cycles decode is squashing
77system.cpu.decode.DecodedInsts 30080 # Number of instructions handled by decode
78system.cpu.rename.SquashCycles 1965 # Number of cycles rename is squashing
79system.cpu.rename.IdleCycles 13582 # Number of cycles rename is idle
80system.cpu.rename.BlockCycles 285 # Number of cycles rename is blocking
81system.cpu.rename.serializeStallCycles 7298 # count of cycles rename stalled for serializing inst
82system.cpu.rename.RunCycles 8277 # Number of cycles rename is running
83system.cpu.rename.UnblockCycles 510 # Number of cycles rename is unblocking
84system.cpu.rename.RenamedInsts 27385 # Number of instructions processed by rename
85system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
86system.cpu.rename.LSQFullEvents 172 # Number of times rename has blocked due to LSQ full
87system.cpu.rename.RenamedOperands 24421 # Number of destination operands rename has renamed
88system.cpu.rename.RenameLookups 50913 # Number of register rename lookups that rename has made
89system.cpu.rename.int_rename_lookups 50913 # Number of integer rename lookups

90system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed

91system.cpu.rename.UndoneMaps 10613 # Number of HB maps that are undone due to squashing
92system.cpu.rename.serializingInsts 705 # count of serializing insts renamed
93system.cpu.rename.tempSerializingInsts 708 # count of temporary serializing insts renamed
94system.cpu.rename.skidInsts 2841 # count of insts added to the skid buffer
95system.cpu.memDep0.insertedLoads 3647 # Number of loads inserted to the mem dependence unit.
96system.cpu.memDep0.insertedStores 2469 # Number of stores inserted to the mem dependence unit.

91system.cpu.rename.UndoneMaps 10589 # Number of HB maps that are undone due to squashing
92system.cpu.rename.serializingInsts 704 # count of serializing insts renamed
93system.cpu.rename.tempSerializingInsts 706 # count of temporary serializing insts renamed
94system.cpu.rename.skidInsts 2903 # count of insts added to the skid buffer
95system.cpu.memDep0.insertedLoads 3640 # Number of loads inserted to the mem dependence unit.
96system.cpu.memDep0.insertedStores 2472 # Number of stores inserted to the mem dependence unit.

97system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
98system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.

99system.cpu.iq.iqInstsAdded 23180 # Number of instructions added to the IQ (excludes non-spec)
100system.cpu.iq.iqNonSpecInstsAdded 670 # Number of non-speculative instructions added to the IQ
101system.cpu.iq.iqInstsIssued 21761 # Number of instructions issued
102system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued
103system.cpu.iq.iqSquashedInstsExamined 8457 # Number of squashed instructions iterated over during squash; mainly for profiling
104system.cpu.iq.iqSquashedOperandsExamined 5919 # Number of squashed operands that are examined and possibly removed from graph
105system.cpu.iq.iqSquashedNonSpecRemoved 195 # Number of squashed non-spec instructions that were removed
106system.cpu.iq.issued_per_cycle::samples 31065 # Number of insts issued each cycle
107system.cpu.iq.issued_per_cycle::mean 0.700499 # Number of insts issued each cycle
108system.cpu.iq.issued_per_cycle::stdev 1.316624 # Number of insts issued each cycle

99system.cpu.iq.iqInstsAdded 23148 # Number of instructions added to the IQ (excludes non-spec)
100system.cpu.iq.iqNonSpecInstsAdded 669 # Number of non-speculative instructions added to the IQ
101system.cpu.iq.iqInstsIssued 21730 # Number of instructions issued
102system.cpu.iq.iqSquashedInstsIssued 108 # Number of squashed instructions issued
103system.cpu.iq.iqSquashedInstsExamined 8364 # Number of squashed instructions iterated over during squash; mainly for profiling
104system.cpu.iq.iqSquashedOperandsExamined 5915 # Number of squashed operands that are examined and possibly removed from graph
105system.cpu.iq.iqSquashedNonSpecRemoved 194 # Number of squashed non-spec instructions that were removed
106system.cpu.iq.issued_per_cycle::samples 31917 # Number of insts issued each cycle
107system.cpu.iq.issued_per_cycle::mean 0.680828 # Number of insts issued each cycle
108system.cpu.iq.issued_per_cycle::stdev 1.297413 # Number of insts issued each cycle

109system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

110system.cpu.iq.issued_per_cycle::0 21619 69.59% 69.59% # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::1 3603 11.60% 81.19% # Number of insts issued each cycle
112system.cpu.iq.issued_per_cycle::2 2384 7.67% 88.87% # Number of insts issued each cycle
113system.cpu.iq.issued_per_cycle::3 1730 5.57% 94.43% # Number of insts issued each cycle
114system.cpu.iq.issued_per_cycle::4 898 2.89% 97.32% # Number of insts issued each cycle
115system.cpu.iq.issued_per_cycle::5 488 1.57% 98.90% # Number of insts issued each cycle
116system.cpu.iq.issued_per_cycle::6 252 0.81% 99.71% # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::7 72 0.23% 99.94% # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle

110system.cpu.iq.issued_per_cycle::0 22417 70.24% 70.24% # Number of insts issued each cycle
111system.cpu.iq.issued_per_cycle::1 3682 11.54% 81.77% # Number of insts issued each cycle
112system.cpu.iq.issued_per_cycle::2 2373 7.43% 89.21% # Number of insts issued each cycle
113system.cpu.iq.issued_per_cycle::3 1722 5.40% 94.60% # Number of insts issued each cycle
114system.cpu.iq.issued_per_cycle::4 904 2.83% 97.43% # Number of insts issued each cycle
115system.cpu.iq.issued_per_cycle::5 493 1.54% 98.98% # Number of insts issued each cycle
116system.cpu.iq.issued_per_cycle::6 244 0.76% 99.74% # Number of insts issued each cycle
117system.cpu.iq.issued_per_cycle::7 65 0.20% 99.95% # Number of insts issued each cycle
118system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle

119system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
120system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
121system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

122system.cpu.iq.issued_per_cycle::total 31065 # Number of insts issued each cycle

122system.cpu.iq.issued_per_cycle::total 31917 # Number of insts issued each cycle

123system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

124system.cpu.iq.fu_full::IntAlu 54 29.19% 29.19% # attempts to use FU when none available
125system.cpu.iq.fu_full::IntMult 0 0.00% 29.19% # attempts to use FU when none available
126system.cpu.iq.fu_full::IntDiv 0 0.00% 29.19% # attempts to use FU when none available
127system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.19% # attempts to use FU when none available
128system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.19% # attempts to use FU when none available
129system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.19% # attempts to use FU when none available
130system.cpu.iq.fu_full::FloatMult 0 0.00% 29.19% # attempts to use FU when none available
131system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.19% # attempts to use FU when none available
132system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.19% # attempts to use FU when none available
133system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.19% # attempts to use FU when none available
134system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.19% # attempts to use FU when none available
135system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.19% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.19% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.19% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.19% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdMult 0 0.00% 29.19% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.19% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdShift 0 0.00% 29.19% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.19% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.19% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.19% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.19% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.19% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.19% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.19% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.19% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.19% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.19% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.19% # attempts to use FU when none available
153system.cpu.iq.fu_full::MemRead 26 14.05% 43.24% # attempts to use FU when none available
154system.cpu.iq.fu_full::MemWrite 105 56.76% 100.00% # attempts to use FU when none available

124system.cpu.iq.fu_full::IntAlu 46 26.59% 26.59% # attempts to use FU when none available
125system.cpu.iq.fu_full::IntMult 0 0.00% 26.59% # attempts to use FU when none available
126system.cpu.iq.fu_full::IntDiv 0 0.00% 26.59% # attempts to use FU when none available
127system.cpu.iq.fu_full::FloatAdd 0 0.00% 26.59% # attempts to use FU when none available
128system.cpu.iq.fu_full::FloatCmp 0 0.00% 26.59% # attempts to use FU when none available
129system.cpu.iq.fu_full::FloatCvt 0 0.00% 26.59% # attempts to use FU when none available
130system.cpu.iq.fu_full::FloatMult 0 0.00% 26.59% # attempts to use FU when none available
131system.cpu.iq.fu_full::FloatDiv 0 0.00% 26.59% # attempts to use FU when none available
132system.cpu.iq.fu_full::FloatSqrt 0 0.00% 26.59% # attempts to use FU when none available
133system.cpu.iq.fu_full::SimdAdd 0 0.00% 26.59% # attempts to use FU when none available
134system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 26.59% # attempts to use FU when none available
135system.cpu.iq.fu_full::SimdAlu 0 0.00% 26.59% # attempts to use FU when none available
136system.cpu.iq.fu_full::SimdCmp 0 0.00% 26.59% # attempts to use FU when none available
137system.cpu.iq.fu_full::SimdCvt 0 0.00% 26.59% # attempts to use FU when none available
138system.cpu.iq.fu_full::SimdMisc 0 0.00% 26.59% # attempts to use FU when none available
139system.cpu.iq.fu_full::SimdMult 0 0.00% 26.59% # attempts to use FU when none available
140system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 26.59% # attempts to use FU when none available
141system.cpu.iq.fu_full::SimdShift 0 0.00% 26.59% # attempts to use FU when none available
142system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 26.59% # attempts to use FU when none available
143system.cpu.iq.fu_full::SimdSqrt 0 0.00% 26.59% # attempts to use FU when none available
144system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 26.59% # attempts to use FU when none available
145system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 26.59% # attempts to use FU when none available
146system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 26.59% # attempts to use FU when none available
147system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 26.59% # attempts to use FU when none available
148system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 26.59% # attempts to use FU when none available
149system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 26.59% # attempts to use FU when none available
150system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 26.59% # attempts to use FU when none available
151system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.59% # attempts to use FU when none available
152system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 26.59% # attempts to use FU when none available
153system.cpu.iq.fu_full::MemRead 24 13.87% 40.46% # attempts to use FU when none available
154system.cpu.iq.fu_full::MemWrite 103 59.54% 100.00% # attempts to use FU when none available

155system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
156system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
157system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

158system.cpu.iq.FU_type_0::IntAlu 16056 73.78% 73.78% # Type of FU issued
159system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.78% # Type of FU issued
160system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.78% # Type of FU issued
161system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.78% # Type of FU issued
162system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.78% # Type of FU issued
163system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.78% # Type of FU issued
164system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.78% # Type of FU issued
165system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.78% # Type of FU issued
166system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.78% # Type of FU issued
167system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.78% # Type of FU issued
168system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.78% # Type of FU issued
169system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.78% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.78% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.78% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.78% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.78% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.78% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.78% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.78% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.78% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.78% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.78% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.78% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.78% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.78% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.78% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.78% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.78% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.78% # Type of FU issued
187system.cpu.iq.FU_type_0::MemRead 3441 15.81% 89.60% # Type of FU issued
188system.cpu.iq.FU_type_0::MemWrite 2264 10.40% 100.00% # Type of FU issued

158system.cpu.iq.FU_type_0::IntAlu 16031 73.77% 73.77% # Type of FU issued
159system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.77% # Type of FU issued
160system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.77% # Type of FU issued
161system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.77% # Type of FU issued
162system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.77% # Type of FU issued
163system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.77% # Type of FU issued
164system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.77% # Type of FU issued
165system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.77% # Type of FU issued
166system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.77% # Type of FU issued
167system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.77% # Type of FU issued
168system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.77% # Type of FU issued
169system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.77% # Type of FU issued
170system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.77% # Type of FU issued
171system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.77% # Type of FU issued
172system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.77% # Type of FU issued
173system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.77% # Type of FU issued
174system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.77% # Type of FU issued
175system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.77% # Type of FU issued
176system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.77% # Type of FU issued
177system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.77% # Type of FU issued
178system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.77% # Type of FU issued
179system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.77% # Type of FU issued
180system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.77% # Type of FU issued
181system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.77% # Type of FU issued
182system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.77% # Type of FU issued
183system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.77% # Type of FU issued
184system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.77% # Type of FU issued
185system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.77% # Type of FU issued
186system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.77% # Type of FU issued
187system.cpu.iq.FU_type_0::MemRead 3433 15.80% 89.57% # Type of FU issued
188system.cpu.iq.FU_type_0::MemWrite 2266 10.43% 100.00% # Type of FU issued

189system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
190system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

191system.cpu.iq.FU_type_0::total 21761 # Type of FU issued
192system.cpu.iq.rate 0.549326 # Inst issue rate
193system.cpu.iq.fu_busy_cnt 185 # FU busy when requested
194system.cpu.iq.fu_busy_rate 0.008501 # FU busy rate (busy events/executed inst)
195system.cpu.iq.int_inst_queue_reads 74877 # Number of integer instruction queue reads
196system.cpu.iq.int_inst_queue_writes 32333 # Number of integer instruction queue writes
197system.cpu.iq.int_inst_queue_wakeup_accesses 19979 # Number of integer instruction queue wakeup accesses

191system.cpu.iq.FU_type_0::total 21730 # Type of FU issued
192system.cpu.iq.rate 0.535882 # Inst issue rate
193system.cpu.iq.fu_busy_cnt 173 # FU busy when requested
194system.cpu.iq.fu_busy_rate 0.007961 # FU busy rate (busy events/executed inst)
195system.cpu.iq.int_inst_queue_reads 75658 # Number of integer instruction queue reads
196system.cpu.iq.int_inst_queue_writes 32207 # Number of integer instruction queue writes
197system.cpu.iq.int_inst_queue_wakeup_accesses 19957 # Number of integer instruction queue wakeup accesses

198system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
199system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
200system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

201system.cpu.iq.int_alu_accesses 21946 # Number of integer alu accesses

201system.cpu.iq.int_alu_accesses 21903 # Number of integer alu accesses

202system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
203system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores
204system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

205system.cpu.iew.lsq.thread0.squashedLoads 1421 # Number of loads squashed

205system.cpu.iew.lsq.thread0.squashedLoads 1414 # Number of loads squashed

206system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
207system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations

208system.cpu.iew.lsq.thread0.squashedStores 1021 # Number of stores squashed

208system.cpu.iew.lsq.thread0.squashedStores 1024 # Number of stores squashed

209system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
210system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
211system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
212system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
213system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

214system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing
215system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking
216system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
217system.cpu.iew.iewDispatchedInsts 25018 # Number of instructions dispatched to IQ
218system.cpu.iew.iewDispSquashedInsts 406 # Number of squashed instructions skipped by dispatch
219system.cpu.iew.iewDispLoadInsts 3647 # Number of dispatched load instructions
220system.cpu.iew.iewDispStoreInsts 2469 # Number of dispatched store instructions
221system.cpu.iew.iewDispNonSpecInsts 670 # Number of dispatched non-speculative instructions
222system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall

214system.cpu.iew.iewSquashCycles 1965 # Number of cycles IEW is squashing
215system.cpu.iew.iewBlockCycles 99 # Number of cycles IEW is blocking
216system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
217system.cpu.iew.iewDispatchedInsts 24982 # Number of instructions dispatched to IQ
218system.cpu.iew.iewDispSquashedInsts 417 # Number of squashed instructions skipped by dispatch
219system.cpu.iew.iewDispLoadInsts 3640 # Number of dispatched load instructions
220system.cpu.iew.iewDispStoreInsts 2472 # Number of dispatched store instructions
221system.cpu.iew.iewDispNonSpecInsts 669 # Number of dispatched non-speculative instructions
222system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall

223system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
224system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
225system.cpu.iew.predictedTakenIncorrect 291 # Number of branches that were predicted taken incorrectly

226system.cpu.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly
227system.cpu.iew.branchMispredicts 1253 # Number of branch mispredicts detected at execute
228system.cpu.iew.iewExecutedInsts 20571 # Number of executed instructions
229system.cpu.iew.iewExecLoadInsts 3278 # Number of load instructions executed
230system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute

226system.cpu.iew.predictedNotTakenIncorrect 958 # Number of branches that were predicted not taken incorrectly
227system.cpu.iew.branchMispredicts 1249 # Number of branch mispredicts detected at execute
228system.cpu.iew.iewExecutedInsts 20553 # Number of executed instructions
229system.cpu.iew.iewExecLoadInsts 3273 # Number of load instructions executed
230system.cpu.iew.iewExecSquashedInsts 1177 # Number of squashed instructions skipped in execute

231system.cpu.iew.exec_swp 0 # number of swp insts executed

232system.cpu.iew.exec_nop 1168 # number of nop insts executed
233system.cpu.iew.exec_refs 5421 # number of memory reference insts executed
234system.cpu.iew.exec_branches 4301 # Number of branches executed
235system.cpu.iew.exec_stores 2143 # Number of stores executed
236system.cpu.iew.exec_rate 0.519286 # Inst execution rate
237system.cpu.iew.wb_sent 20246 # cumulative count of insts sent to commit
238system.cpu.iew.wb_count 19979 # cumulative count of insts written-back
239system.cpu.iew.wb_producers 9281 # num instructions producing a value
240system.cpu.iew.wb_consumers 11411 # num instructions consuming a value

232system.cpu.iew.exec_nop 1165 # number of nop insts executed
233system.cpu.iew.exec_refs 5419 # number of memory reference insts executed
234system.cpu.iew.exec_branches 4294 # Number of branches executed
235system.cpu.iew.exec_stores 2146 # Number of stores executed
236system.cpu.iew.exec_rate 0.506856 # Inst execution rate
237system.cpu.iew.wb_sent 20221 # cumulative count of insts sent to commit
238system.cpu.iew.wb_count 19957 # cumulative count of insts written-back
239system.cpu.iew.wb_producers 9257 # num instructions producing a value
240system.cpu.iew.wb_consumers 11359 # num instructions consuming a value

241system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

242system.cpu.iew.wb_rate 0.504342 # insts written-back per cycle
243system.cpu.iew.wb_fanout 0.813338 # average fanout of values written-back

242system.cpu.iew.wb_rate 0.492158 # insts written-back per cycle
243system.cpu.iew.wb_fanout 0.814948 # average fanout of values written-back

244system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
245system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
246system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions

247system.cpu.commit.commitSquashedInsts 9761 # The number of squashed insts skipped by commit

247system.cpu.commit.commitSquashedInsts 9725 # The number of squashed insts skipped by commit

248system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards

249system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted
250system.cpu.commit.committed_per_cycle::samples 29111 # Number of insts commited each cycle
251system.cpu.commit.committed_per_cycle::mean 0.521281 # Number of insts commited each cycle
252system.cpu.commit.committed_per_cycle::stdev 1.203804 # Number of insts commited each cycle

249system.cpu.commit.branchMispredicts 1120 # The number of times a branch was mispredicted
250system.cpu.commit.committed_per_cycle::samples 29969 # Number of insts commited each cycle
251system.cpu.commit.committed_per_cycle::mean 0.506357 # Number of insts commited each cycle
252system.cpu.commit.committed_per_cycle::stdev 1.189037 # Number of insts commited each cycle

253system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

254system.cpu.commit.committed_per_cycle::0 21721 74.61% 74.61% # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::1 4069 13.98% 88.59% # Number of insts commited each cycle
256system.cpu.commit.committed_per_cycle::2 1444 4.96% 93.55% # Number of insts commited each cycle
257system.cpu.commit.committed_per_cycle::3 793 2.72% 96.28% # Number of insts commited each cycle
258system.cpu.commit.committed_per_cycle::4 337 1.16% 97.43% # Number of insts commited each cycle
259system.cpu.commit.committed_per_cycle::5 258 0.89% 98.32% # Number of insts commited each cycle
260system.cpu.commit.committed_per_cycle::6 320 1.10% 99.42% # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::7 71 0.24% 99.66% # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::8 98 0.34% 100.00% # Number of insts commited each cycle

254system.cpu.commit.committed_per_cycle::0 22543 75.22% 75.22% # Number of insts commited each cycle
255system.cpu.commit.committed_per_cycle::1 4136 13.80% 89.02% # Number of insts commited each cycle
256system.cpu.commit.committed_per_cycle::2 1421 4.74% 93.76% # Number of insts commited each cycle
257system.cpu.commit.committed_per_cycle::3 789 2.63% 96.40% # Number of insts commited each cycle
258system.cpu.commit.committed_per_cycle::4 331 1.10% 97.50% # Number of insts commited each cycle
259system.cpu.commit.committed_per_cycle::5 259 0.86% 98.36% # Number of insts commited each cycle
260system.cpu.commit.committed_per_cycle::6 318 1.06% 99.43% # Number of insts commited each cycle
261system.cpu.commit.committed_per_cycle::7 73 0.24% 99.67% # Number of insts commited each cycle
262system.cpu.commit.committed_per_cycle::8 99 0.33% 100.00% # Number of insts commited each cycle

263system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
264system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
265system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

266system.cpu.commit.committed_per_cycle::total 29111 # Number of insts commited each cycle

266system.cpu.commit.committed_per_cycle::total 29969 # Number of insts commited each cycle

267system.cpu.commit.committedInsts 15175 # Number of instructions committed
268system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed
269system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
270system.cpu.commit.refs 3674 # Number of memory references committed
271system.cpu.commit.loads 2226 # Number of loads committed
272system.cpu.commit.membars 0 # Number of memory barriers committed
273system.cpu.commit.branches 3359 # Number of branches committed
274system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
275system.cpu.commit.int_insts 12186 # Number of committed integer instructions.
276system.cpu.commit.function_calls 187 # Number of function calls committed.

277system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached

277system.cpu.commit.bw_lim_events 99 # number cycles where commit BW limit reached

278system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

279system.cpu.rob.rob_reads 53126 # The number of ROB reads
280system.cpu.rob.rob_writes 51851 # The number of ROB writes
281system.cpu.timesIdled 186 # Number of times that the entire CPU went into an idle state and unscheduled itself
282system.cpu.idleCycles 8549 # Total number of cycles that the CPU has spent unscheduled due to idling

279system.cpu.rob.rob_reads 53947 # The number of ROB reads
280system.cpu.rob.rob_writes 51773 # The number of ROB writes
281system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself
282system.cpu.idleCycles 8633 # Total number of cycles that the CPU has spent unscheduled due to idling

283system.cpu.committedInsts 14449 # Number of Instructions Simulated
284system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated
285system.cpu.committedInsts_total 14449 # Number of Instructions Simulated

286system.cpu.cpi 2.741643 # CPI: Cycles Per Instruction
287system.cpu.cpi_total 2.741643 # CPI: Total CPI of All Threads
288system.cpu.ipc 0.364745 # IPC: Instructions Per Cycle
289system.cpu.ipc_total 0.364745 # IPC: Total IPC of All Threads
290system.cpu.int_regfile_reads 32757 # number of integer regfile reads
291system.cpu.int_regfile_writes 18209 # number of integer regfile writes
292system.cpu.misc_regfile_reads 7073 # number of misc regfile reads

286system.cpu.cpi 2.806423 # CPI: Cycles Per Instruction
287system.cpu.cpi_total 2.806423 # CPI: Total CPI of All Threads
288system.cpu.ipc 0.356326 # IPC: Instructions Per Cycle
289system.cpu.ipc_total 0.356326 # IPC: Total IPC of All Threads
290system.cpu.int_regfile_reads 32739 # number of integer regfile reads
291system.cpu.int_regfile_writes 18191 # number of integer regfile writes
292system.cpu.misc_regfile_reads 7070 # number of misc regfile reads

293system.cpu.misc_regfile_writes 569 # number of misc regfile writes
294system.cpu.icache.replacements 0 # number of replacements

295system.cpu.icache.tagsinuse 201.055469 # Cycle average of tags in use
296system.cpu.icache.total_refs 5034 # Total number of references to valid blocks.
297system.cpu.icache.sampled_refs 340 # Sample count of references to valid blocks.
298system.cpu.icache.avg_refs 14.805882 # Average number of references to valid blocks.

295system.cpu.icache.tagsinuse 199.218311 # Cycle average of tags in use
296system.cpu.icache.total_refs 5020 # Total number of references to valid blocks.
297system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks.
298system.cpu.icache.avg_refs 14.808260 # Average number of references to valid blocks.

299system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

300system.cpu.icache.occ_blocks::cpu.inst 201.055469 # Average occupied blocks per requestor
301system.cpu.icache.occ_percent::cpu.inst 0.098172 # Average percentage of cache occupancy
302system.cpu.icache.occ_percent::total 0.098172 # Average percentage of cache occupancy
303system.cpu.icache.ReadReq_hits::cpu.inst 5034 # number of ReadReq hits
304system.cpu.icache.ReadReq_hits::total 5034 # number of ReadReq hits
305system.cpu.icache.demand_hits::cpu.inst 5034 # number of demand (read+write) hits
306system.cpu.icache.demand_hits::total 5034 # number of demand (read+write) hits
307system.cpu.icache.overall_hits::cpu.inst 5034 # number of overall hits
308system.cpu.icache.overall_hits::total 5034 # number of overall hits
309system.cpu.icache.ReadReq_misses::cpu.inst 482 # number of ReadReq misses
310system.cpu.icache.ReadReq_misses::total 482 # number of ReadReq misses
311system.cpu.icache.demand_misses::cpu.inst 482 # number of demand (read+write) misses
312system.cpu.icache.demand_misses::total 482 # number of demand (read+write) misses
313system.cpu.icache.overall_misses::cpu.inst 482 # number of overall misses
314system.cpu.icache.overall_misses::total 482 # number of overall misses
315system.cpu.icache.ReadReq_miss_latency::cpu.inst 16634500 # number of ReadReq miss cycles
316system.cpu.icache.ReadReq_miss_latency::total 16634500 # number of ReadReq miss cycles
317system.cpu.icache.demand_miss_latency::cpu.inst 16634500 # number of demand (read+write) miss cycles
318system.cpu.icache.demand_miss_latency::total 16634500 # number of demand (read+write) miss cycles
319system.cpu.icache.overall_miss_latency::cpu.inst 16634500 # number of overall miss cycles
320system.cpu.icache.overall_miss_latency::total 16634500 # number of overall miss cycles
321system.cpu.icache.ReadReq_accesses::cpu.inst 5516 # number of ReadReq accesses(hits+misses)
322system.cpu.icache.ReadReq_accesses::total 5516 # number of ReadReq accesses(hits+misses)
323system.cpu.icache.demand_accesses::cpu.inst 5516 # number of demand (read+write) accesses
324system.cpu.icache.demand_accesses::total 5516 # number of demand (read+write) accesses
325system.cpu.icache.overall_accesses::cpu.inst 5516 # number of overall (read+write) accesses
326system.cpu.icache.overall_accesses::total 5516 # number of overall (read+write) accesses
327system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087382 # miss rate for ReadReq accesses
328system.cpu.icache.ReadReq_miss_rate::total 0.087382 # miss rate for ReadReq accesses
329system.cpu.icache.demand_miss_rate::cpu.inst 0.087382 # miss rate for demand accesses
330system.cpu.icache.demand_miss_rate::total 0.087382 # miss rate for demand accesses
331system.cpu.icache.overall_miss_rate::cpu.inst 0.087382 # miss rate for overall accesses
332system.cpu.icache.overall_miss_rate::total 0.087382 # miss rate for overall accesses
333system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34511.410788 # average ReadReq miss latency
334system.cpu.icache.ReadReq_avg_miss_latency::total 34511.410788 # average ReadReq miss latency
335system.cpu.icache.demand_avg_miss_latency::cpu.inst 34511.410788 # average overall miss latency
336system.cpu.icache.demand_avg_miss_latency::total 34511.410788 # average overall miss latency
337system.cpu.icache.overall_avg_miss_latency::cpu.inst 34511.410788 # average overall miss latency
338system.cpu.icache.overall_avg_miss_latency::total 34511.410788 # average overall miss latency

300system.cpu.icache.occ_blocks::cpu.inst 199.218311 # Average occupied blocks per requestor
301system.cpu.icache.occ_percent::cpu.inst 0.097275 # Average percentage of cache occupancy
302system.cpu.icache.occ_percent::total 0.097275 # Average percentage of cache occupancy
303system.cpu.icache.ReadReq_hits::cpu.inst 5020 # number of ReadReq hits
304system.cpu.icache.ReadReq_hits::total 5020 # number of ReadReq hits
305system.cpu.icache.demand_hits::cpu.inst 5020 # number of demand (read+write) hits
306system.cpu.icache.demand_hits::total 5020 # number of demand (read+write) hits
307system.cpu.icache.overall_hits::cpu.inst 5020 # number of overall hits
308system.cpu.icache.overall_hits::total 5020 # number of overall hits
309system.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses
310system.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses
311system.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses
312system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses
313system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses
314system.cpu.icache.overall_misses::total 480 # number of overall misses
315system.cpu.icache.ReadReq_miss_latency::cpu.inst 16877500 # number of ReadReq miss cycles
316system.cpu.icache.ReadReq_miss_latency::total 16877500 # number of ReadReq miss cycles
317system.cpu.icache.demand_miss_latency::cpu.inst 16877500 # number of demand (read+write) miss cycles
318system.cpu.icache.demand_miss_latency::total 16877500 # number of demand (read+write) miss cycles
319system.cpu.icache.overall_miss_latency::cpu.inst 16877500 # number of overall miss cycles
320system.cpu.icache.overall_miss_latency::total 16877500 # number of overall miss cycles
321system.cpu.icache.ReadReq_accesses::cpu.inst 5500 # number of ReadReq accesses(hits+misses)
322system.cpu.icache.ReadReq_accesses::total 5500 # number of ReadReq accesses(hits+misses)
323system.cpu.icache.demand_accesses::cpu.inst 5500 # number of demand (read+write) accesses
324system.cpu.icache.demand_accesses::total 5500 # number of demand (read+write) accesses
325system.cpu.icache.overall_accesses::cpu.inst 5500 # number of overall (read+write) accesses
326system.cpu.icache.overall_accesses::total 5500 # number of overall (read+write) accesses
327system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087273 # miss rate for ReadReq accesses
328system.cpu.icache.ReadReq_miss_rate::total 0.087273 # miss rate for ReadReq accesses
329system.cpu.icache.demand_miss_rate::cpu.inst 0.087273 # miss rate for demand accesses
330system.cpu.icache.demand_miss_rate::total 0.087273 # miss rate for demand accesses
331system.cpu.icache.overall_miss_rate::cpu.inst 0.087273 # miss rate for overall accesses
332system.cpu.icache.overall_miss_rate::total 0.087273 # miss rate for overall accesses
333system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35161.458333 # average ReadReq miss latency
334system.cpu.icache.ReadReq_avg_miss_latency::total 35161.458333 # average ReadReq miss latency
335system.cpu.icache.demand_avg_miss_latency::cpu.inst 35161.458333 # average overall miss latency
336system.cpu.icache.demand_avg_miss_latency::total 35161.458333 # average overall miss latency
337system.cpu.icache.overall_avg_miss_latency::cpu.inst 35161.458333 # average overall miss latency
338system.cpu.icache.overall_avg_miss_latency::total 35161.458333 # average overall miss latency

339system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
340system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
341system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
342system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
343system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
344system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
345system.cpu.icache.fast_writes 0 # number of fast writes performed
346system.cpu.icache.cache_copies 0 # number of cache copies performed

347system.cpu.icache.ReadReq_mshr_hits::cpu.inst 142 # number of ReadReq MSHR hits
348system.cpu.icache.ReadReq_mshr_hits::total 142 # number of ReadReq MSHR hits
349system.cpu.icache.demand_mshr_hits::cpu.inst 142 # number of demand (read+write) MSHR hits
350system.cpu.icache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits
351system.cpu.icache.overall_mshr_hits::cpu.inst 142 # number of overall MSHR hits
352system.cpu.icache.overall_mshr_hits::total 142 # number of overall MSHR hits
353system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses
354system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses
355system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses
356system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses
357system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses
358system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses
359system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11937500 # number of ReadReq MSHR miss cycles
360system.cpu.icache.ReadReq_mshr_miss_latency::total 11937500 # number of ReadReq MSHR miss cycles
361system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 # number of demand (read+write) MSHR miss cycles
362system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles
363system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles
364system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles
365system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for ReadReq accesses
366system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061639 # mshr miss rate for ReadReq accesses
367system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for demand accesses
368system.cpu.icache.demand_mshr_miss_rate::total 0.061639 # mshr miss rate for demand accesses
369system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for overall accesses
370system.cpu.icache.overall_mshr_miss_rate::total 0.061639 # mshr miss rate for overall accesses
371system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency
372system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency
373system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency
374system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency
375system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency
376system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency

347system.cpu.icache.ReadReq_mshr_hits::cpu.inst 141 # number of ReadReq MSHR hits
348system.cpu.icache.ReadReq_mshr_hits::total 141 # number of ReadReq MSHR hits
349system.cpu.icache.demand_mshr_hits::cpu.inst 141 # number of demand (read+write) MSHR hits
350system.cpu.icache.demand_mshr_hits::total 141 # number of demand (read+write) MSHR hits
351system.cpu.icache.overall_mshr_hits::cpu.inst 141 # number of overall MSHR hits
352system.cpu.icache.overall_mshr_hits::total 141 # number of overall MSHR hits
353system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses
354system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses
355system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses
356system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses
357system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses
358system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses
359system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12213000 # number of ReadReq MSHR miss cycles
360system.cpu.icache.ReadReq_mshr_miss_latency::total 12213000 # number of ReadReq MSHR miss cycles
361system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12213000 # number of demand (read+write) MSHR miss cycles
362system.cpu.icache.demand_mshr_miss_latency::total 12213000 # number of demand (read+write) MSHR miss cycles
363system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12213000 # number of overall MSHR miss cycles
364system.cpu.icache.overall_mshr_miss_latency::total 12213000 # number of overall MSHR miss cycles
365system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for ReadReq accesses
366system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061636 # mshr miss rate for ReadReq accesses
367system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for demand accesses
368system.cpu.icache.demand_mshr_miss_rate::total 0.061636 # mshr miss rate for demand accesses
369system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061636 # mshr miss rate for overall accesses
370system.cpu.icache.overall_mshr_miss_rate::total 0.061636 # mshr miss rate for overall accesses
371system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36026.548673 # average ReadReq mshr miss latency
372system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36026.548673 # average ReadReq mshr miss latency
373system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency
374system.cpu.icache.demand_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency
375system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36026.548673 # average overall mshr miss latency
376system.cpu.icache.overall_avg_mshr_miss_latency::total 36026.548673 # average overall mshr miss latency

377system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
378system.cpu.dcache.replacements 0 # number of replacements

379system.cpu.dcache.tagsinuse 103.574586 # Cycle average of tags in use
380system.cpu.dcache.total_refs 4084 # Total number of references to valid blocks.

379system.cpu.dcache.tagsinuse 102.764065 # Cycle average of tags in use
380system.cpu.dcache.total_refs 4075 # Total number of references to valid blocks.

381system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.

382system.cpu.dcache.avg_refs 27.972603 # Average number of references to valid blocks.

382system.cpu.dcache.avg_refs 27.910959 # Average number of references to valid blocks.

383system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

384system.cpu.dcache.occ_blocks::cpu.data 103.574586 # Average occupied blocks per requestor
385system.cpu.dcache.occ_percent::cpu.data 0.025287 # Average percentage of cache occupancy
386system.cpu.dcache.occ_percent::total 0.025287 # Average percentage of cache occupancy
387system.cpu.dcache.ReadReq_hits::cpu.data 3044 # number of ReadReq hits
388system.cpu.dcache.ReadReq_hits::total 3044 # number of ReadReq hits
389system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits
390system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits

384system.cpu.dcache.occ_blocks::cpu.data 102.764065 # Average occupied blocks per requestor
385system.cpu.dcache.occ_percent::cpu.data 0.025089 # Average percentage of cache occupancy
386system.cpu.dcache.occ_percent::total 0.025089 # Average percentage of cache occupancy
387system.cpu.dcache.ReadReq_hits::cpu.data 3036 # number of ReadReq hits
388system.cpu.dcache.ReadReq_hits::total 3036 # number of ReadReq hits
389system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
390system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits

391system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
392system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits

393system.cpu.dcache.demand_hits::cpu.data 4078 # number of demand (read+write) hits
394system.cpu.dcache.demand_hits::total 4078 # number of demand (read+write) hits
395system.cpu.dcache.overall_hits::cpu.data 4078 # number of overall hits
396system.cpu.dcache.overall_hits::total 4078 # number of overall hits
397system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses
398system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses
399system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses
400system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses
401system.cpu.dcache.demand_misses::cpu.data 524 # number of demand (read+write) misses
402system.cpu.dcache.demand_misses::total 524 # number of demand (read+write) misses
403system.cpu.dcache.overall_misses::cpu.data 524 # number of overall misses
404system.cpu.dcache.overall_misses::total 524 # number of overall misses
405system.cpu.dcache.ReadReq_miss_latency::cpu.data 4022000 # number of ReadReq miss cycles
406system.cpu.dcache.ReadReq_miss_latency::total 4022000 # number of ReadReq miss cycles
407system.cpu.dcache.WriteReq_miss_latency::cpu.data 14592500 # number of WriteReq miss cycles
408system.cpu.dcache.WriteReq_miss_latency::total 14592500 # number of WriteReq miss cycles
409system.cpu.dcache.demand_miss_latency::cpu.data 18614500 # number of demand (read+write) miss cycles
410system.cpu.dcache.demand_miss_latency::total 18614500 # number of demand (read+write) miss cycles
411system.cpu.dcache.overall_miss_latency::cpu.data 18614500 # number of overall miss cycles
412system.cpu.dcache.overall_miss_latency::total 18614500 # number of overall miss cycles
413system.cpu.dcache.ReadReq_accesses::cpu.data 3160 # number of ReadReq accesses(hits+misses)
414system.cpu.dcache.ReadReq_accesses::total 3160 # number of ReadReq accesses(hits+misses)

393system.cpu.dcache.demand_hits::cpu.data 4069 # number of demand (read+write) hits
394system.cpu.dcache.demand_hits::total 4069 # number of demand (read+write) hits
395system.cpu.dcache.overall_hits::cpu.data 4069 # number of overall hits
396system.cpu.dcache.overall_hits::total 4069 # number of overall hits
397system.cpu.dcache.ReadReq_misses::cpu.data 121 # number of ReadReq misses
398system.cpu.dcache.ReadReq_misses::total 121 # number of ReadReq misses
399system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
400system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
401system.cpu.dcache.demand_misses::cpu.data 530 # number of demand (read+write) misses
402system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses
403system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses
404system.cpu.dcache.overall_misses::total 530 # number of overall misses
405system.cpu.dcache.ReadReq_miss_latency::cpu.data 4649500 # number of ReadReq miss cycles
406system.cpu.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles
407system.cpu.dcache.WriteReq_miss_latency::cpu.data 17651000 # number of WriteReq miss cycles
408system.cpu.dcache.WriteReq_miss_latency::total 17651000 # number of WriteReq miss cycles
409system.cpu.dcache.demand_miss_latency::cpu.data 22300500 # number of demand (read+write) miss cycles
410system.cpu.dcache.demand_miss_latency::total 22300500 # number of demand (read+write) miss cycles
411system.cpu.dcache.overall_miss_latency::cpu.data 22300500 # number of overall miss cycles
412system.cpu.dcache.overall_miss_latency::total 22300500 # number of overall miss cycles
413system.cpu.dcache.ReadReq_accesses::cpu.data 3157 # number of ReadReq accesses(hits+misses)
414system.cpu.dcache.ReadReq_accesses::total 3157 # number of ReadReq accesses(hits+misses)

415system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
416system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
417system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
418system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)

419system.cpu.dcache.demand_accesses::cpu.data 4602 # number of demand (read+write) accesses
420system.cpu.dcache.demand_accesses::total 4602 # number of demand (read+write) accesses
421system.cpu.dcache.overall_accesses::cpu.data 4602 # number of overall (read+write) accesses
422system.cpu.dcache.overall_accesses::total 4602 # number of overall (read+write) accesses
423system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.036709 # miss rate for ReadReq accesses
424system.cpu.dcache.ReadReq_miss_rate::total 0.036709 # miss rate for ReadReq accesses
425system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses
426system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses
427system.cpu.dcache.demand_miss_rate::cpu.data 0.113864 # miss rate for demand accesses
428system.cpu.dcache.demand_miss_rate::total 0.113864 # miss rate for demand accesses
429system.cpu.dcache.overall_miss_rate::cpu.data 0.113864 # miss rate for overall accesses
430system.cpu.dcache.overall_miss_rate::total 0.113864 # miss rate for overall accesses
431system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34672.413793 # average ReadReq miss latency
432system.cpu.dcache.ReadReq_avg_miss_latency::total 34672.413793 # average ReadReq miss latency
433system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35765.931373 # average WriteReq miss latency
434system.cpu.dcache.WriteReq_avg_miss_latency::total 35765.931373 # average WriteReq miss latency
435system.cpu.dcache.demand_avg_miss_latency::cpu.data 35523.854962 # average overall miss latency
436system.cpu.dcache.demand_avg_miss_latency::total 35523.854962 # average overall miss latency
437system.cpu.dcache.overall_avg_miss_latency::cpu.data 35523.854962 # average overall miss latency
438system.cpu.dcache.overall_avg_miss_latency::total 35523.854962 # average overall miss latency

419system.cpu.dcache.demand_accesses::cpu.data 4599 # number of demand (read+write) accesses
420system.cpu.dcache.demand_accesses::total 4599 # number of demand (read+write) accesses
421system.cpu.dcache.overall_accesses::cpu.data 4599 # number of overall (read+write) accesses
422system.cpu.dcache.overall_accesses::total 4599 # number of overall (read+write) accesses
423system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.038328 # miss rate for ReadReq accesses
424system.cpu.dcache.ReadReq_miss_rate::total 0.038328 # miss rate for ReadReq accesses
425system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
426system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
427system.cpu.dcache.demand_miss_rate::cpu.data 0.115242 # miss rate for demand accesses
428system.cpu.dcache.demand_miss_rate::total 0.115242 # miss rate for demand accesses
429system.cpu.dcache.overall_miss_rate::cpu.data 0.115242 # miss rate for overall accesses
430system.cpu.dcache.overall_miss_rate::total 0.115242 # miss rate for overall accesses
431system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38425.619835 # average ReadReq miss latency
432system.cpu.dcache.ReadReq_avg_miss_latency::total 38425.619835 # average ReadReq miss latency
433system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43156.479218 # average WriteReq miss latency
434system.cpu.dcache.WriteReq_avg_miss_latency::total 43156.479218 # average WriteReq miss latency
435system.cpu.dcache.demand_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency
436system.cpu.dcache.demand_avg_miss_latency::total 42076.415094 # average overall miss latency
437system.cpu.dcache.overall_avg_miss_latency::cpu.data 42076.415094 # average overall miss latency
438system.cpu.dcache.overall_avg_miss_latency::total 42076.415094 # average overall miss latency

439system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
440system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
441system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
442system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
443system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
444system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
445system.cpu.dcache.fast_writes 0 # number of fast writes performed
446system.cpu.dcache.cache_copies 0 # number of cache copies performed

447system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits
448system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits
449system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits
450system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits
451system.cpu.dcache.demand_mshr_hits::cpu.data 378 # number of demand (read+write) MSHR hits
452system.cpu.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits
453system.cpu.dcache.overall_mshr_hits::cpu.data 378 # number of overall MSHR hits
454system.cpu.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits

447system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits
448system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
449system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
450system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
451system.cpu.dcache.demand_mshr_hits::cpu.data 384 # number of demand (read+write) MSHR hits
452system.cpu.dcache.demand_mshr_hits::total 384 # number of demand (read+write) MSHR hits
453system.cpu.dcache.overall_mshr_hits::cpu.data 384 # number of overall MSHR hits
454system.cpu.dcache.overall_mshr_hits::total 384 # number of overall MSHR hits

455system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses
456system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses
457system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
458system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
459system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses
460system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses
461system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses
462system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses

463system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243500 # number of ReadReq MSHR miss cycles
464system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243500 # number of ReadReq MSHR miss cycles
465system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2978500 # number of WriteReq MSHR miss cycles
466system.cpu.dcache.WriteReq_mshr_miss_latency::total 2978500 # number of WriteReq MSHR miss cycles
467system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5222000 # number of demand (read+write) MSHR miss cycles
468system.cpu.dcache.demand_mshr_miss_latency::total 5222000 # number of demand (read+write) MSHR miss cycles
469system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5222000 # number of overall MSHR miss cycles
470system.cpu.dcache.overall_mshr_miss_latency::total 5222000 # number of overall MSHR miss cycles
471system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019937 # mshr miss rate for ReadReq accesses
472system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019937 # mshr miss rate for ReadReq accesses

463system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2518000 # number of ReadReq MSHR miss cycles
464system.cpu.dcache.ReadReq_mshr_miss_latency::total 2518000 # number of ReadReq MSHR miss cycles
465system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3293000 # number of WriteReq MSHR miss cycles
466system.cpu.dcache.WriteReq_mshr_miss_latency::total 3293000 # number of WriteReq MSHR miss cycles
467system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5811000 # number of demand (read+write) MSHR miss cycles
468system.cpu.dcache.demand_mshr_miss_latency::total 5811000 # number of demand (read+write) MSHR miss cycles
469system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5811000 # number of overall MSHR miss cycles
470system.cpu.dcache.overall_mshr_miss_latency::total 5811000 # number of overall MSHR miss cycles
471system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019956 # mshr miss rate for ReadReq accesses
472system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019956 # mshr miss rate for ReadReq accesses

473system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
474system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses

475system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031725 # mshr miss rate for demand accesses
476system.cpu.dcache.demand_mshr_miss_rate::total 0.031725 # mshr miss rate for demand accesses
477system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031725 # mshr miss rate for overall accesses
478system.cpu.dcache.overall_mshr_miss_rate::total 0.031725 # mshr miss rate for overall accesses
479system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency
480system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency
481system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35885.542169 # average WriteReq mshr miss latency
482system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35885.542169 # average WriteReq mshr miss latency
483system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35767.123288 # average overall mshr miss latency
484system.cpu.dcache.demand_avg_mshr_miss_latency::total 35767.123288 # average overall mshr miss latency
485system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35767.123288 # average overall mshr miss latency
486system.cpu.dcache.overall_avg_mshr_miss_latency::total 35767.123288 # average overall mshr miss latency

475system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031746 # mshr miss rate for demand accesses
476system.cpu.dcache.demand_mshr_miss_rate::total 0.031746 # mshr miss rate for demand accesses
477system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031746 # mshr miss rate for overall accesses
478system.cpu.dcache.overall_mshr_miss_rate::total 0.031746 # mshr miss rate for overall accesses
479system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39968.253968 # average ReadReq mshr miss latency
480system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39968.253968 # average ReadReq mshr miss latency
481system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39674.698795 # average WriteReq mshr miss latency
482system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39674.698795 # average WriteReq mshr miss latency
483system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency
484system.cpu.dcache.demand_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency
485system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39801.369863 # average overall mshr miss latency
486system.cpu.dcache.overall_avg_mshr_miss_latency::total 39801.369863 # average overall mshr miss latency

487system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
488system.cpu.l2cache.replacements 0 # number of replacements

489system.cpu.l2cache.tagsinuse 236.586962 # Cycle average of tags in use

489system.cpu.l2cache.tagsinuse 234.467813 # Cycle average of tags in use

490system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.

491system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks.
492system.cpu.l2cache.avg_refs 0.004988 # Average number of references to valid blocks.

491system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
492system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks.

493system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

494system.cpu.l2cache.occ_blocks::cpu.inst 200.308921 # Average occupied blocks per requestor
495system.cpu.l2cache.occ_blocks::cpu.data 36.278041 # Average occupied blocks per requestor
496system.cpu.l2cache.occ_percent::cpu.inst 0.006113 # Average percentage of cache occupancy
497system.cpu.l2cache.occ_percent::cpu.data 0.001107 # Average percentage of cache occupancy
498system.cpu.l2cache.occ_percent::total 0.007220 # Average percentage of cache occupancy

494system.cpu.l2cache.occ_blocks::cpu.inst 198.479082 # Average occupied blocks per requestor
495system.cpu.l2cache.occ_blocks::cpu.data 35.988731 # Average occupied blocks per requestor
496system.cpu.l2cache.occ_percent::cpu.inst 0.006057 # Average percentage of cache occupancy
497system.cpu.l2cache.occ_percent::cpu.data 0.001098 # Average percentage of cache occupancy
498system.cpu.l2cache.occ_percent::total 0.007155 # Average percentage of cache occupancy

499system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
500system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
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504system.cpu.l2cache.overall_hits::total 2 # number of overall hits

505system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses

505system.cpu.l2cache.ReadReq_misses::cpu.inst 337 # number of ReadReq misses

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507system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses

507system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses

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509system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses

510system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses

510system.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses

511system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses

512system.cpu.l2cache.demand_misses::total 484 # number of demand (read+write) misses
513system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses

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513system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses

514system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses

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529system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses)

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532system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses

533system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses

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535system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses

536system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses

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552system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency
553system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency
554system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34264.792899 # average overall miss latency
555system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency
556system.cpu.l2cache.demand_avg_miss_latency::total 34337.809917 # average overall miss latency
557system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34264.792899 # average overall miss latency
558system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency
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549system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35213.649852 # average ReadReq miss latency
550system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38595.238095 # average ReadReq miss latency
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552system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38487.951807 # average ReadExReq miss latency
553system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38487.951807 # average ReadExReq miss latency
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555system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38534.246575 # average overall miss latency
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557system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35213.649852 # average overall miss latency
558system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38534.246575 # average overall miss latency
559system.cpu.l2cache.overall_avg_miss_latency::total 36217.391304 # average overall miss latency

560system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
561system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
562system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
563system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
564system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
565system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
566system.cpu.l2cache.fast_writes 0 # number of fast writes performed
567system.cpu.l2cache.cache_copies 0 # number of cache copies performed

568system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses

568system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses

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573system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses

573system.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses

574system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses

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576system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses

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