| stats.txt (8844:a451e4eda591) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 19744500 # Number of ticks simulated 5final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 19744500 # Number of ticks simulated 5final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 108489 # Simulator instruction rate (inst/s) 8host_op_rate 108474 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 148211557 # Simulator tick rate (ticks/s) 10host_mem_usage 211612 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host | 7host_inst_rate 52427 # Simulator instruction rate (inst/s) 8host_op_rate 52424 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 71633039 # Simulator tick rate (ticks/s) 10host_mem_usage 221536 # Number of bytes of host memory used 11host_seconds 0.28 # Real time elapsed on the host |
| 12sim_insts 14449 # Number of instructions simulated 13sim_ops 14449 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 30976 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 484 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 302 unchanged lines hidden (view full) --- 322system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses 323system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency 324system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency 325system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency 326system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 327system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 328system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 329system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 14449 # Number of instructions simulated 13sim_ops 14449 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 30976 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 484 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 302 unchanged lines hidden (view full) --- 322system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses 323system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency 324system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency 325system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency 326system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 327system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 328system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 329system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 330system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 331system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 330system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 331system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 332system.cpu.icache.fast_writes 0 # number of fast writes performed 333system.cpu.icache.cache_copies 0 # number of cache copies performed 334system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits 335system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits 336system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits 337system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits 338system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits 339system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits --- 68 unchanged lines hidden (view full) --- 408system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency 410system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency 411system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency 412system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 413system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 332system.cpu.icache.fast_writes 0 # number of fast writes performed 333system.cpu.icache.cache_copies 0 # number of cache copies performed 334system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits 335system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits 336system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits 337system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits 338system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits 339system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits --- 68 unchanged lines hidden (view full) --- 408system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency 410system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency 411system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency 412system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 413system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 416system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 417system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 416system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 417system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 418system.cpu.dcache.fast_writes 0 # number of fast writes performed 419system.cpu.dcache.cache_copies 0 # number of cache copies performed 420system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits 421system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits 422system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits 423system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits 424system.cpu.dcache.demand_mshr_hits::cpu.data 380 # number of demand (read+write) MSHR hits 425system.cpu.dcache.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits --- 87 unchanged lines hidden (view full) --- 513system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency 514system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency 515system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency 516system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency 517system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 518system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 519system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 520system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 418system.cpu.dcache.fast_writes 0 # number of fast writes performed 419system.cpu.dcache.cache_copies 0 # number of cache copies performed 420system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits 421system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits 422system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits 423system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits 424system.cpu.dcache.demand_mshr_hits::cpu.data 380 # number of demand (read+write) MSHR hits 425system.cpu.dcache.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits --- 87 unchanged lines hidden (view full) --- 513system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency 514system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency 515system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency 516system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency 517system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 518system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 519system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 520system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 521system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 522system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 521system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 522system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 523system.cpu.l2cache.fast_writes 0 # number of fast writes performed 524system.cpu.l2cache.cache_copies 0 # number of cache copies performed 525system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 526system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses 527system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses 528system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 529system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 530system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- | 523system.cpu.l2cache.fast_writes 0 # number of fast writes performed 524system.cpu.l2cache.cache_copies 0 # number of cache copies performed 525system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 526system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses 527system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses 528system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 529system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 530system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- |