| stats.txt (11731:c473ca7cc650) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated |
| 4sim_ticks 29908500 # Number of ticks simulated 5final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 29673500 # Number of ticks simulated 5final_tick 29673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 19226 # Simulator instruction rate (inst/s) 8host_op_rate 19225 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39829510 # Simulator tick rate (ticks/s) 10host_mem_usage 234412 # Number of bytes of host memory used 11host_seconds 0.75 # Real time elapsed on the host | 7host_inst_rate 97740 # Simulator instruction rate (inst/s) 8host_op_rate 97731 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 200871294 # Simulator tick rate (ticks/s) 10host_mem_usage 251556 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 23360 # Number of bytes read from this memory | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 32768 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 23360 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 23360 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 365 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 32640 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory | 23system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::total 512 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 781048866 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 314559406 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1095608272 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 781048866 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 781048866 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 781048866 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 314559406 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1095608272 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 513 # Number of read requests accepted | 24system.physmem.num_reads::total 510 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 782920788 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 317050567 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1099971355 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 782920788 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 782920788 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 782920788 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 317050567 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1099971355 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 511 # Number of read requests accepted |
| 34system.physmem.writeReqs 0 # Number of write requests accepted | 34system.physmem.writeReqs 0 # Number of write requests accepted |
| 35system.physmem.readBursts 513 # Number of DRAM read bursts, including those serviced by the write queue | 35system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue |
| 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 37system.physmem.bytesReadDRAM 32832 # Total number of bytes read from DRAM | 37system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM |
| 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 40system.physmem.bytesReadSys 32832 # Total read bytes from the system interface side | 40system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side |
| 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 45system.physmem.perBankRdBursts::0 105 # Per bank write bursts | 45system.physmem.perBankRdBursts::0 104 # Per bank write bursts |
| 46system.physmem.perBankRdBursts::1 28 # Per bank write bursts | 46system.physmem.perBankRdBursts::1 28 # Per bank write bursts |
| 47system.physmem.perBankRdBursts::2 55 # Per bank write bursts 48system.physmem.perBankRdBursts::3 27 # Per bank write bursts 49system.physmem.perBankRdBursts::4 23 # Per bank write bursts | 47system.physmem.perBankRdBursts::2 54 # Per bank write bursts 48system.physmem.perBankRdBursts::3 28 # Per bank write bursts 49system.physmem.perBankRdBursts::4 22 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::5 0 # Per bank write bursts 51system.physmem.perBankRdBursts::6 32 # Per bank write bursts 52system.physmem.perBankRdBursts::7 38 # Per bank write bursts 53system.physmem.perBankRdBursts::8 7 # Per bank write bursts 54system.physmem.perBankRdBursts::9 4 # Per bank write bursts 55system.physmem.perBankRdBursts::10 2 # Per bank write bursts 56system.physmem.perBankRdBursts::11 0 # Per bank write bursts 57system.physmem.perBankRdBursts::12 57 # Per bank write bursts --- 13 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 50system.physmem.perBankRdBursts::5 0 # Per bank write bursts 51system.physmem.perBankRdBursts::6 32 # Per bank write bursts 52system.physmem.perBankRdBursts::7 38 # Per bank write bursts 53system.physmem.perBankRdBursts::8 7 # Per bank write bursts 54system.physmem.perBankRdBursts::9 4 # Per bank write bursts 55system.physmem.perBankRdBursts::10 2 # Per bank write bursts 56system.physmem.perBankRdBursts::11 0 # Per bank write bursts 57system.physmem.perBankRdBursts::12 57 # Per bank write bursts --- 13 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 29877000 # Total gap between requests | 79system.physmem.totGap 29642000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 86system.physmem.readPktSize::6 513 # Read request sizes (log2) | 86system.physmem.readPktSize::6 511 # Read request sizes (log2) |
| 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 282 # What read queue length does an incoming req see | 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 282 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::1 156 # What read queue length does an incoming req see | 95system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see | 96system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see |
| 97system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see | 97system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation | 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation |
| 191system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 253.933476 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 348.475070 # Bytes accessed per row activation | 191system.physmem.bytesPerActivate::mean 393.025641 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 252.718123 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 347.605052 # Bytes accessed per row activation |
| 194system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% # Bytes accessed per row activation | 194system.physmem.bytesPerActivate::0-127 17 21.79% 21.79% # Bytes accessed per row activation |
| 195system.physmem.bytesPerActivate::128-255 19 24.36% 46.15% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 12 15.38% 61.54% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 5 6.41% 67.95% # Bytes accessed per row activation | 195system.physmem.bytesPerActivate::128-255 18 23.08% 44.87% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 14 17.95% 62.82% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 4 5.13% 67.95% # Bytes accessed per row activation |
| 198system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation | 198system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation |
| 200system.physmem.bytesPerActivate::768-895 6 7.69% 83.33% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.28% 84.62% # Bytes accessed per row activation | 200system.physmem.bytesPerActivate::768-895 7 8.97% 84.62% # Bytes accessed per row activation |
| 202system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation | 201system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation |
| 204system.physmem.totQLat 6719500 # Total ticks spent queuing 205system.physmem.totMemAccLat 16338250 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2565000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 13098.44 # Average queueing delay per DRAM burst | 203system.physmem.totQLat 6610250 # Total ticks spent queuing 204system.physmem.totMemAccLat 16191500 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 12935.91 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 31848.44 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1097.75 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 31685.91 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1102.13 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 1097.75 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1102.13 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 8.58 # Data bus utilization in percentage 216system.physmem.busUtilRead 8.58 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 8.61 # Data bus utilization in percentage 215system.physmem.busUtilRead 8.61 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 424 # Number of row buffer hits during reads | 219system.physmem.readRowHits 422 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 82.65 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 58239.77 # Average gap between requests 225system.physmem.pageHitRate 82.65 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 357000 # Energy for activate commands per rank (pJ) | 223system.physmem.avgGap 58007.83 # Average gap between requests 224system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 364140 # Energy for activate commands per rank (pJ) |
| 227system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) | 226system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) |
| 228system.physmem_0.readEnergy 2199120 # Energy for read commands per rank (pJ) | 227system.physmem_0.readEnergy 2184840 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 3644010 # Energy for active background per rank (pJ) | 230system.physmem_0.actBackEnergy 3606960 # Energy for active background per rank (pJ) |
| 232system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) | 231system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) |
| 233system.physmem_0.actPowerDownEnergy 9899190 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 16800 # Energy for precharge power-down per rank (pJ) | 232system.physmem_0.actPowerDownEnergy 9847320 # Energy for active power-down per rank (pJ) 233system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) |
| 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 234system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 236system.physmem_0.totalEnergy 18197970 # Total energy per rank (pJ) 237system.physmem_0.averagePower 608.449701 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 21617000 # Total Idle time Per DRAM Rank | 235system.physmem_0.totalEnergy 18086550 # Total energy per rank (pJ) 236system.physmem_0.averagePower 609.513459 # Core power per rank (mW) 237system.physmem_0.totalIdleTime 21469250 # Total Idle time Per DRAM Rank |
| 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states | 238system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 239system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 240system.physmem_0.memoryStateTime::SREF 0 # Time in different power states |
| 242system.physmem_0.memoryStateTime::PRE_PDN 44000 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 7338500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 21705500 # Time in different power states 245system.physmem_1.actEnergy 278460 # Energy for activate commands per rank (pJ) | 241system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states 242system.physmem_0.memoryStateTime::ACT 7251250 # Time in different power states 243system.physmem_0.memoryStateTime::ACT_PDN 21598000 # Time in different power states 244system.physmem_1.actEnergy 271320 # Energy for activate commands per rank (pJ) |
| 246system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) | 245system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) 246system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) 247system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 248system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 2521680 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 86880 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 10427010 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) | 249system.physmem_1.actBackEnergy 2504580 # Energy for active background per rank (pJ) 250system.physmem_1.preBackEnergy 86400 # Energy for precharge background per rank (pJ) 251system.physmem_1.actPowerDownEnergy 10184760 # Energy for active power-down per rank (pJ) 252system.physmem_1.prePowerDownEnergy 622560 # Energy for precharge power-down per rank (pJ) |
| 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 253system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 255system.physmem_1.totalEnergy 17237010 # Total energy per rank (pJ) 256system.physmem_1.averagePower 576.319973 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 24154250 # Total Idle time Per DRAM Rank | 254system.physmem_1.totalEnergy 17098680 # Total energy per rank (pJ) 255system.physmem_1.averagePower 576.222419 # Core power per rank (mW) 256system.physmem_1.totalIdleTime 23952750 # Total Idle time Per DRAM Rank |
| 258system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states | 257system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states 258system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 259system.physmem_1.memoryStateTime::SREF 0 # Time in different power states |
| 261system.physmem_1.memoryStateTime::PRE_PDN 1286000 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 4831250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 22868250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 12304 # Number of BP lookups 266system.cpu.branchPred.condPredicted 7429 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 1435 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 9156 # Number of BTB lookups | 260system.physmem_1.memoryStateTime::PRE_PDN 1619750 # Time in different power states 261system.physmem_1.memoryStateTime::ACT 4797750 # Time in different power states 262system.physmem_1.memoryStateTime::ACT_PDN 22333000 # Time in different power states 263system.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states 264system.cpu.branchPred.lookups 11901 # Number of BP lookups 265system.cpu.branchPred.condPredicted 7287 # Number of conditional branches predicted 266system.cpu.branchPred.condIncorrect 1354 # Number of conditional branches incorrect 267system.cpu.branchPred.BTBLookups 9352 # Number of BTB lookups |
| 269system.cpu.branchPred.BTBHits 0 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage | 268system.cpu.branchPred.BTBHits 0 # Number of BTB hits 269system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 270system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage |
| 272system.cpu.branchPred.usedRAS 730 # Number of times the RAS was used to get a target. | 271system.cpu.branchPred.usedRAS 685 # Number of times the RAS was used to get a target. |
| 273system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. | 272system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. |
| 274system.cpu.branchPred.indirectLookups 9156 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 1824 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 7332 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 865 # Number of mispredicted indirect branches. | 273system.cpu.branchPred.indirectLookups 9352 # Number of indirect predictor lookups. 274system.cpu.branchPred.indirectHits 1949 # Number of indirect target hits. 275system.cpu.branchPred.indirectMisses 7403 # Number of indirect misses. 276system.cpu.branchPredindirectMispredicted 793 # Number of mispredicted indirect branches. |
| 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.workload.num_syscalls 18 # Number of system calls | 277system.cpu_clk_domain.clock 500 # Clock period in ticks 278system.cpu.workload.num_syscalls 18 # Number of system calls |
| 280system.cpu.pwrStateResidencyTicks::ON 29908500 # Cumulative time (in ticks) in various power states 281system.cpu.numCycles 59818 # number of cpu cycles simulated | 279system.cpu.pwrStateResidencyTicks::ON 29673500 # Cumulative time (in ticks) in various power states 280system.cpu.numCycles 59348 # number of cpu cycles simulated |
| 282system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 283system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 281system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 282system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 284system.cpu.fetch.icacheStallCycles 15502 # Number of cycles fetch is stalled on an Icache miss 285system.cpu.fetch.Insts 57440 # Number of instructions fetch has processed 286system.cpu.fetch.Branches 12304 # Number of branches that fetch encountered 287system.cpu.fetch.predictedBranches 2554 # Number of branches that fetch has predicted taken 288system.cpu.fetch.Cycles 17524 # Number of cycles fetch has run and was not squashing or blocked 289system.cpu.fetch.SquashCycles 3065 # Number of cycles fetch has spent squashing 290system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 291system.cpu.fetch.PendingTrapStallCycles 1117 # Number of stall cycles due to pending traps | 283system.cpu.fetch.icacheStallCycles 15163 # Number of cycles fetch is stalled on an Icache miss 284system.cpu.fetch.Insts 55604 # Number of instructions fetch has processed 285system.cpu.fetch.Branches 11901 # Number of branches that fetch encountered 286system.cpu.fetch.predictedBranches 2634 # Number of branches that fetch has predicted taken 287system.cpu.fetch.Cycles 17364 # Number of cycles fetch has run and was not squashing or blocked 288system.cpu.fetch.SquashCycles 2905 # Number of cycles fetch has spent squashing 289system.cpu.fetch.TlbCycles 12 # Number of cycles fetch has spent waiting for tlb 290system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 291system.cpu.fetch.PendingTrapStallCycles 1168 # Number of stall cycles due to pending traps |
| 292system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR | 292system.cpu.fetch.IcacheWaitRetryStallCycles 12 # Number of stall cycles due to full MSHR |
| 293system.cpu.fetch.CacheLines 7446 # Number of cache lines fetched 294system.cpu.fetch.IcacheSquashes 730 # Number of outstanding Icache misses that were squashed 295system.cpu.fetch.rateDist::samples 35692 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::mean 1.609324 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::stdev 2.874327 # Number of instructions fetched each cycle (Total) | 293system.cpu.fetch.CacheLines 7191 # Number of cache lines fetched 294system.cpu.fetch.IcacheSquashes 701 # Number of outstanding Icache misses that were squashed 295system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed 296system.cpu.fetch.rateDist::samples 35180 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::mean 1.580557 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::stdev 2.839184 # Number of instructions fetched each cycle (Total) |
| 298system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 299system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 299system.cpu.fetch.rateDist::0 23194 64.98% 64.98% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::1 4479 12.55% 77.53% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::2 496 1.39% 78.92% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::3 441 1.24% 80.16% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::4 761 2.13% 82.29% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::5 680 1.91% 84.20% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::6 284 0.80% 84.99% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::7 358 1.00% 85.99% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::8 4999 14.01% 100.00% # Number of instructions fetched each cycle (Total) | 300system.cpu.fetch.rateDist::0 22867 65.00% 65.00% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::1 4490 12.76% 77.76% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::2 508 1.44% 79.21% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::3 450 1.28% 80.49% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::4 761 2.16% 82.65% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::5 731 2.08% 84.73% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::6 296 0.84% 85.57% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::7 343 0.97% 86.54% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::8 4734 13.46% 100.00% # Number of instructions fetched each cycle (Total) |
| 308system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 309system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 311system.cpu.fetch.rateDist::total 35692 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.branchRate 0.205691 # Number of branch fetches per cycle 313system.cpu.fetch.rate 0.960246 # Number of inst fetches per cycle 314system.cpu.decode.IdleCycles 12333 # Number of cycles decode is idle 315system.cpu.decode.BlockedCycles 13299 # Number of cycles decode is blocked 316system.cpu.decode.RunCycles 7732 # Number of cycles decode is running 317system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking 318system.cpu.decode.SquashCycles 1532 # Number of cycles decode is squashing 319system.cpu.decode.DecodedInsts 41071 # Number of instructions handled by decode 320system.cpu.rename.SquashCycles 1532 # Number of cycles rename is squashing 321system.cpu.rename.IdleCycles 13082 # Number of cycles rename is idle 322system.cpu.rename.BlockCycles 2036 # Number of cycles rename is blocking 323system.cpu.rename.serializeStallCycles 9748 # count of cycles rename stalled for serializing inst 324system.cpu.rename.RunCycles 7750 # Number of cycles rename is running 325system.cpu.rename.UnblockCycles 1544 # Number of cycles rename is unblocking 326system.cpu.rename.RenamedInsts 36233 # Number of instructions processed by rename 327system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full | 312system.cpu.fetch.rateDist::total 35180 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.branchRate 0.200529 # Number of branch fetches per cycle 314system.cpu.fetch.rate 0.936914 # Number of inst fetches per cycle 315system.cpu.decode.IdleCycles 12094 # Number of cycles decode is idle 316system.cpu.decode.BlockedCycles 13233 # Number of cycles decode is blocked 317system.cpu.decode.RunCycles 7639 # Number of cycles decode is running 318system.cpu.decode.UnblockCycles 762 # Number of cycles decode is unblocking 319system.cpu.decode.SquashCycles 1452 # Number of cycles decode is squashing 320system.cpu.decode.DecodedInsts 39805 # Number of instructions handled by decode 321system.cpu.rename.SquashCycles 1452 # Number of cycles rename is squashing 322system.cpu.rename.IdleCycles 12828 # Number of cycles rename is idle 323system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking 324system.cpu.rename.serializeStallCycles 9904 # count of cycles rename stalled for serializing inst 325system.cpu.rename.RunCycles 7640 # Number of cycles rename is running 326system.cpu.rename.UnblockCycles 1543 # Number of cycles rename is unblocking 327system.cpu.rename.RenamedInsts 35279 # Number of instructions processed by rename 328system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full |
| 328system.cpu.rename.SQFullEvents 1128 # Number of times rename has blocked due to SQ full | 329system.cpu.rename.SQFullEvents 1128 # Number of times rename has blocked due to SQ full |
| 329system.cpu.rename.RenamedOperands 31392 # Number of destination operands rename has renamed 330system.cpu.rename.RenameLookups 65112 # Number of register rename lookups that rename has made 331system.cpu.rename.int_rename_lookups 53717 # Number of integer rename lookups | 330system.cpu.rename.RenamedOperands 30611 # Number of destination operands rename has renamed 331system.cpu.rename.RenameLookups 63420 # Number of register rename lookups that rename has made 332system.cpu.rename.int_rename_lookups 52396 # Number of integer rename lookups |
| 332system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed | 333system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed |
| 333system.cpu.rename.UndoneMaps 17573 # Number of HB maps that are undone due to squashing 334system.cpu.rename.serializingInsts 793 # count of serializing insts renamed 335system.cpu.rename.tempSerializingInsts 793 # count of temporary serializing insts renamed 336system.cpu.rename.skidInsts 4281 # count of insts added to the skid buffer 337system.cpu.memDep0.insertedLoads 4496 # Number of loads inserted to the mem dependence unit. 338system.cpu.memDep0.insertedStores 2885 # Number of stores inserted to the mem dependence unit. 339system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. | 334system.cpu.rename.UndoneMaps 16792 # Number of HB maps that are undone due to squashing 335system.cpu.rename.serializingInsts 761 # count of serializing insts renamed 336system.cpu.rename.tempSerializingInsts 767 # count of temporary serializing insts renamed 337system.cpu.rename.skidInsts 4154 # count of insts added to the skid buffer 338system.cpu.memDep0.insertedLoads 4391 # Number of loads inserted to the mem dependence unit. 339system.cpu.memDep0.insertedStores 2803 # Number of stores inserted to the mem dependence unit. 340system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. |
| 340system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. | 341system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. |
| 341system.cpu.iq.iqInstsAdded 28450 # Number of instructions added to the IQ (excludes non-spec) 342system.cpu.iq.iqNonSpecInstsAdded 744 # Number of non-speculative instructions added to the IQ 343system.cpu.iq.iqInstsIssued 25030 # Number of instructions issued 344system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued 345system.cpu.iq.iqSquashedInstsExamined 14758 # Number of squashed instructions iterated over during squash; mainly for profiling 346system.cpu.iq.iqSquashedOperandsExamined 11000 # Number of squashed operands that are examined and possibly removed from graph 347system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed 348system.cpu.iq.issued_per_cycle::samples 35692 # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::mean 0.701278 # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::stdev 1.501683 # Number of insts issued each cycle | 342system.cpu.iq.iqInstsAdded 27854 # Number of instructions added to the IQ (excludes non-spec) 343system.cpu.iq.iqNonSpecInstsAdded 724 # Number of non-speculative instructions added to the IQ 344system.cpu.iq.iqInstsIssued 24627 # Number of instructions issued 345system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued 346system.cpu.iq.iqSquashedInstsExamined 14142 # Number of squashed instructions iterated over during squash; mainly for profiling 347system.cpu.iq.iqSquashedOperandsExamined 10452 # Number of squashed operands that are examined and possibly removed from graph 348system.cpu.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed 349system.cpu.iq.issued_per_cycle::samples 35180 # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::mean 0.700028 # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::stdev 1.493682 # Number of insts issued each cycle |
| 351system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 352system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 352system.cpu.iq.issued_per_cycle::0 26611 74.56% 74.56% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::1 3173 8.89% 83.45% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::2 1585 4.44% 87.89% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::3 1525 4.27% 92.16% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::4 1196 3.35% 95.51% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::5 748 2.10% 97.61% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::6 484 1.36% 98.96% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::7 276 0.77% 99.74% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::8 94 0.26% 100.00% # Number of insts issued each cycle | 353system.cpu.iq.issued_per_cycle::0 26218 74.53% 74.53% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::1 3125 8.88% 83.41% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::2 1567 4.45% 87.86% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::3 1507 4.28% 92.15% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::4 1190 3.38% 95.53% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::5 757 2.15% 97.68% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::6 486 1.38% 99.06% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::7 254 0.72% 99.78% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::8 76 0.22% 100.00% # Number of insts issued each cycle |
| 361system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 362system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 364system.cpu.iq.issued_per_cycle::total 35692 # Number of insts issued each cycle | 365system.cpu.iq.issued_per_cycle::total 35180 # Number of insts issued each cycle |
| 365system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 366system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 366system.cpu.iq.fu_full::IntAlu 164 53.07% 53.07% # attempts to use FU when none available 367system.cpu.iq.fu_full::IntMult 0 0.00% 53.07% # attempts to use FU when none available 368system.cpu.iq.fu_full::IntDiv 0 0.00% 53.07% # attempts to use FU when none available 369system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.07% # attempts to use FU when none available 370system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.07% # attempts to use FU when none available 371system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.07% # attempts to use FU when none available 372system.cpu.iq.fu_full::FloatMult 0 0.00% 53.07% # attempts to use FU when none available 373system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.07% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.07% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.07% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.07% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.07% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.07% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.07% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.07% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.07% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdMult 0 0.00% 53.07% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.07% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdShift 0 0.00% 53.07% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.07% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.07% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.07% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.07% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.07% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.07% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.07% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.07% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.07% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.07% # attempts to use FU when none available 397system.cpu.iq.fu_full::MemRead 53 17.15% 70.23% # attempts to use FU when none available 398system.cpu.iq.fu_full::MemWrite 92 29.77% 100.00% # attempts to use FU when none available | 367system.cpu.iq.fu_full::IntAlu 151 52.07% 52.07% # attempts to use FU when none available 368system.cpu.iq.fu_full::IntMult 0 0.00% 52.07% # attempts to use FU when none available 369system.cpu.iq.fu_full::IntDiv 0 0.00% 52.07% # attempts to use FU when none available 370system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.07% # attempts to use FU when none available 371system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.07% # attempts to use FU when none available 372system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.07% # attempts to use FU when none available 373system.cpu.iq.fu_full::FloatMult 0 0.00% 52.07% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.07% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.07% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.07% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.07% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.07% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.07% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.07% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.07% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.07% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdMult 0 0.00% 52.07% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.07% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdShift 0 0.00% 52.07% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.07% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.07% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.07% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.07% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.07% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.07% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.07% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.07% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.07% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.07% # attempts to use FU when none available 398system.cpu.iq.fu_full::MemRead 51 17.59% 69.66% # attempts to use FU when none available 399system.cpu.iq.fu_full::MemWrite 88 30.34% 100.00% # attempts to use FU when none available |
| 399system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 401system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 402system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 403system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 400system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 402system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 404system.cpu.iq.FU_type_0::IntAlu 18344 73.29% 73.29% # Type of FU issued 405system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.29% # Type of FU issued 406system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.29% # Type of FU issued 407system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.29% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.29% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.29% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.29% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.29% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.29% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.29% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.29% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.29% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.29% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.29% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.29% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.29% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.29% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.29% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.29% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.29% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.29% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.29% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.29% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.29% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.29% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.29% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.29% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.29% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.29% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.29% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 4185 16.72% 90.01% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 2501 9.99% 100.00% # Type of FU issued | 405system.cpu.iq.FU_type_0::IntAlu 18085 73.44% 73.44% # Type of FU issued 406system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.44% # Type of FU issued 407system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.44% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.44% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.44% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.44% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.44% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.44% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.44% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.44% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.44% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.44% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.44% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.44% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.44% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.44% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.44% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.44% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.44% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.44% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.44% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.44% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.44% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.44% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.44% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.44% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.44% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.44% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.44% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.44% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.44% # Type of FU issued 436system.cpu.iq.FU_type_0::MemRead 4096 16.63% 90.07% # Type of FU issued 437system.cpu.iq.FU_type_0::MemWrite 2446 9.93% 100.00% # Type of FU issued |
| 437system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 438system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 441system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 441system.cpu.iq.FU_type_0::total 25030 # Type of FU issued 442system.cpu.iq.rate 0.418436 # Inst issue rate 443system.cpu.iq.fu_busy_cnt 309 # FU busy when requested 444system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst) 445system.cpu.iq.int_inst_queue_reads 86193 # Number of integer instruction queue reads 446system.cpu.iq.int_inst_queue_writes 43979 # Number of integer instruction queue writes 447system.cpu.iq.int_inst_queue_wakeup_accesses 22369 # Number of integer instruction queue wakeup accesses | 442system.cpu.iq.FU_type_0::total 24627 # Type of FU issued 443system.cpu.iq.rate 0.414959 # Inst issue rate 444system.cpu.iq.fu_busy_cnt 290 # FU busy when requested 445system.cpu.iq.fu_busy_rate 0.011776 # FU busy rate (busy events/executed inst) 446system.cpu.iq.int_inst_queue_reads 84846 # Number of integer instruction queue reads 447system.cpu.iq.int_inst_queue_writes 42748 # Number of integer instruction queue writes 448system.cpu.iq.int_inst_queue_wakeup_accesses 22066 # Number of integer instruction queue wakeup accesses |
| 448system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 449system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 450system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 449system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 450system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 451system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 451system.cpu.iq.int_alu_accesses 25339 # Number of integer alu accesses | 452system.cpu.iq.int_alu_accesses 24917 # Number of integer alu accesses |
| 452system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 453system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores 454system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 453system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 454system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores 455system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 455system.cpu.iew.lsq.thread0.squashedLoads 2271 # Number of loads squashed | 456system.cpu.iew.lsq.thread0.squashedLoads 2166 # Number of loads squashed |
| 456system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed | 457system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed |
| 457system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations 458system.cpu.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed | 458system.cpu.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations 459system.cpu.iew.lsq.thread0.squashedStores 1355 # Number of stores squashed |
| 459system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 460system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 461system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 462system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked 463system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 460system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 461system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 462system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 463system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked 464system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 464system.cpu.iew.iewSquashCycles 1532 # Number of cycles IEW is squashing 465system.cpu.iew.iewBlockCycles 2073 # Number of cycles IEW is blocking 466system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 467system.cpu.iew.iewDispatchedInsts 30726 # Number of instructions dispatched to IQ 468system.cpu.iew.iewDispSquashedInsts 235 # Number of squashed instructions skipped by dispatch 469system.cpu.iew.iewDispLoadInsts 4496 # Number of dispatched load instructions 470system.cpu.iew.iewDispStoreInsts 2885 # Number of dispatched store instructions 471system.cpu.iew.iewDispNonSpecInsts 744 # Number of dispatched non-speculative instructions | 465system.cpu.iew.iewSquashCycles 1452 # Number of cycles IEW is squashing 466system.cpu.iew.iewBlockCycles 1841 # Number of cycles IEW is blocking 467system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking 468system.cpu.iew.iewDispatchedInsts 30085 # Number of instructions dispatched to IQ 469system.cpu.iew.iewDispSquashedInsts 231 # Number of squashed instructions skipped by dispatch 470system.cpu.iew.iewDispLoadInsts 4391 # Number of dispatched load instructions 471system.cpu.iew.iewDispStoreInsts 2803 # Number of dispatched store instructions 472system.cpu.iew.iewDispNonSpecInsts 724 # Number of dispatched non-speculative instructions |
| 472system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 473system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall | 473system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 474system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall |
| 474system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations 475system.cpu.iew.predictedTakenIncorrect 207 # Number of branches that were predicted taken incorrectly 476system.cpu.iew.predictedNotTakenIncorrect 1574 # Number of branches that were predicted not taken incorrectly 477system.cpu.iew.branchMispredicts 1781 # Number of branch mispredicts detected at execute 478system.cpu.iew.iewExecutedInsts 23432 # Number of executed instructions 479system.cpu.iew.iewExecLoadInsts 3882 # Number of load instructions executed 480system.cpu.iew.iewExecSquashedInsts 1598 # Number of squashed instructions skipped in execute | 475system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations 476system.cpu.iew.predictedTakenIncorrect 209 # Number of branches that were predicted taken incorrectly 477system.cpu.iew.predictedNotTakenIncorrect 1460 # Number of branches that were predicted not taken incorrectly 478system.cpu.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute 479system.cpu.iew.iewExecutedInsts 23080 # Number of executed instructions 480system.cpu.iew.iewExecLoadInsts 3816 # Number of load instructions executed 481system.cpu.iew.iewExecSquashedInsts 1547 # Number of squashed instructions skipped in execute |
| 481system.cpu.iew.exec_swp 0 # number of swp insts executed | 482system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 482system.cpu.iew.exec_nop 1532 # number of nop insts executed 483system.cpu.iew.exec_refs 6190 # number of memory reference insts executed 484system.cpu.iew.exec_branches 4984 # Number of branches executed 485system.cpu.iew.exec_stores 2308 # Number of stores executed 486system.cpu.iew.exec_rate 0.391722 # Inst execution rate 487system.cpu.iew.wb_sent 22840 # cumulative count of insts sent to commit 488system.cpu.iew.wb_count 22369 # cumulative count of insts written-back 489system.cpu.iew.wb_producers 10409 # num instructions producing a value 490system.cpu.iew.wb_consumers 13648 # num instructions consuming a value 491system.cpu.iew.wb_rate 0.373951 # insts written-back per cycle 492system.cpu.iew.wb_fanout 0.762676 # average fanout of values written-back 493system.cpu.commit.commitSquashedInsts 15475 # The number of squashed insts skipped by commit | 483system.cpu.iew.exec_nop 1507 # number of nop insts executed 484system.cpu.iew.exec_refs 6070 # number of memory reference insts executed 485system.cpu.iew.exec_branches 4884 # Number of branches executed 486system.cpu.iew.exec_stores 2254 # Number of stores executed 487system.cpu.iew.exec_rate 0.388893 # Inst execution rate 488system.cpu.iew.wb_sent 22529 # cumulative count of insts sent to commit 489system.cpu.iew.wb_count 22066 # cumulative count of insts written-back 490system.cpu.iew.wb_producers 10367 # num instructions producing a value 491system.cpu.iew.wb_consumers 13651 # num instructions consuming a value 492system.cpu.iew.wb_rate 0.371807 # insts written-back per cycle 493system.cpu.iew.wb_fanout 0.759432 # average fanout of values written-back 494system.cpu.commit.commitSquashedInsts 14855 # The number of squashed insts skipped by commit |
| 494system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards | 495system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards |
| 495system.cpu.commit.branchMispredicts 1435 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 32615 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 0.464878 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 1.257144 # Number of insts commited each cycle | 496system.cpu.commit.branchMispredicts 1354 # The number of times a branch was mispredicted 497system.cpu.commit.committed_per_cycle::samples 32262 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::mean 0.469965 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::stdev 1.260994 # Number of insts commited each cycle |
| 499system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 500system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 500system.cpu.commit.committed_per_cycle::0 25974 79.64% 79.64% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::1 3555 10.90% 90.54% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::2 1191 3.65% 94.19% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::3 577 1.77% 95.96% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::4 319 0.98% 96.94% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::5 311 0.95% 97.89% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::6 392 1.20% 99.09% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::7 57 0.17% 99.27% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::8 239 0.73% 100.00% # Number of insts commited each cycle | 501system.cpu.commit.committed_per_cycle::0 25609 79.38% 79.38% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::1 3577 11.09% 90.47% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::2 1157 3.59% 94.05% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::3 603 1.87% 95.92% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::4 332 1.03% 96.95% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::5 298 0.92% 97.87% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::6 393 1.22% 99.09% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::7 58 0.18% 99.27% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::8 235 0.73% 100.00% # Number of insts commited each cycle |
| 509system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 510system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 512system.cpu.commit.committed_per_cycle::total 32615 # Number of insts commited each cycle | 513system.cpu.commit.committed_per_cycle::total 32262 # Number of insts commited each cycle |
| 513system.cpu.commit.committedInsts 15162 # Number of instructions committed 514system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 515system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 516system.cpu.commit.refs 3673 # Number of memory references committed 517system.cpu.commit.loads 2225 # Number of loads committed 518system.cpu.commit.membars 0 # Number of memory barriers committed 519system.cpu.commit.branches 3358 # Number of branches committed 520system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 554system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction 555system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction 556system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 558system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 559system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 560system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 561system.cpu.commit.op_class_0::total 15162 # Class of committed instruction | 514system.cpu.commit.committedInsts 15162 # Number of instructions committed 515system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 516system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 517system.cpu.commit.refs 3673 # Number of memory references committed 518system.cpu.commit.loads 2225 # Number of loads committed 519system.cpu.commit.membars 0 # Number of memory barriers committed 520system.cpu.commit.branches 3358 # Number of branches committed 521system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 555system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction 556system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction 557system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 558system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 559system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 560system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 561system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 562system.cpu.commit.op_class_0::total 15162 # Class of committed instruction |
| 562system.cpu.commit.bw_lim_events 239 # number cycles where commit BW limit reached 563system.cpu.rob.rob_reads 62190 # The number of ROB reads 564system.cpu.rob.rob_writes 64431 # The number of ROB writes | 563system.cpu.commit.bw_lim_events 235 # number cycles where commit BW limit reached 564system.cpu.rob.rob_reads 61221 # The number of ROB reads 565system.cpu.rob.rob_writes 63021 # The number of ROB writes |
| 565system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself | 566system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 566system.cpu.idleCycles 24126 # Total number of cycles that the CPU has spent unscheduled due to idling | 567system.cpu.idleCycles 24168 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 567system.cpu.committedInsts 14436 # Number of Instructions Simulated 568system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated | 568system.cpu.committedInsts 14436 # Number of Instructions Simulated 569system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated |
| 569system.cpu.cpi 4.143669 # CPI: Cycles Per Instruction 570system.cpu.cpi_total 4.143669 # CPI: Total CPI of All Threads 571system.cpu.ipc 0.241332 # IPC: Instructions Per Cycle 572system.cpu.ipc_total 0.241332 # IPC: Total IPC of All Threads 573system.cpu.int_regfile_reads 36473 # number of integer regfile reads 574system.cpu.int_regfile_writes 20293 # number of integer regfile writes 575system.cpu.misc_regfile_reads 8093 # number of misc regfile reads | 570system.cpu.cpi 4.111111 # CPI: Cycles Per Instruction 571system.cpu.cpi_total 4.111111 # CPI: Total CPI of All Threads 572system.cpu.ipc 0.243243 # IPC: Instructions Per Cycle 573system.cpu.ipc_total 0.243243 # IPC: Total IPC of All Threads 574system.cpu.int_regfile_reads 36173 # number of integer regfile reads 575system.cpu.int_regfile_writes 20126 # number of integer regfile writes 576system.cpu.misc_regfile_reads 7956 # number of misc regfile reads |
| 576system.cpu.misc_regfile_writes 569 # number of misc regfile writes | 577system.cpu.misc_regfile_writes 569 # number of misc regfile writes |
| 577system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states | 578system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states |
| 578system.cpu.dcache.tags.replacements 0 # number of replacements | 579system.cpu.dcache.tags.replacements 0 # number of replacements |
| 579system.cpu.dcache.tags.tagsinuse 99.156027 # Cycle average of tags in use 580system.cpu.dcache.tags.total_refs 4579 # Total number of references to valid blocks. | 580system.cpu.dcache.tags.tagsinuse 98.931439 # Cycle average of tags in use 581system.cpu.dcache.tags.total_refs 4528 # Total number of references to valid blocks. |
| 581system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. | 582system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. |
| 582system.cpu.dcache.tags.avg_refs 31.363014 # Average number of references to valid blocks. | 583system.cpu.dcache.tags.avg_refs 31.013699 # Average number of references to valid blocks. |
| 583system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 584system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 584system.cpu.dcache.tags.occ_blocks::cpu.data 99.156027 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.data 0.024208 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.024208 # Average percentage of cache occupancy | 585system.cpu.dcache.tags.occ_blocks::cpu.data 98.931439 # Average occupied blocks per requestor 586system.cpu.dcache.tags.occ_percent::cpu.data 0.024153 # Average percentage of cache occupancy 587system.cpu.dcache.tags.occ_percent::total 0.024153 # Average percentage of cache occupancy |
| 587system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 590system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id | 588system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 590system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 591system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id |
| 591system.cpu.dcache.tags.tag_accesses 10412 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 10412 # Number of data accesses 593system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 594system.cpu.dcache.ReadReq_hits::cpu.data 3540 # number of ReadReq hits 595system.cpu.dcache.ReadReq_hits::total 3540 # number of ReadReq hits | 592system.cpu.dcache.tags.tag_accesses 10292 # Number of tag accesses 593system.cpu.dcache.tags.data_accesses 10292 # Number of data accesses 594system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states 595system.cpu.dcache.ReadReq_hits::cpu.data 3489 # number of ReadReq hits 596system.cpu.dcache.ReadReq_hits::total 3489 # number of ReadReq hits |
| 596system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 597system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 598system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 599system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits | 597system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 598system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 599system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 600system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits |
| 600system.cpu.dcache.demand_hits::cpu.data 4573 # number of demand (read+write) hits 601system.cpu.dcache.demand_hits::total 4573 # number of demand (read+write) hits 602system.cpu.dcache.overall_hits::cpu.data 4573 # number of overall hits 603system.cpu.dcache.overall_hits::total 4573 # number of overall hits 604system.cpu.dcache.ReadReq_misses::cpu.data 145 # number of ReadReq misses 605system.cpu.dcache.ReadReq_misses::total 145 # number of ReadReq misses | 601system.cpu.dcache.demand_hits::cpu.data 4522 # number of demand (read+write) hits 602system.cpu.dcache.demand_hits::total 4522 # number of demand (read+write) hits 603system.cpu.dcache.overall_hits::cpu.data 4522 # number of overall hits 604system.cpu.dcache.overall_hits::total 4522 # number of overall hits 605system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses 606system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses |
| 606system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 607system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses | 607system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 608system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses |
| 608system.cpu.dcache.demand_misses::cpu.data 554 # number of demand (read+write) misses 609system.cpu.dcache.demand_misses::total 554 # number of demand (read+write) misses 610system.cpu.dcache.overall_misses::cpu.data 554 # number of overall misses 611system.cpu.dcache.overall_misses::total 554 # number of overall misses 612system.cpu.dcache.ReadReq_miss_latency::cpu.data 11443500 # number of ReadReq miss cycles 613system.cpu.dcache.ReadReq_miss_latency::total 11443500 # number of ReadReq miss cycles 614system.cpu.dcache.WriteReq_miss_latency::cpu.data 29003985 # number of WriteReq miss cycles 615system.cpu.dcache.WriteReq_miss_latency::total 29003985 # number of WriteReq miss cycles 616system.cpu.dcache.demand_miss_latency::cpu.data 40447485 # number of demand (read+write) miss cycles 617system.cpu.dcache.demand_miss_latency::total 40447485 # number of demand (read+write) miss cycles 618system.cpu.dcache.overall_miss_latency::cpu.data 40447485 # number of overall miss cycles 619system.cpu.dcache.overall_miss_latency::total 40447485 # number of overall miss cycles 620system.cpu.dcache.ReadReq_accesses::cpu.data 3685 # number of ReadReq accesses(hits+misses) 621system.cpu.dcache.ReadReq_accesses::total 3685 # number of ReadReq accesses(hits+misses) | 609system.cpu.dcache.demand_misses::cpu.data 545 # number of demand (read+write) misses 610system.cpu.dcache.demand_misses::total 545 # number of demand (read+write) misses 611system.cpu.dcache.overall_misses::cpu.data 545 # number of overall misses 612system.cpu.dcache.overall_misses::total 545 # number of overall misses 613system.cpu.dcache.ReadReq_miss_latency::cpu.data 10734500 # number of ReadReq miss cycles 614system.cpu.dcache.ReadReq_miss_latency::total 10734500 # number of ReadReq miss cycles 615system.cpu.dcache.WriteReq_miss_latency::cpu.data 29028485 # number of WriteReq miss cycles 616system.cpu.dcache.WriteReq_miss_latency::total 29028485 # number of WriteReq miss cycles 617system.cpu.dcache.demand_miss_latency::cpu.data 39762985 # number of demand (read+write) miss cycles 618system.cpu.dcache.demand_miss_latency::total 39762985 # number of demand (read+write) miss cycles 619system.cpu.dcache.overall_miss_latency::cpu.data 39762985 # number of overall miss cycles 620system.cpu.dcache.overall_miss_latency::total 39762985 # number of overall miss cycles 621system.cpu.dcache.ReadReq_accesses::cpu.data 3625 # number of ReadReq accesses(hits+misses) 622system.cpu.dcache.ReadReq_accesses::total 3625 # number of ReadReq accesses(hits+misses) |
| 622system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 623system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 624system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 625system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) | 623system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 624system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 625system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 626system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) |
| 626system.cpu.dcache.demand_accesses::cpu.data 5127 # number of demand (read+write) accesses 627system.cpu.dcache.demand_accesses::total 5127 # number of demand (read+write) accesses 628system.cpu.dcache.overall_accesses::cpu.data 5127 # number of overall (read+write) accesses 629system.cpu.dcache.overall_accesses::total 5127 # number of overall (read+write) accesses 630system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039349 # miss rate for ReadReq accesses 631system.cpu.dcache.ReadReq_miss_rate::total 0.039349 # miss rate for ReadReq accesses | 627system.cpu.dcache.demand_accesses::cpu.data 5067 # number of demand (read+write) accesses 628system.cpu.dcache.demand_accesses::total 5067 # number of demand (read+write) accesses 629system.cpu.dcache.overall_accesses::cpu.data 5067 # number of overall (read+write) accesses 630system.cpu.dcache.overall_accesses::total 5067 # number of overall (read+write) accesses 631system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037517 # miss rate for ReadReq accesses 632system.cpu.dcache.ReadReq_miss_rate::total 0.037517 # miss rate for ReadReq accesses |
| 632system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 633system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses | 633system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 634system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses |
| 634system.cpu.dcache.demand_miss_rate::cpu.data 0.108055 # miss rate for demand accesses 635system.cpu.dcache.demand_miss_rate::total 0.108055 # miss rate for demand accesses 636system.cpu.dcache.overall_miss_rate::cpu.data 0.108055 # miss rate for overall accesses 637system.cpu.dcache.overall_miss_rate::total 0.108055 # miss rate for overall accesses 638system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78920.689655 # average ReadReq miss latency 639system.cpu.dcache.ReadReq_avg_miss_latency::total 78920.689655 # average ReadReq miss latency 640system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70914.388753 # average WriteReq miss latency 641system.cpu.dcache.WriteReq_avg_miss_latency::total 70914.388753 # average WriteReq miss latency 642system.cpu.dcache.demand_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency 643system.cpu.dcache.demand_avg_miss_latency::total 73009.900722 # average overall miss latency 644system.cpu.dcache.overall_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency 645system.cpu.dcache.overall_avg_miss_latency::total 73009.900722 # average overall miss latency | 635system.cpu.dcache.demand_miss_rate::cpu.data 0.107559 # miss rate for demand accesses 636system.cpu.dcache.demand_miss_rate::total 0.107559 # miss rate for demand accesses 637system.cpu.dcache.overall_miss_rate::cpu.data 0.107559 # miss rate for overall accesses 638system.cpu.dcache.overall_miss_rate::total 0.107559 # miss rate for overall accesses 639system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78930.147059 # average ReadReq miss latency 640system.cpu.dcache.ReadReq_avg_miss_latency::total 78930.147059 # average ReadReq miss latency 641system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70974.290954 # average WriteReq miss latency 642system.cpu.dcache.WriteReq_avg_miss_latency::total 70974.290954 # average WriteReq miss latency 643system.cpu.dcache.demand_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency 644system.cpu.dcache.demand_avg_miss_latency::total 72959.605505 # average overall miss latency 645system.cpu.dcache.overall_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency 646system.cpu.dcache.overall_avg_miss_latency::total 72959.605505 # average overall miss latency |
| 646system.cpu.dcache.blocked_cycles::no_mshrs 1437 # number of cycles access was blocked 647system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 648system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked 649system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 650system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.631579 # average number of cycles each access was blocked 651system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 647system.cpu.dcache.blocked_cycles::no_mshrs 1437 # number of cycles access was blocked 648system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 649system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked 650system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 651system.cpu.dcache.avg_blocked_cycles::no_mshrs 75.631579 # average number of cycles each access was blocked 652system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 652system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits 653system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits | 653system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits 654system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits |
| 654system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 655system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits | 655system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 656system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits |
| 656system.cpu.dcache.demand_mshr_hits::cpu.data 406 # number of demand (read+write) MSHR hits 657system.cpu.dcache.demand_mshr_hits::total 406 # number of demand (read+write) MSHR hits 658system.cpu.dcache.overall_mshr_hits::cpu.data 406 # number of overall MSHR hits 659system.cpu.dcache.overall_mshr_hits::total 406 # number of overall MSHR hits | 657system.cpu.dcache.demand_mshr_hits::cpu.data 397 # number of demand (read+write) MSHR hits 658system.cpu.dcache.demand_mshr_hits::total 397 # number of demand (read+write) MSHR hits 659system.cpu.dcache.overall_mshr_hits::cpu.data 397 # number of overall MSHR hits 660system.cpu.dcache.overall_mshr_hits::total 397 # number of overall MSHR hits |
| 660system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 661system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 662system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 663system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 664system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 665system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 666system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 667system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses | 661system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 662system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 663system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 664system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 665system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 666system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 667system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 668system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses |
| 668system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6078000 # number of ReadReq MSHR miss cycles 669system.cpu.dcache.ReadReq_mshr_miss_latency::total 6078000 # number of ReadReq MSHR miss cycles 670system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6888000 # number of WriteReq MSHR miss cycles 671system.cpu.dcache.WriteReq_mshr_miss_latency::total 6888000 # number of WriteReq MSHR miss cycles 672system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12966000 # number of demand (read+write) MSHR miss cycles 673system.cpu.dcache.demand_mshr_miss_latency::total 12966000 # number of demand (read+write) MSHR miss cycles 674system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12966000 # number of overall MSHR miss cycles 675system.cpu.dcache.overall_mshr_miss_latency::total 12966000 # number of overall MSHR miss cycles 676system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017639 # mshr miss rate for ReadReq accesses 677system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017639 # mshr miss rate for ReadReq accesses | 669system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080000 # number of ReadReq MSHR miss cycles 670system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080000 # number of ReadReq MSHR miss cycles 671system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6906500 # number of WriteReq MSHR miss cycles 672system.cpu.dcache.WriteReq_mshr_miss_latency::total 6906500 # number of WriteReq MSHR miss cycles 673system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12986500 # number of demand (read+write) MSHR miss cycles 674system.cpu.dcache.demand_mshr_miss_latency::total 12986500 # number of demand (read+write) MSHR miss cycles 675system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12986500 # number of overall MSHR miss cycles 676system.cpu.dcache.overall_mshr_miss_latency::total 12986500 # number of overall MSHR miss cycles 677system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017931 # mshr miss rate for ReadReq accesses 678system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017931 # mshr miss rate for ReadReq accesses |
| 678system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 679system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses | 679system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 680system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses |
| 680system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for demand accesses 681system.cpu.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses 682system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for overall accesses 683system.cpu.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses 684system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93507.692308 # average ReadReq mshr miss latency 685system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93507.692308 # average ReadReq mshr miss latency 686system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82987.951807 # average WriteReq mshr miss latency 687system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82987.951807 # average WriteReq mshr miss latency 688system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency 690system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency 692system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states | 681system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for demand accesses 682system.cpu.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses 683system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for overall accesses 684system.cpu.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses 685system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93538.461538 # average ReadReq mshr miss latency 686system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93538.461538 # average ReadReq mshr miss latency 687system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83210.843373 # average WriteReq mshr miss latency 688system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83210.843373 # average WriteReq mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency 690system.cpu.dcache.demand_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency 692system.cpu.dcache.overall_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency 693system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states |
| 693system.cpu.icache.tags.replacements 0 # number of replacements | 694system.cpu.icache.tags.replacements 0 # number of replacements |
| 694system.cpu.icache.tags.tagsinuse 204.744610 # Cycle average of tags in use 695system.cpu.icache.tags.total_refs 6856 # Total number of references to valid blocks. 696system.cpu.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 697system.cpu.icache.tags.avg_refs 18.681199 # Average number of references to valid blocks. | 695system.cpu.icache.tags.tagsinuse 202.053622 # Cycle average of tags in use 696system.cpu.icache.tags.total_refs 6606 # Total number of references to valid blocks. 697system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 698system.cpu.icache.tags.avg_refs 18.098630 # Average number of references to valid blocks. |
| 698system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 699system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 699system.cpu.icache.tags.occ_blocks::cpu.inst 204.744610 # Average occupied blocks per requestor 700system.cpu.icache.tags.occ_percent::cpu.inst 0.099973 # Average percentage of cache occupancy 701system.cpu.icache.tags.occ_percent::total 0.099973 # Average percentage of cache occupancy 702system.cpu.icache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id 703system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 704system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id 705system.cpu.icache.tags.occ_task_id_percent::1024 0.179199 # Percentage of cache occupancy per task id 706system.cpu.icache.tags.tag_accesses 15259 # Number of tag accesses 707system.cpu.icache.tags.data_accesses 15259 # Number of data accesses 708system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 709system.cpu.icache.ReadReq_hits::cpu.inst 6856 # number of ReadReq hits 710system.cpu.icache.ReadReq_hits::total 6856 # number of ReadReq hits 711system.cpu.icache.demand_hits::cpu.inst 6856 # number of demand (read+write) hits 712system.cpu.icache.demand_hits::total 6856 # number of demand (read+write) hits 713system.cpu.icache.overall_hits::cpu.inst 6856 # number of overall hits 714system.cpu.icache.overall_hits::total 6856 # number of overall hits 715system.cpu.icache.ReadReq_misses::cpu.inst 590 # number of ReadReq misses 716system.cpu.icache.ReadReq_misses::total 590 # number of ReadReq misses 717system.cpu.icache.demand_misses::cpu.inst 590 # number of demand (read+write) misses 718system.cpu.icache.demand_misses::total 590 # number of demand (read+write) misses 719system.cpu.icache.overall_misses::cpu.inst 590 # number of overall misses 720system.cpu.icache.overall_misses::total 590 # number of overall misses 721system.cpu.icache.ReadReq_miss_latency::cpu.inst 45890500 # number of ReadReq miss cycles 722system.cpu.icache.ReadReq_miss_latency::total 45890500 # number of ReadReq miss cycles 723system.cpu.icache.demand_miss_latency::cpu.inst 45890500 # number of demand (read+write) miss cycles 724system.cpu.icache.demand_miss_latency::total 45890500 # number of demand (read+write) miss cycles 725system.cpu.icache.overall_miss_latency::cpu.inst 45890500 # number of overall miss cycles 726system.cpu.icache.overall_miss_latency::total 45890500 # number of overall miss cycles 727system.cpu.icache.ReadReq_accesses::cpu.inst 7446 # number of ReadReq accesses(hits+misses) 728system.cpu.icache.ReadReq_accesses::total 7446 # number of ReadReq accesses(hits+misses) 729system.cpu.icache.demand_accesses::cpu.inst 7446 # number of demand (read+write) accesses 730system.cpu.icache.demand_accesses::total 7446 # number of demand (read+write) accesses 731system.cpu.icache.overall_accesses::cpu.inst 7446 # number of overall (read+write) accesses 732system.cpu.icache.overall_accesses::total 7446 # number of overall (read+write) accesses 733system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.079237 # miss rate for ReadReq accesses 734system.cpu.icache.ReadReq_miss_rate::total 0.079237 # miss rate for ReadReq accesses 735system.cpu.icache.demand_miss_rate::cpu.inst 0.079237 # miss rate for demand accesses 736system.cpu.icache.demand_miss_rate::total 0.079237 # miss rate for demand accesses 737system.cpu.icache.overall_miss_rate::cpu.inst 0.079237 # miss rate for overall accesses 738system.cpu.icache.overall_miss_rate::total 0.079237 # miss rate for overall accesses 739system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77780.508475 # average ReadReq miss latency 740system.cpu.icache.ReadReq_avg_miss_latency::total 77780.508475 # average ReadReq miss latency 741system.cpu.icache.demand_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency 742system.cpu.icache.demand_avg_miss_latency::total 77780.508475 # average overall miss latency 743system.cpu.icache.overall_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency 744system.cpu.icache.overall_avg_miss_latency::total 77780.508475 # average overall miss latency 745system.cpu.icache.blocked_cycles::no_mshrs 123 # number of cycles access was blocked | 700system.cpu.icache.tags.occ_blocks::cpu.inst 202.053622 # Average occupied blocks per requestor 701system.cpu.icache.tags.occ_percent::cpu.inst 0.098659 # Average percentage of cache occupancy 702system.cpu.icache.tags.occ_percent::total 0.098659 # Average percentage of cache occupancy 703system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 704system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 705system.cpu.icache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id 706system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id 707system.cpu.icache.tags.tag_accesses 14747 # Number of tag accesses 708system.cpu.icache.tags.data_accesses 14747 # Number of data accesses 709system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states 710system.cpu.icache.ReadReq_hits::cpu.inst 6606 # number of ReadReq hits 711system.cpu.icache.ReadReq_hits::total 6606 # number of ReadReq hits 712system.cpu.icache.demand_hits::cpu.inst 6606 # number of demand (read+write) hits 713system.cpu.icache.demand_hits::total 6606 # number of demand (read+write) hits 714system.cpu.icache.overall_hits::cpu.inst 6606 # number of overall hits 715system.cpu.icache.overall_hits::total 6606 # number of overall hits 716system.cpu.icache.ReadReq_misses::cpu.inst 585 # number of ReadReq misses 717system.cpu.icache.ReadReq_misses::total 585 # number of ReadReq misses 718system.cpu.icache.demand_misses::cpu.inst 585 # number of demand (read+write) misses 719system.cpu.icache.demand_misses::total 585 # number of demand (read+write) misses 720system.cpu.icache.overall_misses::cpu.inst 585 # number of overall misses 721system.cpu.icache.overall_misses::total 585 # number of overall misses 722system.cpu.icache.ReadReq_miss_latency::cpu.inst 45161000 # number of ReadReq miss cycles 723system.cpu.icache.ReadReq_miss_latency::total 45161000 # number of ReadReq miss cycles 724system.cpu.icache.demand_miss_latency::cpu.inst 45161000 # number of demand (read+write) miss cycles 725system.cpu.icache.demand_miss_latency::total 45161000 # number of demand (read+write) miss cycles 726system.cpu.icache.overall_miss_latency::cpu.inst 45161000 # number of overall miss cycles 727system.cpu.icache.overall_miss_latency::total 45161000 # number of overall miss cycles 728system.cpu.icache.ReadReq_accesses::cpu.inst 7191 # number of ReadReq accesses(hits+misses) 729system.cpu.icache.ReadReq_accesses::total 7191 # number of ReadReq accesses(hits+misses) 730system.cpu.icache.demand_accesses::cpu.inst 7191 # number of demand (read+write) accesses 731system.cpu.icache.demand_accesses::total 7191 # number of demand (read+write) accesses 732system.cpu.icache.overall_accesses::cpu.inst 7191 # number of overall (read+write) accesses 733system.cpu.icache.overall_accesses::total 7191 # number of overall (read+write) accesses 734system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081352 # miss rate for ReadReq accesses 735system.cpu.icache.ReadReq_miss_rate::total 0.081352 # miss rate for ReadReq accesses 736system.cpu.icache.demand_miss_rate::cpu.inst 0.081352 # miss rate for demand accesses 737system.cpu.icache.demand_miss_rate::total 0.081352 # miss rate for demand accesses 738system.cpu.icache.overall_miss_rate::cpu.inst 0.081352 # miss rate for overall accesses 739system.cpu.icache.overall_miss_rate::total 0.081352 # miss rate for overall accesses 740system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77198.290598 # average ReadReq miss latency 741system.cpu.icache.ReadReq_avg_miss_latency::total 77198.290598 # average ReadReq miss latency 742system.cpu.icache.demand_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency 743system.cpu.icache.demand_avg_miss_latency::total 77198.290598 # average overall miss latency 744system.cpu.icache.overall_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency 745system.cpu.icache.overall_avg_miss_latency::total 77198.290598 # average overall miss latency 746system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked |
| 746system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 747system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 747system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked | 748system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked |
| 748system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 749system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 749system.cpu.icache.avg_blocked_cycles::no_mshrs 123 # average number of cycles each access was blocked | 750system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked |
| 750system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 751system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 751system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits 752system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits 753system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits 754system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits 755system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits 756system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits 757system.cpu.icache.ReadReq_mshr_misses::cpu.inst 367 # number of ReadReq MSHR misses 758system.cpu.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 759system.cpu.icache.demand_mshr_misses::cpu.inst 367 # number of demand (read+write) MSHR misses 760system.cpu.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 761system.cpu.icache.overall_mshr_misses::cpu.inst 367 # number of overall MSHR misses 762system.cpu.icache.overall_mshr_misses::total 367 # number of overall MSHR misses 763system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30255500 # number of ReadReq MSHR miss cycles 764system.cpu.icache.ReadReq_mshr_miss_latency::total 30255500 # number of ReadReq MSHR miss cycles 765system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30255500 # number of demand (read+write) MSHR miss cycles 766system.cpu.icache.demand_mshr_miss_latency::total 30255500 # number of demand (read+write) MSHR miss cycles 767system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30255500 # number of overall MSHR miss cycles 768system.cpu.icache.overall_mshr_miss_latency::total 30255500 # number of overall MSHR miss cycles 769system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for ReadReq accesses 770system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049288 # mshr miss rate for ReadReq accesses 771system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for demand accesses 772system.cpu.icache.demand_mshr_miss_rate::total 0.049288 # mshr miss rate for demand accesses 773system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for overall accesses 774system.cpu.icache.overall_mshr_miss_rate::total 0.049288 # mshr miss rate for overall accesses 775system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82440.054496 # average ReadReq mshr miss latency 776system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82440.054496 # average ReadReq mshr miss latency 777system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency 778system.cpu.icache.demand_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency 779system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency 780system.cpu.icache.overall_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency 781system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states | 752system.cpu.icache.ReadReq_mshr_hits::cpu.inst 220 # number of ReadReq MSHR hits 753system.cpu.icache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits 754system.cpu.icache.demand_mshr_hits::cpu.inst 220 # number of demand (read+write) MSHR hits 755system.cpu.icache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits 756system.cpu.icache.overall_mshr_hits::cpu.inst 220 # number of overall MSHR hits 757system.cpu.icache.overall_mshr_hits::total 220 # number of overall MSHR hits 758system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 759system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses 760system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 761system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses 762system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 763system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses 764system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29981500 # number of ReadReq MSHR miss cycles 765system.cpu.icache.ReadReq_mshr_miss_latency::total 29981500 # number of ReadReq MSHR miss cycles 766system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29981500 # number of demand (read+write) MSHR miss cycles 767system.cpu.icache.demand_mshr_miss_latency::total 29981500 # number of demand (read+write) MSHR miss cycles 768system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29981500 # number of overall MSHR miss cycles 769system.cpu.icache.overall_mshr_miss_latency::total 29981500 # number of overall MSHR miss cycles 770system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for ReadReq accesses 771system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050758 # mshr miss rate for ReadReq accesses 772system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for demand accesses 773system.cpu.icache.demand_mshr_miss_rate::total 0.050758 # mshr miss rate for demand accesses 774system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for overall accesses 775system.cpu.icache.overall_mshr_miss_rate::total 0.050758 # mshr miss rate for overall accesses 776system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82141.095890 # average ReadReq mshr miss latency 777system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82141.095890 # average ReadReq mshr miss latency 778system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency 779system.cpu.icache.demand_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency 780system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency 781system.cpu.icache.overall_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency 782system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states |
| 782system.cpu.l2cache.tags.replacements 0 # number of replacements | 783system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 783system.cpu.l2cache.tags.tagsinuse 303.310888 # Cycle average of tags in use | 784system.cpu.l2cache.tags.tagsinuse 300.398022 # Cycle average of tags in use |
| 784system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. | 785system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. |
| 785system.cpu.l2cache.tags.sampled_refs 511 # Sample count of references to valid blocks. 786system.cpu.l2cache.tags.avg_refs 0.003914 # Average number of references to valid blocks. | 786system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks. 787system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks. |
| 787system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 788system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 788system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.103605 # Average occupied blocks per requestor 789system.cpu.l2cache.tags.occ_blocks::cpu.data 99.207284 # Average occupied blocks per requestor 790system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006229 # Average percentage of cache occupancy 791system.cpu.l2cache.tags.occ_percent::cpu.data 0.003028 # Average percentage of cache occupancy 792system.cpu.l2cache.tags.occ_percent::total 0.009256 # Average percentage of cache occupancy 793system.cpu.l2cache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 794system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 795system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id 796system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015594 # Percentage of cache occupancy per task id 797system.cpu.l2cache.tags.tag_accesses 4631 # Number of tag accesses 798system.cpu.l2cache.tags.data_accesses 4631 # Number of data accesses 799system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states | 789system.cpu.l2cache.tags.occ_blocks::cpu.inst 201.414921 # Average occupied blocks per requestor 790system.cpu.l2cache.tags.occ_blocks::cpu.data 98.983101 # Average occupied blocks per requestor 791system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006147 # Average percentage of cache occupancy 792system.cpu.l2cache.tags.occ_percent::cpu.data 0.003021 # Average percentage of cache occupancy 793system.cpu.l2cache.tags.occ_percent::total 0.009167 # Average percentage of cache occupancy 794system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 795system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 796system.cpu.l2cache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id 797system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id 798system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses 799system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses 800system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states |
| 800system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 801system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 802system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 804system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 805system.cpu.l2cache.overall_hits::total 2 # number of overall hits 806system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 807system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses | 801system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 802system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 803system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 804system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 805system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 806system.cpu.l2cache.overall_hits::total 2 # number of overall hits 807system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 808system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses |
| 808system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 365 # number of ReadCleanReq misses 809system.cpu.l2cache.ReadCleanReq_misses::total 365 # number of ReadCleanReq misses | 809system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses 810system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses |
| 810system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses 811system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses | 811system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses 812system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses |
| 812system.cpu.l2cache.demand_misses::cpu.inst 365 # number of demand (read+write) misses | 813system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses |
| 813system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses | 814system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses |
| 814system.cpu.l2cache.demand_misses::total 513 # number of demand (read+write) misses 815system.cpu.l2cache.overall_misses::cpu.inst 365 # number of overall misses | 815system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses 816system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses |
| 816system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses | 817system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses |
| 817system.cpu.l2cache.overall_misses::total 513 # number of overall misses 818system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6762500 # number of ReadExReq miss cycles 819system.cpu.l2cache.ReadExReq_miss_latency::total 6762500 # number of ReadExReq miss cycles 820system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29682000 # number of ReadCleanReq miss cycles 821system.cpu.l2cache.ReadCleanReq_miss_latency::total 29682000 # number of ReadCleanReq miss cycles 822system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5983000 # number of ReadSharedReq miss cycles 823system.cpu.l2cache.ReadSharedReq_miss_latency::total 5983000 # number of ReadSharedReq miss cycles 824system.cpu.l2cache.demand_miss_latency::cpu.inst 29682000 # number of demand (read+write) miss cycles 825system.cpu.l2cache.demand_miss_latency::cpu.data 12745500 # number of demand (read+write) miss cycles 826system.cpu.l2cache.demand_miss_latency::total 42427500 # number of demand (read+write) miss cycles 827system.cpu.l2cache.overall_miss_latency::cpu.inst 29682000 # number of overall miss cycles 828system.cpu.l2cache.overall_miss_latency::cpu.data 12745500 # number of overall miss cycles 829system.cpu.l2cache.overall_miss_latency::total 42427500 # number of overall miss cycles | 818system.cpu.l2cache.overall_misses::total 511 # number of overall misses 819system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6781000 # number of ReadExReq miss cycles 820system.cpu.l2cache.ReadExReq_miss_latency::total 6781000 # number of ReadExReq miss cycles 821system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29411000 # number of ReadCleanReq miss cycles 822system.cpu.l2cache.ReadCleanReq_miss_latency::total 29411000 # number of ReadCleanReq miss cycles 823system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5985000 # number of ReadSharedReq miss cycles 824system.cpu.l2cache.ReadSharedReq_miss_latency::total 5985000 # number of ReadSharedReq miss cycles 825system.cpu.l2cache.demand_miss_latency::cpu.inst 29411000 # number of demand (read+write) miss cycles 826system.cpu.l2cache.demand_miss_latency::cpu.data 12766000 # number of demand (read+write) miss cycles 827system.cpu.l2cache.demand_miss_latency::total 42177000 # number of demand (read+write) miss cycles 828system.cpu.l2cache.overall_miss_latency::cpu.inst 29411000 # number of overall miss cycles 829system.cpu.l2cache.overall_miss_latency::cpu.data 12766000 # number of overall miss cycles 830system.cpu.l2cache.overall_miss_latency::total 42177000 # number of overall miss cycles |
| 830system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 831system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) | 831system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 832system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) |
| 832system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 367 # number of ReadCleanReq accesses(hits+misses) 833system.cpu.l2cache.ReadCleanReq_accesses::total 367 # number of ReadCleanReq accesses(hits+misses) | 833system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) 834system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) |
| 834system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) 835system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) | 835system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) 836system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) |
| 836system.cpu.l2cache.demand_accesses::cpu.inst 367 # number of demand (read+write) accesses | 837system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses |
| 837system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses | 838system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses |
| 838system.cpu.l2cache.demand_accesses::total 515 # number of demand (read+write) accesses 839system.cpu.l2cache.overall_accesses::cpu.inst 367 # number of overall (read+write) accesses | 839system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses 840system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses |
| 840system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses | 841system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses |
| 841system.cpu.l2cache.overall_accesses::total 515 # number of overall (read+write) accesses | 842system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses |
| 842system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 843system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 843system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 844system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 844system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994550 # miss rate for ReadCleanReq accesses 845system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994550 # miss rate for ReadCleanReq accesses | 845system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses 846system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses |
| 846system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 847system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses | 847system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 848system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses |
| 848system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994550 # miss rate for demand accesses | 849system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses |
| 849system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 850system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 850system.cpu.l2cache.demand_miss_rate::total 0.996117 # miss rate for demand accesses 851system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994550 # miss rate for overall accesses | 851system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses 852system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses |
| 852system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 853system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 853system.cpu.l2cache.overall_miss_rate::total 0.996117 # miss rate for overall accesses 854system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81475.903614 # average ReadExReq miss latency 855system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81475.903614 # average ReadExReq miss latency 856system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.547945 # average ReadCleanReq miss latency 857system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.547945 # average ReadCleanReq miss latency 858system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92046.153846 # average ReadSharedReq miss latency 859system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92046.153846 # average ReadSharedReq miss latency 860system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency 861system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency 862system.cpu.l2cache.demand_avg_miss_latency::total 82704.678363 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency 865system.cpu.l2cache.overall_avg_miss_latency::total 82704.678363 # average overall miss latency | 854system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses 855system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81698.795181 # average ReadExReq miss latency 856system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81698.795181 # average ReadExReq miss latency 857system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81022.038567 # average ReadCleanReq miss latency 858system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81022.038567 # average ReadCleanReq miss latency 859system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92076.923077 # average ReadSharedReq miss latency 860system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92076.923077 # average ReadSharedReq miss latency 861system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency 862system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency 863system.cpu.l2cache.demand_avg_miss_latency::total 82538.160470 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency 865system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency 866system.cpu.l2cache.overall_avg_miss_latency::total 82538.160470 # average overall miss latency |
| 866system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 867system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 869system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 870system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 871system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 872system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 873system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses | 867system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 869system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 870system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 871system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 872system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 873system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 874system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses |
| 874system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 365 # number of ReadCleanReq MSHR misses 875system.cpu.l2cache.ReadCleanReq_mshr_misses::total 365 # number of ReadCleanReq MSHR misses | 875system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 876system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses |
| 876system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses 877system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses | 877system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses 878system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses |
| 878system.cpu.l2cache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses | 879system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses |
| 879system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses | 880system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses |
| 880system.cpu.l2cache.demand_mshr_misses::total 513 # number of demand (read+write) MSHR misses 881system.cpu.l2cache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses | 881system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses 882system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses |
| 882system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses | 883system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses |
| 883system.cpu.l2cache.overall_mshr_misses::total 513 # number of overall MSHR misses 884system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5932500 # number of ReadExReq MSHR miss cycles 885system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5932500 # number of ReadExReq MSHR miss cycles 886system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26032000 # number of ReadCleanReq MSHR miss cycles 887system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26032000 # number of ReadCleanReq MSHR miss cycles 888system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5353000 # number of ReadSharedReq MSHR miss cycles 889system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5353000 # number of ReadSharedReq MSHR miss cycles 890system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26032000 # number of demand (read+write) MSHR miss cycles 891system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11285500 # number of demand (read+write) MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::total 37317500 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26032000 # number of overall MSHR miss cycles 894system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11285500 # number of overall MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::total 37317500 # number of overall MSHR miss cycles | 884system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses 885system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5951000 # number of ReadExReq MSHR miss cycles 886system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5951000 # number of ReadExReq MSHR miss cycles 887system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25781000 # number of ReadCleanReq MSHR miss cycles 888system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25781000 # number of ReadCleanReq MSHR miss cycles 889system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5355000 # number of ReadSharedReq MSHR miss cycles 890system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5355000 # number of ReadSharedReq MSHR miss cycles 891system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25781000 # number of demand (read+write) MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11306000 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.demand_mshr_miss_latency::total 37087000 # number of demand (read+write) MSHR miss cycles 894system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25781000 # number of overall MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11306000 # number of overall MSHR miss cycles 896system.cpu.l2cache.overall_mshr_miss_latency::total 37087000 # number of overall MSHR miss cycles |
| 896system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 897system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 897system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 898system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for ReadCleanReq accesses 899system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994550 # mshr miss rate for ReadCleanReq accesses | 899system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses 900system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses |
| 900system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 901system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses | 901system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 902system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses |
| 902system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for demand accesses | 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses |
| 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 904system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 904system.cpu.l2cache.demand_mshr_miss_rate::total 0.996117 # mshr miss rate for demand accesses 905system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for overall accesses | 905system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses |
| 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 907system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 907system.cpu.l2cache.overall_mshr_miss_rate::total 0.996117 # mshr miss rate for overall accesses 908system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614 # average ReadExReq mshr miss latency 909system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614 # average ReadExReq mshr miss latency 910system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71320.547945 # average ReadCleanReq mshr miss latency 911system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71320.547945 # average ReadCleanReq mshr miss latency 912system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154 # average ReadSharedReq mshr miss latency 913system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154 # average ReadSharedReq mshr miss latency 914system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency 917system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency 920system.cpu.toL2Bus.snoop_filter.tot_requests 515 # Total number of requests made to the snoop filter. | 908system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses 909system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71698.795181 # average ReadExReq mshr miss latency 910system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71698.795181 # average ReadExReq mshr miss latency 911system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71022.038567 # average ReadCleanReq mshr miss latency 912system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71022.038567 # average ReadCleanReq mshr miss latency 913system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82384.615385 # average ReadSharedReq mshr miss latency 914system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82384.615385 # average ReadSharedReq mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency 921system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. |
| 921system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 922system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 923system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 924system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 925system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 922system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 923system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 924system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 925system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 926system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 926system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 927system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution | 927system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states 928system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution |
| 928system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution | 929system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution |
| 930system.cpu.toL2Bus.trans_dist::ReadCleanReq 367 # Transaction distribution | 931system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution |
| 931system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution | 932system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution |
| 932system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734 # Packet count per connected master and slave (bytes) | 933system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) |
| 933system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) | 934system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) |
| 934system.cpu.toL2Bus.pkt_count::total 1028 # Packet count per connected master and slave (bytes) 935system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) | 935system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) 936system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) |
| 936system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) | 937system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) |
| 937system.cpu.toL2Bus.pkt_size::total 32832 # Cumulative packet size per connected master and slave (bytes) | 938system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) |
| 938system.cpu.toL2Bus.snoops 0 # Total snoops (count) 939system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) | 939system.cpu.toL2Bus.snoops 0 # Total snoops (count) 940system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 940system.cpu.toL2Bus.snoop_fanout::samples 515 # Request fanout histogram 941system.cpu.toL2Bus.snoop_fanout::mean 0.003883 # Request fanout histogram 942system.cpu.toL2Bus.snoop_fanout::stdev 0.062257 # Request fanout histogram | 941system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram 942system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram 943system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram |
| 943system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 944system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 944system.cpu.toL2Bus.snoop_fanout::0 513 99.61% 99.61% # Request fanout histogram | 945system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram |
| 945system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram 946system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 946system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram 947system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 948system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 949system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 950system.cpu.toL2Bus.snoop_fanout::total 515 # Request fanout histogram 951system.cpu.toL2Bus.reqLayer0.occupancy 257500 # Layer occupancy (ticks) | 951system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram 952system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) |
| 952system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) | 953system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) |
| 953system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) | 954system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) |
| 954system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) 955system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) 956system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 955system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) 956system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) 957system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 957system.membus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. | 958system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. |
| 958system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 959system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 960system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 961system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 962system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 959system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 960system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 961system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 962system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 963system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 963system.membus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 964system.membus.trans_dist::ReadResp 428 # Transaction distribution | 964system.membus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states 965system.membus.trans_dist::ReadResp 426 # Transaction distribution |
| 965system.membus.trans_dist::ReadExReq 83 # Transaction distribution 966system.membus.trans_dist::ReadExResp 83 # Transaction distribution | 966system.membus.trans_dist::ReadExReq 83 # Transaction distribution 967system.membus.trans_dist::ReadExResp 83 # Transaction distribution |
| 967system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution 968system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024 # Packet count per connected master and slave (bytes) 969system.membus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) 970system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32704 # Cumulative packet size per connected master and slave (bytes) 971system.membus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) | 968system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution 969system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) 970system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) 971system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) 972system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) |
| 972system.membus.snoops 0 # Total snoops (count) 973system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 973system.membus.snoops 0 # Total snoops (count) 974system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 974system.membus.snoop_fanout::samples 513 # Request fanout histogram | 975system.membus.snoop_fanout::samples 511 # Request fanout histogram |
| 975system.membus.snoop_fanout::mean 0 # Request fanout histogram 976system.membus.snoop_fanout::stdev 0 # Request fanout histogram 977system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 976system.membus.snoop_fanout::mean 0 # Request fanout histogram 977system.membus.snoop_fanout::stdev 0 # Request fanout histogram 978system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 978system.membus.snoop_fanout::0 513 100.00% 100.00% # Request fanout histogram | 979system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram |
| 979system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 980system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 981system.membus.snoop_fanout::min_value 0 # Request fanout histogram 982system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 980system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 981system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 982system.membus.snoop_fanout::min_value 0 # Request fanout histogram 983system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 983system.membus.snoop_fanout::total 513 # Request fanout histogram 984system.membus.reqLayer0.occupancy 627500 # Layer occupancy (ticks) | 984system.membus.snoop_fanout::total 511 # Request fanout histogram 985system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) |
| 985system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) | 986system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) |
| 986system.membus.respLayer1.occupancy 2707250 # Layer occupancy (ticks) | 987system.membus.respLayer1.occupancy 2697250 # Layer occupancy (ticks) |
| 987system.membus.respLayer1.utilization 9.1 # Layer utilization (%) 988 989---------- End Simulation Statistics ---------- | 988system.membus.respLayer1.utilization 9.1 # Layer utilization (%) 989 990---------- End Simulation Statistics ---------- |