| stats.txt (11687:b3d5f0e9e258) | stats.txt (11731:c473ca7cc650) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated 4sim_ticks 29908500 # Number of ticks simulated 5final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000030 # Number of seconds simulated 4sim_ticks 29908500 # Number of ticks simulated 5final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 90593 # Simulator instruction rate (inst/s) 8host_op_rate 90586 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 187662601 # Simulator tick rate (ticks/s) 10host_mem_usage 251772 # Number of bytes of host memory used 11host_seconds 0.16 # Real time elapsed on the host | 7host_inst_rate 19226 # Simulator instruction rate (inst/s) 8host_op_rate 19225 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 39829510 # Simulator tick rate (ticks/s) 10host_mem_usage 234412 # Number of bytes of host memory used 11host_seconds 0.75 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 23360 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 19system.physmem.bytes_read::total 32768 # Number of bytes read from this memory --- 176 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 12 15.38% 61.54% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 5 6.41% 67.95% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 6 7.69% 83.33% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.28% 84.62% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 23360 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 19system.physmem.bytes_read::total 32768 # Number of bytes read from this memory --- 176 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 12 15.38% 61.54% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 5 6.41% 67.95% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 5 6.41% 74.36% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 1 1.28% 75.64% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 6 7.69% 83.33% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.28% 84.62% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 12 15.38% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation |
| 204system.physmem.totQLat 6721500 # Total ticks spent queuing 205system.physmem.totMemAccLat 16340250 # Total ticks spent from burst creation until serviced by the DRAM | 204system.physmem.totQLat 6719500 # Total ticks spent queuing 205system.physmem.totMemAccLat 16338250 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 2565000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 2565000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 13102.34 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 13098.44 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 31852.34 # Average memory access latency per DRAM burst | 209system.physmem.avgMemAccLat 31848.44 # Average memory access latency per DRAM burst |
| 210system.physmem.avgRdBW 1097.75 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 1097.75 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 8.58 # Data bus utilization in percentage 216system.physmem.busUtilRead 8.58 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 58239.77 # Average gap between requests 225system.physmem.pageHitRate 82.65 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 357000 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 2199120 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) | 210system.physmem.avgRdBW 1097.75 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 1097.75 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 8.58 # Data bus utilization in percentage 216system.physmem.busUtilRead 8.58 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 58239.77 # Average gap between requests 225system.physmem.pageHitRate 82.65 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 357000 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 174570 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 2199120 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 3642300 # Energy for active background per rank (pJ) | 231system.physmem_0.actBackEnergy 3644010 # Energy for active background per rank (pJ) |
| 232system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) | 232system.physmem_0.preBackEnergy 63360 # Energy for precharge background per rank (pJ) |
| 233system.physmem_0.actPowerDownEnergy 9900900 # Energy for active power-down per rank (pJ) | 233system.physmem_0.actPowerDownEnergy 9899190 # Energy for active power-down per rank (pJ) |
| 234system.physmem_0.prePowerDownEnergy 16800 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 18197970 # Total energy per rank (pJ) 237system.physmem_0.averagePower 608.449701 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 21617000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 44000 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 7338500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 21705500 # Time in different power states 245system.physmem_1.actEnergy 278460 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) | 234system.physmem_0.prePowerDownEnergy 16800 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 18197970 # Total energy per rank (pJ) 237system.physmem_0.averagePower 608.449701 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 21617000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 44000 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 7338500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 21705500 # Time in different power states 245system.physmem_1.actEnergy 278460 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 121440 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1463700 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 2522250 # Energy for active background per rank (pJ) | 250system.physmem_1.actBackEnergy 2521680 # Energy for active background per rank (pJ) |
| 251system.physmem_1.preBackEnergy 86880 # Energy for precharge background per rank (pJ) | 251system.physmem_1.preBackEnergy 86880 # Energy for precharge background per rank (pJ) |
| 252system.physmem_1.actPowerDownEnergy 10426440 # Energy for active power-down per rank (pJ) | 252system.physmem_1.actPowerDownEnergy 10427010 # Energy for active power-down per rank (pJ) |
| 253system.physmem_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 17237010 # Total energy per rank (pJ) 256system.physmem_1.averagePower 576.319973 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 24154250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states --- 74 unchanged lines hidden (view full) --- 335system.cpu.rename.tempSerializingInsts 793 # count of temporary serializing insts renamed 336system.cpu.rename.skidInsts 4281 # count of insts added to the skid buffer 337system.cpu.memDep0.insertedLoads 4496 # Number of loads inserted to the mem dependence unit. 338system.cpu.memDep0.insertedStores 2885 # Number of stores inserted to the mem dependence unit. 339system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. 340system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. 341system.cpu.iq.iqInstsAdded 28450 # Number of instructions added to the IQ (excludes non-spec) 342system.cpu.iq.iqNonSpecInstsAdded 744 # Number of non-speculative instructions added to the IQ | 253system.physmem_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 17237010 # Total energy per rank (pJ) 256system.physmem_1.averagePower 576.319973 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 24154250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 143000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states --- 74 unchanged lines hidden (view full) --- 335system.cpu.rename.tempSerializingInsts 793 # count of temporary serializing insts renamed 336system.cpu.rename.skidInsts 4281 # count of insts added to the skid buffer 337system.cpu.memDep0.insertedLoads 4496 # Number of loads inserted to the mem dependence unit. 338system.cpu.memDep0.insertedStores 2885 # Number of stores inserted to the mem dependence unit. 339system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads. 340system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. 341system.cpu.iq.iqInstsAdded 28450 # Number of instructions added to the IQ (excludes non-spec) 342system.cpu.iq.iqNonSpecInstsAdded 744 # Number of non-speculative instructions added to the IQ |
| 343system.cpu.iq.iqInstsIssued 25032 # Number of instructions issued | 343system.cpu.iq.iqInstsIssued 25030 # Number of instructions issued |
| 344system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued 345system.cpu.iq.iqSquashedInstsExamined 14758 # Number of squashed instructions iterated over during squash; mainly for profiling | 344system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued 345system.cpu.iq.iqSquashedInstsExamined 14758 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 346system.cpu.iq.iqSquashedOperandsExamined 10993 # Number of squashed operands that are examined and possibly removed from graph | 346system.cpu.iq.iqSquashedOperandsExamined 11000 # Number of squashed operands that are examined and possibly removed from graph |
| 347system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed 348system.cpu.iq.issued_per_cycle::samples 35692 # Number of insts issued each cycle | 347system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed 348system.cpu.iq.issued_per_cycle::samples 35692 # Number of insts issued each cycle |
| 349system.cpu.iq.issued_per_cycle::mean 0.701334 # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::stdev 1.501806 # Number of insts issued each cycle | 349system.cpu.iq.issued_per_cycle::mean 0.701278 # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::stdev 1.501683 # Number of insts issued each cycle |
| 351system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 351system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 352system.cpu.iq.issued_per_cycle::0 26613 74.56% 74.56% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::1 3169 8.88% 83.44% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::2 1586 4.44% 87.89% # Number of insts issued each cycle | 352system.cpu.iq.issued_per_cycle::0 26611 74.56% 74.56% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::1 3173 8.89% 83.45% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::2 1585 4.44% 87.89% # Number of insts issued each cycle |
| 355system.cpu.iq.issued_per_cycle::3 1525 4.27% 92.16% # Number of insts issued each cycle | 355system.cpu.iq.issued_per_cycle::3 1525 4.27% 92.16% # Number of insts issued each cycle |
| 356system.cpu.iq.issued_per_cycle::4 1197 3.35% 95.51% # Number of insts issued each cycle | 356system.cpu.iq.issued_per_cycle::4 1196 3.35% 95.51% # Number of insts issued each cycle |
| 357system.cpu.iq.issued_per_cycle::5 748 2.10% 97.61% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::6 484 1.36% 98.96% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::7 276 0.77% 99.74% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::8 94 0.26% 100.00% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::total 35692 # Number of insts issued each cycle --- 31 unchanged lines hidden (view full) --- 396system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.07% # attempts to use FU when none available 397system.cpu.iq.fu_full::MemRead 53 17.15% 70.23% # attempts to use FU when none available 398system.cpu.iq.fu_full::MemWrite 92 29.77% 100.00% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 401system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 402system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 403system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 357system.cpu.iq.issued_per_cycle::5 748 2.10% 97.61% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::6 484 1.36% 98.96% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::7 276 0.77% 99.74% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::8 94 0.26% 100.00% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::total 35692 # Number of insts issued each cycle --- 31 unchanged lines hidden (view full) --- 396system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.07% # attempts to use FU when none available 397system.cpu.iq.fu_full::MemRead 53 17.15% 70.23% # attempts to use FU when none available 398system.cpu.iq.fu_full::MemWrite 92 29.77% 100.00% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 401system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 402system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 403system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 404system.cpu.iq.FU_type_0::IntAlu 18346 73.29% 73.29% # Type of FU issued | 404system.cpu.iq.FU_type_0::IntAlu 18344 73.29% 73.29% # Type of FU issued |
| 405system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.29% # Type of FU issued 406system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.29% # Type of FU issued 407system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.29% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.29% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.29% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.29% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.29% # Type of FU issued --- 20 unchanged lines hidden (view full) --- 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.29% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.29% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 4185 16.72% 90.01% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 2501 9.99% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 405system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.29% # Type of FU issued 406system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.29% # Type of FU issued 407system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.29% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.29% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.29% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.29% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.29% # Type of FU issued --- 20 unchanged lines hidden (view full) --- 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.29% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.29% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 4185 16.72% 90.01% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 2501 9.99% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 440system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 441system.cpu.iq.FU_type_0::total 25032 # Type of FU issued 442system.cpu.iq.rate 0.418469 # Inst issue rate | 441system.cpu.iq.FU_type_0::total 25030 # Type of FU issued 442system.cpu.iq.rate 0.418436 # Inst issue rate |
| 443system.cpu.iq.fu_busy_cnt 309 # FU busy when requested | 443system.cpu.iq.fu_busy_cnt 309 # FU busy when requested |
| 444system.cpu.iq.fu_busy_rate 0.012344 # FU busy rate (busy events/executed inst) 445system.cpu.iq.int_inst_queue_reads 86197 # Number of integer instruction queue reads | 444system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst) 445system.cpu.iq.int_inst_queue_reads 86193 # Number of integer instruction queue reads |
| 446system.cpu.iq.int_inst_queue_writes 43979 # Number of integer instruction queue writes | 446system.cpu.iq.int_inst_queue_writes 43979 # Number of integer instruction queue writes |
| 447system.cpu.iq.int_inst_queue_wakeup_accesses 22374 # Number of integer instruction queue wakeup accesses | 447system.cpu.iq.int_inst_queue_wakeup_accesses 22369 # Number of integer instruction queue wakeup accesses |
| 448system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 449system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 450system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 448system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 449system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 450system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 451system.cpu.iq.int_alu_accesses 25341 # Number of integer alu accesses | 451system.cpu.iq.int_alu_accesses 25339 # Number of integer alu accesses |
| 452system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 453system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores 454system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 455system.cpu.iew.lsq.thread0.squashedLoads 2271 # Number of loads squashed 456system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 457system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations 458system.cpu.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed 459system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address --- 8 unchanged lines hidden (view full) --- 468system.cpu.iew.iewDispSquashedInsts 235 # Number of squashed instructions skipped by dispatch 469system.cpu.iew.iewDispLoadInsts 4496 # Number of dispatched load instructions 470system.cpu.iew.iewDispStoreInsts 2885 # Number of dispatched store instructions 471system.cpu.iew.iewDispNonSpecInsts 744 # Number of dispatched non-speculative instructions 472system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 473system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 474system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations 475system.cpu.iew.predictedTakenIncorrect 207 # Number of branches that were predicted taken incorrectly | 452system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 453system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores 454system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 455system.cpu.iew.lsq.thread0.squashedLoads 2271 # Number of loads squashed 456system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 457system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations 458system.cpu.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed 459system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address --- 8 unchanged lines hidden (view full) --- 468system.cpu.iew.iewDispSquashedInsts 235 # Number of squashed instructions skipped by dispatch 469system.cpu.iew.iewDispLoadInsts 4496 # Number of dispatched load instructions 470system.cpu.iew.iewDispStoreInsts 2885 # Number of dispatched store instructions 471system.cpu.iew.iewDispNonSpecInsts 744 # Number of dispatched non-speculative instructions 472system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 473system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 474system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations 475system.cpu.iew.predictedTakenIncorrect 207 # Number of branches that were predicted taken incorrectly |
| 476system.cpu.iew.predictedNotTakenIncorrect 1575 # Number of branches that were predicted not taken incorrectly 477system.cpu.iew.branchMispredicts 1782 # Number of branch mispredicts detected at execute 478system.cpu.iew.iewExecutedInsts 23436 # Number of executed instructions | 476system.cpu.iew.predictedNotTakenIncorrect 1574 # Number of branches that were predicted not taken incorrectly 477system.cpu.iew.branchMispredicts 1781 # Number of branch mispredicts detected at execute 478system.cpu.iew.iewExecutedInsts 23432 # Number of executed instructions |
| 479system.cpu.iew.iewExecLoadInsts 3882 # Number of load instructions executed | 479system.cpu.iew.iewExecLoadInsts 3882 # Number of load instructions executed |
| 480system.cpu.iew.iewExecSquashedInsts 1596 # Number of squashed instructions skipped in execute | 480system.cpu.iew.iewExecSquashedInsts 1598 # Number of squashed instructions skipped in execute |
| 481system.cpu.iew.exec_swp 0 # number of swp insts executed 482system.cpu.iew.exec_nop 1532 # number of nop insts executed | 481system.cpu.iew.exec_swp 0 # number of swp insts executed 482system.cpu.iew.exec_nop 1532 # number of nop insts executed |
| 483system.cpu.iew.exec_refs 6191 # number of memory reference insts executed 484system.cpu.iew.exec_branches 4986 # Number of branches executed 485system.cpu.iew.exec_stores 2309 # Number of stores executed 486system.cpu.iew.exec_rate 0.391788 # Inst execution rate 487system.cpu.iew.wb_sent 22845 # cumulative count of insts sent to commit 488system.cpu.iew.wb_count 22374 # cumulative count of insts written-back 489system.cpu.iew.wb_producers 10411 # num instructions producing a value 490system.cpu.iew.wb_consumers 13650 # num instructions consuming a value 491system.cpu.iew.wb_rate 0.374035 # insts written-back per cycle 492system.cpu.iew.wb_fanout 0.762711 # average fanout of values written-back | 483system.cpu.iew.exec_refs 6190 # number of memory reference insts executed 484system.cpu.iew.exec_branches 4984 # Number of branches executed 485system.cpu.iew.exec_stores 2308 # Number of stores executed 486system.cpu.iew.exec_rate 0.391722 # Inst execution rate 487system.cpu.iew.wb_sent 22840 # cumulative count of insts sent to commit 488system.cpu.iew.wb_count 22369 # cumulative count of insts written-back 489system.cpu.iew.wb_producers 10409 # num instructions producing a value 490system.cpu.iew.wb_consumers 13648 # num instructions consuming a value 491system.cpu.iew.wb_rate 0.373951 # insts written-back per cycle 492system.cpu.iew.wb_fanout 0.762676 # average fanout of values written-back |
| 493system.cpu.commit.commitSquashedInsts 15475 # The number of squashed insts skipped by commit 494system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 495system.cpu.commit.branchMispredicts 1435 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 32615 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 0.464878 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 1.257144 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::0 25974 79.64% 79.64% # Number of insts commited each cycle --- 64 unchanged lines hidden (view full) --- 565system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself 566system.cpu.idleCycles 24126 # Total number of cycles that the CPU has spent unscheduled due to idling 567system.cpu.committedInsts 14436 # Number of Instructions Simulated 568system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 569system.cpu.cpi 4.143669 # CPI: Cycles Per Instruction 570system.cpu.cpi_total 4.143669 # CPI: Total CPI of All Threads 571system.cpu.ipc 0.241332 # IPC: Instructions Per Cycle 572system.cpu.ipc_total 0.241332 # IPC: Total IPC of All Threads | 493system.cpu.commit.commitSquashedInsts 15475 # The number of squashed insts skipped by commit 494system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 495system.cpu.commit.branchMispredicts 1435 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 32615 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 0.464878 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 1.257144 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::0 25974 79.64% 79.64% # Number of insts commited each cycle --- 64 unchanged lines hidden (view full) --- 565system.cpu.timesIdled 194 # Number of times that the entire CPU went into an idle state and unscheduled itself 566system.cpu.idleCycles 24126 # Total number of cycles that the CPU has spent unscheduled due to idling 567system.cpu.committedInsts 14436 # Number of Instructions Simulated 568system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 569system.cpu.cpi 4.143669 # CPI: Cycles Per Instruction 570system.cpu.cpi_total 4.143669 # CPI: Total CPI of All Threads 571system.cpu.ipc 0.241332 # IPC: Instructions Per Cycle 572system.cpu.ipc_total 0.241332 # IPC: Total IPC of All Threads |
| 573system.cpu.int_regfile_reads 36480 # number of integer regfile reads 574system.cpu.int_regfile_writes 20296 # number of integer regfile writes 575system.cpu.misc_regfile_reads 8094 # number of misc regfile reads | 573system.cpu.int_regfile_reads 36473 # number of integer regfile reads 574system.cpu.int_regfile_writes 20293 # number of integer regfile writes 575system.cpu.misc_regfile_reads 8093 # number of misc regfile reads |
| 576system.cpu.misc_regfile_writes 569 # number of misc regfile writes 577system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 578system.cpu.dcache.tags.replacements 0 # number of replacements | 576system.cpu.misc_regfile_writes 569 # number of misc regfile writes 577system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 578system.cpu.dcache.tags.replacements 0 # number of replacements |
| 579system.cpu.dcache.tags.tagsinuse 99.158435 # Cycle average of tags in use | 579system.cpu.dcache.tags.tagsinuse 99.156027 # Cycle average of tags in use |
| 580system.cpu.dcache.tags.total_refs 4579 # Total number of references to valid blocks. 581system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 582system.cpu.dcache.tags.avg_refs 31.363014 # Average number of references to valid blocks. 583system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 580system.cpu.dcache.tags.total_refs 4579 # Total number of references to valid blocks. 581system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 582system.cpu.dcache.tags.avg_refs 31.363014 # Average number of references to valid blocks. 583system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 584system.cpu.dcache.tags.occ_blocks::cpu.data 99.158435 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.data 0.024209 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.024209 # Average percentage of cache occupancy | 584system.cpu.dcache.tags.occ_blocks::cpu.data 99.156027 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.data 0.024208 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.024208 # Average percentage of cache occupancy |
| 587system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 590system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 591system.cpu.dcache.tags.tag_accesses 10412 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 10412 # Number of data accesses 593system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 594system.cpu.dcache.ReadReq_hits::cpu.data 3540 # number of ReadReq hits --- 91 unchanged lines hidden (view full) --- 686system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82987.951807 # average WriteReq mshr miss latency 687system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82987.951807 # average WriteReq mshr miss latency 688system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency 690system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency 692system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 693system.cpu.icache.tags.replacements 0 # number of replacements | 587system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 590system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 591system.cpu.dcache.tags.tag_accesses 10412 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 10412 # Number of data accesses 593system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 594system.cpu.dcache.ReadReq_hits::cpu.data 3540 # number of ReadReq hits --- 91 unchanged lines hidden (view full) --- 686system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82987.951807 # average WriteReq mshr miss latency 687system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82987.951807 # average WriteReq mshr miss latency 688system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency 689system.cpu.dcache.demand_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency 690system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency 691system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency 692system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 693system.cpu.icache.tags.replacements 0 # number of replacements |
| 694system.cpu.icache.tags.tagsinuse 204.747820 # Cycle average of tags in use | 694system.cpu.icache.tags.tagsinuse 204.744610 # Cycle average of tags in use |
| 695system.cpu.icache.tags.total_refs 6856 # Total number of references to valid blocks. 696system.cpu.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 697system.cpu.icache.tags.avg_refs 18.681199 # Average number of references to valid blocks. 698system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 695system.cpu.icache.tags.total_refs 6856 # Total number of references to valid blocks. 696system.cpu.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. 697system.cpu.icache.tags.avg_refs 18.681199 # Average number of references to valid blocks. 698system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 699system.cpu.icache.tags.occ_blocks::cpu.inst 204.747820 # Average occupied blocks per requestor 700system.cpu.icache.tags.occ_percent::cpu.inst 0.099975 # Average percentage of cache occupancy 701system.cpu.icache.tags.occ_percent::total 0.099975 # Average percentage of cache occupancy | 699system.cpu.icache.tags.occ_blocks::cpu.inst 204.744610 # Average occupied blocks per requestor 700system.cpu.icache.tags.occ_percent::cpu.inst 0.099973 # Average percentage of cache occupancy 701system.cpu.icache.tags.occ_percent::total 0.099973 # Average percentage of cache occupancy |
| 702system.cpu.icache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id 703system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 704system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id 705system.cpu.icache.tags.occ_task_id_percent::1024 0.179199 # Percentage of cache occupancy per task id 706system.cpu.icache.tags.tag_accesses 15259 # Number of tag accesses 707system.cpu.icache.tags.data_accesses 15259 # Number of data accesses 708system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 709system.cpu.icache.ReadReq_hits::cpu.inst 6856 # number of ReadReq hits 710system.cpu.icache.ReadReq_hits::total 6856 # number of ReadReq hits 711system.cpu.icache.demand_hits::cpu.inst 6856 # number of demand (read+write) hits 712system.cpu.icache.demand_hits::total 6856 # number of demand (read+write) hits 713system.cpu.icache.overall_hits::cpu.inst 6856 # number of overall hits 714system.cpu.icache.overall_hits::total 6856 # number of overall hits 715system.cpu.icache.ReadReq_misses::cpu.inst 590 # number of ReadReq misses 716system.cpu.icache.ReadReq_misses::total 590 # number of ReadReq misses 717system.cpu.icache.demand_misses::cpu.inst 590 # number of demand (read+write) misses 718system.cpu.icache.demand_misses::total 590 # number of demand (read+write) misses 719system.cpu.icache.overall_misses::cpu.inst 590 # number of overall misses 720system.cpu.icache.overall_misses::total 590 # number of overall misses | 702system.cpu.icache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id 703system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 704system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id 705system.cpu.icache.tags.occ_task_id_percent::1024 0.179199 # Percentage of cache occupancy per task id 706system.cpu.icache.tags.tag_accesses 15259 # Number of tag accesses 707system.cpu.icache.tags.data_accesses 15259 # Number of data accesses 708system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 709system.cpu.icache.ReadReq_hits::cpu.inst 6856 # number of ReadReq hits 710system.cpu.icache.ReadReq_hits::total 6856 # number of ReadReq hits 711system.cpu.icache.demand_hits::cpu.inst 6856 # number of demand (read+write) hits 712system.cpu.icache.demand_hits::total 6856 # number of demand (read+write) hits 713system.cpu.icache.overall_hits::cpu.inst 6856 # number of overall hits 714system.cpu.icache.overall_hits::total 6856 # number of overall hits 715system.cpu.icache.ReadReq_misses::cpu.inst 590 # number of ReadReq misses 716system.cpu.icache.ReadReq_misses::total 590 # number of ReadReq misses 717system.cpu.icache.demand_misses::cpu.inst 590 # number of demand (read+write) misses 718system.cpu.icache.demand_misses::total 590 # number of demand (read+write) misses 719system.cpu.icache.overall_misses::cpu.inst 590 # number of overall misses 720system.cpu.icache.overall_misses::total 590 # number of overall misses |
| 721system.cpu.icache.ReadReq_miss_latency::cpu.inst 45891500 # number of ReadReq miss cycles 722system.cpu.icache.ReadReq_miss_latency::total 45891500 # number of ReadReq miss cycles 723system.cpu.icache.demand_miss_latency::cpu.inst 45891500 # number of demand (read+write) miss cycles 724system.cpu.icache.demand_miss_latency::total 45891500 # number of demand (read+write) miss cycles 725system.cpu.icache.overall_miss_latency::cpu.inst 45891500 # number of overall miss cycles 726system.cpu.icache.overall_miss_latency::total 45891500 # number of overall miss cycles | 721system.cpu.icache.ReadReq_miss_latency::cpu.inst 45890500 # number of ReadReq miss cycles 722system.cpu.icache.ReadReq_miss_latency::total 45890500 # number of ReadReq miss cycles 723system.cpu.icache.demand_miss_latency::cpu.inst 45890500 # number of demand (read+write) miss cycles 724system.cpu.icache.demand_miss_latency::total 45890500 # number of demand (read+write) miss cycles 725system.cpu.icache.overall_miss_latency::cpu.inst 45890500 # number of overall miss cycles 726system.cpu.icache.overall_miss_latency::total 45890500 # number of overall miss cycles |
| 727system.cpu.icache.ReadReq_accesses::cpu.inst 7446 # number of ReadReq accesses(hits+misses) 728system.cpu.icache.ReadReq_accesses::total 7446 # number of ReadReq accesses(hits+misses) 729system.cpu.icache.demand_accesses::cpu.inst 7446 # number of demand (read+write) accesses 730system.cpu.icache.demand_accesses::total 7446 # number of demand (read+write) accesses 731system.cpu.icache.overall_accesses::cpu.inst 7446 # number of overall (read+write) accesses 732system.cpu.icache.overall_accesses::total 7446 # number of overall (read+write) accesses 733system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.079237 # miss rate for ReadReq accesses 734system.cpu.icache.ReadReq_miss_rate::total 0.079237 # miss rate for ReadReq accesses 735system.cpu.icache.demand_miss_rate::cpu.inst 0.079237 # miss rate for demand accesses 736system.cpu.icache.demand_miss_rate::total 0.079237 # miss rate for demand accesses 737system.cpu.icache.overall_miss_rate::cpu.inst 0.079237 # miss rate for overall accesses 738system.cpu.icache.overall_miss_rate::total 0.079237 # miss rate for overall accesses | 727system.cpu.icache.ReadReq_accesses::cpu.inst 7446 # number of ReadReq accesses(hits+misses) 728system.cpu.icache.ReadReq_accesses::total 7446 # number of ReadReq accesses(hits+misses) 729system.cpu.icache.demand_accesses::cpu.inst 7446 # number of demand (read+write) accesses 730system.cpu.icache.demand_accesses::total 7446 # number of demand (read+write) accesses 731system.cpu.icache.overall_accesses::cpu.inst 7446 # number of overall (read+write) accesses 732system.cpu.icache.overall_accesses::total 7446 # number of overall (read+write) accesses 733system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.079237 # miss rate for ReadReq accesses 734system.cpu.icache.ReadReq_miss_rate::total 0.079237 # miss rate for ReadReq accesses 735system.cpu.icache.demand_miss_rate::cpu.inst 0.079237 # miss rate for demand accesses 736system.cpu.icache.demand_miss_rate::total 0.079237 # miss rate for demand accesses 737system.cpu.icache.overall_miss_rate::cpu.inst 0.079237 # miss rate for overall accesses 738system.cpu.icache.overall_miss_rate::total 0.079237 # miss rate for overall accesses |
| 739system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77782.203390 # average ReadReq miss latency 740system.cpu.icache.ReadReq_avg_miss_latency::total 77782.203390 # average ReadReq miss latency 741system.cpu.icache.demand_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency 742system.cpu.icache.demand_avg_miss_latency::total 77782.203390 # average overall miss latency 743system.cpu.icache.overall_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency 744system.cpu.icache.overall_avg_miss_latency::total 77782.203390 # average overall miss latency | 739system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77780.508475 # average ReadReq miss latency 740system.cpu.icache.ReadReq_avg_miss_latency::total 77780.508475 # average ReadReq miss latency 741system.cpu.icache.demand_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency 742system.cpu.icache.demand_avg_miss_latency::total 77780.508475 # average overall miss latency 743system.cpu.icache.overall_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency 744system.cpu.icache.overall_avg_miss_latency::total 77780.508475 # average overall miss latency |
| 745system.cpu.icache.blocked_cycles::no_mshrs 123 # number of cycles access was blocked 746system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 747system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 748system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 749system.cpu.icache.avg_blocked_cycles::no_mshrs 123 # average number of cycles each access was blocked 750system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 751system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits 752system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits 753system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits 754system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits 755system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits 756system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits 757system.cpu.icache.ReadReq_mshr_misses::cpu.inst 367 # number of ReadReq MSHR misses 758system.cpu.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 759system.cpu.icache.demand_mshr_misses::cpu.inst 367 # number of demand (read+write) MSHR misses 760system.cpu.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 761system.cpu.icache.overall_mshr_misses::cpu.inst 367 # number of overall MSHR misses 762system.cpu.icache.overall_mshr_misses::total 367 # number of overall MSHR misses | 745system.cpu.icache.blocked_cycles::no_mshrs 123 # number of cycles access was blocked 746system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 747system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 748system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 749system.cpu.icache.avg_blocked_cycles::no_mshrs 123 # average number of cycles each access was blocked 750system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 751system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits 752system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits 753system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits 754system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits 755system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits 756system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits 757system.cpu.icache.ReadReq_mshr_misses::cpu.inst 367 # number of ReadReq MSHR misses 758system.cpu.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses 759system.cpu.icache.demand_mshr_misses::cpu.inst 367 # number of demand (read+write) MSHR misses 760system.cpu.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses 761system.cpu.icache.overall_mshr_misses::cpu.inst 367 # number of overall MSHR misses 762system.cpu.icache.overall_mshr_misses::total 367 # number of overall MSHR misses |
| 763system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30257500 # number of ReadReq MSHR miss cycles 764system.cpu.icache.ReadReq_mshr_miss_latency::total 30257500 # number of ReadReq MSHR miss cycles 765system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30257500 # number of demand (read+write) MSHR miss cycles 766system.cpu.icache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles 767system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30257500 # number of overall MSHR miss cycles 768system.cpu.icache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles | 763system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30255500 # number of ReadReq MSHR miss cycles 764system.cpu.icache.ReadReq_mshr_miss_latency::total 30255500 # number of ReadReq MSHR miss cycles 765system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30255500 # number of demand (read+write) MSHR miss cycles 766system.cpu.icache.demand_mshr_miss_latency::total 30255500 # number of demand (read+write) MSHR miss cycles 767system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30255500 # number of overall MSHR miss cycles 768system.cpu.icache.overall_mshr_miss_latency::total 30255500 # number of overall MSHR miss cycles |
| 769system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for ReadReq accesses 770system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049288 # mshr miss rate for ReadReq accesses 771system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for demand accesses 772system.cpu.icache.demand_mshr_miss_rate::total 0.049288 # mshr miss rate for demand accesses 773system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for overall accesses 774system.cpu.icache.overall_mshr_miss_rate::total 0.049288 # mshr miss rate for overall accesses | 769system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for ReadReq accesses 770system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049288 # mshr miss rate for ReadReq accesses 771system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for demand accesses 772system.cpu.icache.demand_mshr_miss_rate::total 0.049288 # mshr miss rate for demand accesses 773system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for overall accesses 774system.cpu.icache.overall_mshr_miss_rate::total 0.049288 # mshr miss rate for overall accesses |
| 775system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82445.504087 # average ReadReq mshr miss latency 776system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82445.504087 # average ReadReq mshr miss latency 777system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency 778system.cpu.icache.demand_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency 779system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency 780system.cpu.icache.overall_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency | 775system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82440.054496 # average ReadReq mshr miss latency 776system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82440.054496 # average ReadReq mshr miss latency 777system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency 778system.cpu.icache.demand_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency 779system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency 780system.cpu.icache.overall_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency |
| 781system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 782system.cpu.l2cache.tags.replacements 0 # number of replacements | 781system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 782system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 783system.cpu.l2cache.tags.tagsinuse 303.316506 # Cycle average of tags in use | 783system.cpu.l2cache.tags.tagsinuse 303.310888 # Cycle average of tags in use |
| 784system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 785system.cpu.l2cache.tags.sampled_refs 511 # Sample count of references to valid blocks. 786system.cpu.l2cache.tags.avg_refs 0.003914 # Average number of references to valid blocks. 787system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 784system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 785system.cpu.l2cache.tags.sampled_refs 511 # Sample count of references to valid blocks. 786system.cpu.l2cache.tags.avg_refs 0.003914 # Average number of references to valid blocks. 787system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 788system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.106814 # Average occupied blocks per requestor 789system.cpu.l2cache.tags.occ_blocks::cpu.data 99.209691 # Average occupied blocks per requestor | 788system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.103605 # Average occupied blocks per requestor 789system.cpu.l2cache.tags.occ_blocks::cpu.data 99.207284 # Average occupied blocks per requestor |
| 790system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006229 # Average percentage of cache occupancy 791system.cpu.l2cache.tags.occ_percent::cpu.data 0.003028 # Average percentage of cache occupancy 792system.cpu.l2cache.tags.occ_percent::total 0.009256 # Average percentage of cache occupancy 793system.cpu.l2cache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 794system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 795system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id 796system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015594 # Percentage of cache occupancy per task id 797system.cpu.l2cache.tags.tag_accesses 4631 # Number of tag accesses --- 14 unchanged lines hidden (view full) --- 812system.cpu.l2cache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 813system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses 814system.cpu.l2cache.demand_misses::total 513 # number of demand (read+write) misses 815system.cpu.l2cache.overall_misses::cpu.inst 365 # number of overall misses 816system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses 817system.cpu.l2cache.overall_misses::total 513 # number of overall misses 818system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6762500 # number of ReadExReq miss cycles 819system.cpu.l2cache.ReadExReq_miss_latency::total 6762500 # number of ReadExReq miss cycles | 790system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006229 # Average percentage of cache occupancy 791system.cpu.l2cache.tags.occ_percent::cpu.data 0.003028 # Average percentage of cache occupancy 792system.cpu.l2cache.tags.occ_percent::total 0.009256 # Average percentage of cache occupancy 793system.cpu.l2cache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 794system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 795system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id 796system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015594 # Percentage of cache occupancy per task id 797system.cpu.l2cache.tags.tag_accesses 4631 # Number of tag accesses --- 14 unchanged lines hidden (view full) --- 812system.cpu.l2cache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 813system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses 814system.cpu.l2cache.demand_misses::total 513 # number of demand (read+write) misses 815system.cpu.l2cache.overall_misses::cpu.inst 365 # number of overall misses 816system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses 817system.cpu.l2cache.overall_misses::total 513 # number of overall misses 818system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6762500 # number of ReadExReq miss cycles 819system.cpu.l2cache.ReadExReq_miss_latency::total 6762500 # number of ReadExReq miss cycles |
| 820system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29684000 # number of ReadCleanReq miss cycles 821system.cpu.l2cache.ReadCleanReq_miss_latency::total 29684000 # number of ReadCleanReq miss cycles | 820system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29682000 # number of ReadCleanReq miss cycles 821system.cpu.l2cache.ReadCleanReq_miss_latency::total 29682000 # number of ReadCleanReq miss cycles |
| 822system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5983000 # number of ReadSharedReq miss cycles 823system.cpu.l2cache.ReadSharedReq_miss_latency::total 5983000 # number of ReadSharedReq miss cycles | 822system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5983000 # number of ReadSharedReq miss cycles 823system.cpu.l2cache.ReadSharedReq_miss_latency::total 5983000 # number of ReadSharedReq miss cycles |
| 824system.cpu.l2cache.demand_miss_latency::cpu.inst 29684000 # number of demand (read+write) miss cycles | 824system.cpu.l2cache.demand_miss_latency::cpu.inst 29682000 # number of demand (read+write) miss cycles |
| 825system.cpu.l2cache.demand_miss_latency::cpu.data 12745500 # number of demand (read+write) miss cycles | 825system.cpu.l2cache.demand_miss_latency::cpu.data 12745500 # number of demand (read+write) miss cycles |
| 826system.cpu.l2cache.demand_miss_latency::total 42429500 # number of demand (read+write) miss cycles 827system.cpu.l2cache.overall_miss_latency::cpu.inst 29684000 # number of overall miss cycles | 826system.cpu.l2cache.demand_miss_latency::total 42427500 # number of demand (read+write) miss cycles 827system.cpu.l2cache.overall_miss_latency::cpu.inst 29682000 # number of overall miss cycles |
| 828system.cpu.l2cache.overall_miss_latency::cpu.data 12745500 # number of overall miss cycles | 828system.cpu.l2cache.overall_miss_latency::cpu.data 12745500 # number of overall miss cycles |
| 829system.cpu.l2cache.overall_miss_latency::total 42429500 # number of overall miss cycles | 829system.cpu.l2cache.overall_miss_latency::total 42427500 # number of overall miss cycles |
| 830system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 831system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 832system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 367 # number of ReadCleanReq accesses(hits+misses) 833system.cpu.l2cache.ReadCleanReq_accesses::total 367 # number of ReadCleanReq accesses(hits+misses) 834system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) 835system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) 836system.cpu.l2cache.demand_accesses::cpu.inst 367 # number of demand (read+write) accesses 837system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses --- 10 unchanged lines hidden (view full) --- 848system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994550 # miss rate for demand accesses 849system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 850system.cpu.l2cache.demand_miss_rate::total 0.996117 # miss rate for demand accesses 851system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994550 # miss rate for overall accesses 852system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 853system.cpu.l2cache.overall_miss_rate::total 0.996117 # miss rate for overall accesses 854system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81475.903614 # average ReadExReq miss latency 855system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81475.903614 # average ReadExReq miss latency | 830system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 831system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 832system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 367 # number of ReadCleanReq accesses(hits+misses) 833system.cpu.l2cache.ReadCleanReq_accesses::total 367 # number of ReadCleanReq accesses(hits+misses) 834system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) 835system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) 836system.cpu.l2cache.demand_accesses::cpu.inst 367 # number of demand (read+write) accesses 837system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses --- 10 unchanged lines hidden (view full) --- 848system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994550 # miss rate for demand accesses 849system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 850system.cpu.l2cache.demand_miss_rate::total 0.996117 # miss rate for demand accesses 851system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994550 # miss rate for overall accesses 852system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 853system.cpu.l2cache.overall_miss_rate::total 0.996117 # miss rate for overall accesses 854system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81475.903614 # average ReadExReq miss latency 855system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81475.903614 # average ReadExReq miss latency |
| 856system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81326.027397 # average ReadCleanReq miss latency 857system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81326.027397 # average ReadCleanReq miss latency | 856system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.547945 # average ReadCleanReq miss latency 857system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.547945 # average ReadCleanReq miss latency |
| 858system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92046.153846 # average ReadSharedReq miss latency 859system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92046.153846 # average ReadSharedReq miss latency | 858system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92046.153846 # average ReadSharedReq miss latency 859system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92046.153846 # average ReadSharedReq miss latency |
| 860system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency | 860system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency |
| 861system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency | 861system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency |
| 862system.cpu.l2cache.demand_avg_miss_latency::total 82708.576998 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency | 862system.cpu.l2cache.demand_avg_miss_latency::total 82704.678363 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency |
| 864system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency | 864system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency |
| 865system.cpu.l2cache.overall_avg_miss_latency::total 82708.576998 # average overall miss latency | 865system.cpu.l2cache.overall_avg_miss_latency::total 82704.678363 # average overall miss latency |
| 866system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 867system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 869system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 870system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 871system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 872system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 873system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 878system.cpu.l2cache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 880system.cpu.l2cache.demand_mshr_misses::total 513 # number of demand (read+write) MSHR misses 881system.cpu.l2cache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 882system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 883system.cpu.l2cache.overall_mshr_misses::total 513 # number of overall MSHR misses 884system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5932500 # number of ReadExReq MSHR miss cycles 885system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5932500 # number of ReadExReq MSHR miss cycles | 866system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 867system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 869system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 870system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 871system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 872system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 873system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 878system.cpu.l2cache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 879system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 880system.cpu.l2cache.demand_mshr_misses::total 513 # number of demand (read+write) MSHR misses 881system.cpu.l2cache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 882system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 883system.cpu.l2cache.overall_mshr_misses::total 513 # number of overall MSHR misses 884system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5932500 # number of ReadExReq MSHR miss cycles 885system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5932500 # number of ReadExReq MSHR miss cycles |
| 886system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26034000 # number of ReadCleanReq MSHR miss cycles 887system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26034000 # number of ReadCleanReq MSHR miss cycles | 886system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26032000 # number of ReadCleanReq MSHR miss cycles 887system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26032000 # number of ReadCleanReq MSHR miss cycles |
| 888system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5353000 # number of ReadSharedReq MSHR miss cycles 889system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5353000 # number of ReadSharedReq MSHR miss cycles | 888system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5353000 # number of ReadSharedReq MSHR miss cycles 889system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5353000 # number of ReadSharedReq MSHR miss cycles |
| 890system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26034000 # number of demand (read+write) MSHR miss cycles | 890system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26032000 # number of demand (read+write) MSHR miss cycles |
| 891system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11285500 # number of demand (read+write) MSHR miss cycles | 891system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11285500 # number of demand (read+write) MSHR miss cycles |
| 892system.cpu.l2cache.demand_mshr_miss_latency::total 37319500 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26034000 # number of overall MSHR miss cycles | 892system.cpu.l2cache.demand_mshr_miss_latency::total 37317500 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26032000 # number of overall MSHR miss cycles |
| 894system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11285500 # number of overall MSHR miss cycles | 894system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11285500 # number of overall MSHR miss cycles |
| 895system.cpu.l2cache.overall_mshr_miss_latency::total 37319500 # number of overall MSHR miss cycles | 895system.cpu.l2cache.overall_mshr_miss_latency::total 37317500 # number of overall MSHR miss cycles |
| 896system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 897system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for ReadCleanReq accesses 899system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994550 # mshr miss rate for ReadCleanReq accesses 900system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 901system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 902system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for demand accesses 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 904system.cpu.l2cache.demand_mshr_miss_rate::total 0.996117 # mshr miss rate for demand accesses 905system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for overall accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::total 0.996117 # mshr miss rate for overall accesses 908system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614 # average ReadExReq mshr miss latency 909system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614 # average ReadExReq mshr miss latency | 896system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 897system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 898system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for ReadCleanReq accesses 899system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994550 # mshr miss rate for ReadCleanReq accesses 900system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 901system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 902system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for demand accesses 903system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 904system.cpu.l2cache.demand_mshr_miss_rate::total 0.996117 # mshr miss rate for demand accesses 905system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for overall accesses 906system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 907system.cpu.l2cache.overall_mshr_miss_rate::total 0.996117 # mshr miss rate for overall accesses 908system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614 # average ReadExReq mshr miss latency 909system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614 # average ReadExReq mshr miss latency |
| 910system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71326.027397 # average ReadCleanReq mshr miss latency 911system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71326.027397 # average ReadCleanReq mshr miss latency | 910system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71320.547945 # average ReadCleanReq mshr miss latency 911system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71320.547945 # average ReadCleanReq mshr miss latency |
| 912system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154 # average ReadSharedReq mshr miss latency 913system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154 # average ReadSharedReq mshr miss latency | 912system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154 # average ReadSharedReq mshr miss latency 913system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154 # average ReadSharedReq mshr miss latency |
| 914system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency | 914system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency |
| 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency | 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency |
| 916system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency 917system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency | 916system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency 917system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency |
| 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency | 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency |
| 919system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency | 919system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency |
| 920system.cpu.toL2Bus.snoop_filter.tot_requests 515 # Total number of requests made to the snoop filter. 921system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 922system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 923system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 924system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 925system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 926system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 927system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution --- 62 unchanged lines hidden --- | 920system.cpu.toL2Bus.snoop_filter.tot_requests 515 # Total number of requests made to the snoop filter. 921system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 922system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 923system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 924system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 925system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 926system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states 927system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution --- 62 unchanged lines hidden --- |