Cross Reference: /gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000029 # Number of seconds simulated

4sim_ticks 28845500 # Number of ticks simulated
5final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 29089500 # Number of ticks simulated
5final_tick 29089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 66025 # Simulator instruction rate (inst/s)
8host_op_rate 66018 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 131902943 # Simulator tick rate (ticks/s)
10host_mem_usage 248796 # Number of bytes of host memory used
11host_seconds 0.22 # Real time elapsed on the host

7host_inst_rate 39190 # Simulator instruction rate (inst/s)
8host_op_rate 39188 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 78964807 # Simulator tick rate (ticks/s)
10host_mem_usage 252916 # Number of bytes of host memory used
11host_seconds 0.37 # Real time elapsed on the host

12sim_insts 14436 # Number of instructions simulated
13sim_ops 14436 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
19system.physmem.bytes_read::total 32640 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 510 # Number of read requests responded to by this memory

25system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s)

25system.physmem.bw_read::cpu.inst 798638684 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 323415665 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 1122054350 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 798638684 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 798638684 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 798638684 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 323415665 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 1122054350 # Total bandwidth to/from this memory (bytes/s)

33system.physmem.readReqs 511 # Number of read requests accepted
34system.physmem.writeReqs 0 # Number of write requests accepted
35system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side

--- 30 unchanged lines hidden (view full) ---

71system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

79system.physmem.totGap 28814000 # Total gap between requests

79system.physmem.totGap 29058000 # Total gap between requests

80system.physmem.readPktSize::0 0 # Read request sizes (log2)
81system.physmem.readPktSize::1 0 # Read request sizes (log2)
82system.physmem.readPktSize::2 0 # Read request sizes (log2)
83system.physmem.readPktSize::3 0 # Read request sizes (log2)
84system.physmem.readPktSize::4 0 # Read request sizes (log2)
85system.physmem.readPktSize::5 0 # Read request sizes (log2)
86system.physmem.readPktSize::6 511 # Read request sizes (log2)
87system.physmem.writePktSize::0 0 # Write request sizes (log2)

--- 95 unchanged lines hidden (view full) ---

183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation

191system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation

191system.physmem.bytesPerActivate::mean 411.306667 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 274.853259 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 343.874505 # Bytes accessed per row activation

194system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation

195system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation

195system.physmem.bytesPerActivate::128-255 19 25.33% 42.67% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383 12 16.00% 58.67% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 6 8.00% 66.67% # Bytes accessed per row activation

198system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation

203system.physmem.totQLat 3584250 # Total ticks spent queuing
204system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM

203system.physmem.totQLat 3266500 # Total ticks spent queuing
204system.physmem.totMemAccLat 12847750 # Total ticks spent from burst creation until serviced by the DRAM

205system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers

206system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst

206system.physmem.avgQLat 6392.37 # Average queueing delay per DRAM burst

207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

208system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s

208system.physmem.avgMemAccLat 25142.37 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 1124.25 # Average DRAM read bandwidth in MiByte/s

210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s

211system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s

211system.physmem.avgRdBWSys 1124.25 # Average system read bandwidth in MiByte/s

212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s

214system.physmem.busUtil 8.86 # Data bus utilization in percentage
215system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads

214system.physmem.busUtil 8.78 # Data bus utilization in percentage
215system.physmem.busUtilRead 8.78 # Data bus utilization in percentage for reads

216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes

217system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing

217system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing

218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing

219system.physmem.readRowHits 428 # Number of row buffer hits during reads

219system.physmem.readRowHits 427 # Number of row buffer hits during reads

220system.physmem.writeRowHits 0 # Number of row buffer hits during writes

221system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads

221system.physmem.readRowHitRate 83.56 # Row buffer hit rate for reads

222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

223system.physmem.avgGap 56387.48 # Average gap between requests
224system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined

223system.physmem.avgGap 56864.97 # Average gap between requests
224system.physmem.pageHitRate 83.56 # Row buffer hit rate, read and write combined

225system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)

227system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ)

227system.physmem_0.readEnergy 2113800 # Energy for read commands per rank (pJ)

228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)

230system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
232system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ)
233system.physmem_0.averagePower 856.515480 # Core power per rank (mW)
234system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states

230system.physmem_0.actBackEnergy 16083405 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 63000 # Energy for precharge background per rank (pJ)
232system.physmem_0.totalEnergy 20264970 # Total energy per rank (pJ)
233system.physmem_0.averagePower 858.003493 # Core power per rank (mW)
234system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states

235system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states

237system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states

237system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states

238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)

244system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ)
247system.physmem_1.averagePower 820.243027 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states

244system.physmem_1.actBackEnergy 15332715 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 721500 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 19350015 # Total energy per rank (pJ)
247system.physmem_1.averagePower 819.264991 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 4570750 # Time in different power states

249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states

251system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states

251system.physmem_1.memoryStateTime::ACT 21719750 # Time in different power states

252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

253system.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
254system.cpu.branchPred.lookups 12618 # Number of BP lookups
255system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted

253system.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
254system.cpu.branchPred.lookups 12614 # Number of BP lookups
255system.cpu.branchPred.condPredicted 7656 # Number of conditional branches predicted

256system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect

257system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups

257system.cpu.branchPred.BTBLookups 9453 # Number of BTB lookups

258system.cpu.branchPred.BTBHits 0 # Number of BTB hits
259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
260system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
261system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target.
262system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.

263system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups.

263system.cpu.branchPred.indirectLookups 9453 # Number of indirect predictor lookups.

264system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits.

265system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses.

265system.cpu.branchPred.indirectMisses 7609 # Number of indirect misses.

266system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches.
267system.cpu_clk_domain.clock 500 # Clock period in ticks
268system.cpu.workload.num_syscalls 18 # Number of system calls

269system.cpu.pwrStateResidencyTicks::ON 28845500 # Cumulative time (in ticks) in various power states
270system.cpu.numCycles 57692 # number of cpu cycles simulated

269system.cpu.pwrStateResidencyTicks::ON 29089500 # Cumulative time (in ticks) in various power states
270system.cpu.numCycles 58180 # number of cpu cycles simulated

271system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
272system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

273system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss
274system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed
275system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered

273system.cpu.fetch.icacheStallCycles 15554 # Number of cycles fetch is stalled on an Icache miss
274system.cpu.fetch.Insts 59055 # Number of instructions fetch has processed
275system.cpu.fetch.Branches 12614 # Number of branches that fetch encountered

276system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken

277system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked

277system.cpu.fetch.Cycles 17529 # Number of cycles fetch has run and was not squashing or blocked

278system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing
279system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs

280system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps

280system.cpu.fetch.PendingTrapStallCycles 1090 # Number of stall cycles due to pending traps

281system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR
282system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched

283system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed
284system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total)

283system.cpu.fetch.IcacheSquashes 720 # Number of outstanding Icache misses that were squashed
284system.cpu.fetch.rateDist::samples 35776 # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::mean 1.650688 # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::stdev 2.904189 # Number of instructions fetched each cycle (Total)

287system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

288system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total)
294system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total)

288system.cpu.fetch.rateDist::0 23025 64.36% 64.36% # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::1 4506 12.60% 76.95% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::2 507 1.42% 78.37% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::3 451 1.26% 79.63% # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::4 761 2.13% 81.76% # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::5 707 1.98% 83.73% # Number of instructions fetched each cycle (Total)
294system.cpu.fetch.rateDist::6 297 0.83% 84.57% # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::7 355 0.99% 85.56% # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.rateDist::8 5167 14.44% 100.00% # Number of instructions fetched each cycle (Total)

297system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
298system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
299system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

300system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total)
301system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle
302system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle
303system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle
304system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked
305system.cpu.decode.RunCycles 7933 # Number of cycles decode is running
306system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking

300system.cpu.fetch.rateDist::total 35776 # Number of instructions fetched each cycle (Total)
301system.cpu.fetch.branchRate 0.216810 # Number of branch fetches per cycle
302system.cpu.fetch.rate 1.015040 # Number of inst fetches per cycle
303system.cpu.decode.IdleCycles 12463 # Number of cycles decode is idle
304system.cpu.decode.BlockedCycles 13012 # Number of cycles decode is blocked
305system.cpu.decode.RunCycles 7932 # Number of cycles decode is running
306system.cpu.decode.UnblockCycles 797 # Number of cycles decode is unblocking

307system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing

308system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode

308system.cpu.decode.DecodedInsts 42051 # Number of instructions handled by decode

309system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing

310system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle
311system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking
312system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst
313system.cpu.rename.RunCycles 7918 # Number of cycles rename is running
314system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking
315system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename

310system.cpu.rename.IdleCycles 13239 # Number of cycles rename is idle
311system.cpu.rename.BlockCycles 1819 # Number of cycles rename is blocking
312system.cpu.rename.serializeStallCycles 9760 # count of cycles rename stalled for serializing inst
313system.cpu.rename.RunCycles 7921 # Number of cycles rename is running
314system.cpu.rename.UnblockCycles 1465 # Number of cycles rename is unblocking
315system.cpu.rename.RenamedInsts 37034 # Number of instructions processed by rename

316system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full

317system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full
318system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed
319system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made
320system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups

317system.cpu.rename.SQFullEvents 1048 # Number of times rename has blocked due to SQ full
318system.cpu.rename.RenamedOperands 31990 # Number of destination operands rename has renamed
319system.cpu.rename.RenameLookups 66442 # Number of register rename lookups that rename has made
320system.cpu.rename.int_rename_lookups 54845 # Number of integer rename lookups

321system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed

322system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing

322system.cpu.rename.UndoneMaps 18171 # Number of HB maps that are undone due to squashing

323system.cpu.rename.serializingInsts 796 # count of serializing insts renamed
324system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed
325system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer
326system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit.

327system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit.

327system.cpu.memDep0.insertedStores 2920 # Number of stores inserted to the mem dependence unit.

328system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads.
329system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.

330system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec)

330system.cpu.iq.iqInstsAdded 28828 # Number of instructions added to the IQ (excludes non-spec)

331system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ
332system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued

333system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
334system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling
335system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph

333system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
334system.cpu.iq.iqSquashedInstsExamined 15149 # Number of squashed instructions iterated over during squash; mainly for profiling
335system.cpu.iq.iqSquashedOperandsExamined 11337 # Number of squashed operands that are examined and possibly removed from graph

336system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed

337system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle
338system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle
339system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle

337system.cpu.iq.issued_per_cycle::samples 35776 # Number of insts issued each cycle
338system.cpu.iq.issued_per_cycle::mean 0.708911 # Number of insts issued each cycle
339system.cpu.iq.issued_per_cycle::stdev 1.503990 # Number of insts issued each cycle

340system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

341system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle
342system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle
343system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle
344system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle
345system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle
346system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle
347system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle
348system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle

341system.cpu.iq.issued_per_cycle::0 26518 74.12% 74.12% # Number of insts issued each cycle
342system.cpu.iq.issued_per_cycle::1 3268 9.13% 83.26% # Number of insts issued each cycle
343system.cpu.iq.issued_per_cycle::2 1619 4.53% 87.78% # Number of insts issued each cycle
344system.cpu.iq.issued_per_cycle::3 1541 4.31% 92.09% # Number of insts issued each cycle
345system.cpu.iq.issued_per_cycle::4 1236 3.45% 95.54% # Number of insts issued each cycle
346system.cpu.iq.issued_per_cycle::5 752 2.10% 97.65% # Number of insts issued each cycle
347system.cpu.iq.issued_per_cycle::6 465 1.30% 98.95% # Number of insts issued each cycle
348system.cpu.iq.issued_per_cycle::7 277 0.77% 99.72% # Number of insts issued each cycle

349system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle
350system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
351system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
352system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

353system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle

353system.cpu.iq.issued_per_cycle::total 35776 # Number of insts issued each cycle

354system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

355system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available
356system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available
357system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available
358system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available
359system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available
360system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available
361system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available
362system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available
363system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available
373system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available
374system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available
375system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available
376system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available
377system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available
378system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available
379system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available
380system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available
381system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available
382system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available
383system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
384system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available
385system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available

355system.cpu.iq.fu_full::IntAlu 154 52.56% 52.56% # attempts to use FU when none available
356system.cpu.iq.fu_full::IntMult 0 0.00% 52.56% # attempts to use FU when none available
357system.cpu.iq.fu_full::IntDiv 0 0.00% 52.56% # attempts to use FU when none available
358system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.56% # attempts to use FU when none available
359system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.56% # attempts to use FU when none available
360system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.56% # attempts to use FU when none available
361system.cpu.iq.fu_full::FloatMult 0 0.00% 52.56% # attempts to use FU when none available
362system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.56% # attempts to use FU when none available
363system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.56% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.56% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.56% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.56% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.56% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.56% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.56% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdMult 0 0.00% 52.56% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.56% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdShift 0 0.00% 52.56% # attempts to use FU when none available
373system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.56% # attempts to use FU when none available
374system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.56% # attempts to use FU when none available
375system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.56% # attempts to use FU when none available
376system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.56% # attempts to use FU when none available
377system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.56% # attempts to use FU when none available
378system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.56% # attempts to use FU when none available
379system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.56% # attempts to use FU when none available
380system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.56% # attempts to use FU when none available
381system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.56% # attempts to use FU when none available
382system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.56% # attempts to use FU when none available
383system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.56% # attempts to use FU when none available
384system.cpu.iq.fu_full::MemRead 51 17.41% 69.97% # attempts to use FU when none available
385system.cpu.iq.fu_full::MemWrite 88 30.03% 100.00% # attempts to use FU when none available

386system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
387system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
388system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

389system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued
390system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued
391system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued
392system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued
393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued
394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued
395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued
396system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued
397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued
407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued
408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued
409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued
410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued
411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued
412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued
413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued
415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued
416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued
417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued
418system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued

389system.cpu.iq.FU_type_0::IntAlu 18584 73.27% 73.27% # Type of FU issued
390system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.27% # Type of FU issued
391system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.27% # Type of FU issued
392system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.27% # Type of FU issued
393system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.27% # Type of FU issued
394system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.27% # Type of FU issued
395system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.27% # Type of FU issued
396system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.27% # Type of FU issued
397system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.27% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.27% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.27% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.27% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.27% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.27% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.27% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.27% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.27% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.27% # Type of FU issued
407system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.27% # Type of FU issued
408system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.27% # Type of FU issued
409system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.27% # Type of FU issued
410system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.27% # Type of FU issued
411system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.27% # Type of FU issued
412system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.27% # Type of FU issued
413system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.27% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.27% # Type of FU issued
415system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.27% # Type of FU issued
416system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.27% # Type of FU issued
417system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.27% # Type of FU issued
418system.cpu.iq.FU_type_0::MemRead 4272 16.84% 90.12% # Type of FU issued

419system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued
420system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
421system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
422system.cpu.iq.FU_type_0::total 25362 # Type of FU issued

423system.cpu.iq.rate 0.439610 # Inst issue rate
424system.cpu.iq.fu_busy_cnt 294 # FU busy when requested
425system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst)
426system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads
427system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes
428system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses

423system.cpu.iq.rate 0.435923 # Inst issue rate
424system.cpu.iq.fu_busy_cnt 293 # FU busy when requested
425system.cpu.iq.fu_busy_rate 0.011553 # FU busy rate (busy events/executed inst)
426system.cpu.iq.int_inst_queue_reads 86911 # Number of integer instruction queue reads
427system.cpu.iq.int_inst_queue_writes 44761 # Number of integer instruction queue writes
428system.cpu.iq.int_inst_queue_wakeup_accesses 22611 # Number of integer instruction queue wakeup accesses

429system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
430system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
431system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses

432system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses

432system.cpu.iq.int_alu_accesses 25655 # Number of integer alu accesses

433system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
434system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
435system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
436system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed
437system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
438system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations

439system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed

439system.cpu.iew.lsq.thread0.squashedStores 1472 # Number of stores squashed

440system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
441system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
442system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
443system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
444system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
445system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing

446system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking

446system.cpu.iew.iewBlockCycles 1852 # Number of cycles IEW is blocking

447system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking

448system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ

448system.cpu.iew.iewDispatchedInsts 31164 # Number of instructions dispatched to IQ

449system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch
450system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions

451system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions

451system.cpu.iew.iewDispStoreInsts 2920 # Number of dispatched store instructions

452system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions
453system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
454system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
455system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
456system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly

457system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly
458system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute
459system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions

457system.cpu.iew.predictedNotTakenIncorrect 1624 # Number of branches that were predicted not taken incorrectly
458system.cpu.iew.branchMispredicts 1835 # Number of branch mispredicts detected at execute
459system.cpu.iew.iewExecutedInsts 23718 # Number of executed instructions

460system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed

461system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute

461system.cpu.iew.iewExecSquashedInsts 1644 # Number of squashed instructions skipped in execute

462system.cpu.iew.exec_swp 0 # number of swp insts executed
463system.cpu.iew.exec_nop 1579 # number of nop insts executed

464system.cpu.iew.exec_refs 6244 # number of memory reference insts executed

464system.cpu.iew.exec_refs 6245 # number of memory reference insts executed

465system.cpu.iew.exec_branches 5021 # Number of branches executed

466system.cpu.iew.exec_stores 2299 # Number of stores executed
467system.cpu.iew.exec_rate 0.411045 # Inst execution rate
468system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit
469system.cpu.iew.wb_count 22607 # cumulative count of insts written-back
470system.cpu.iew.wb_producers 10530 # num instructions producing a value
471system.cpu.iew.wb_consumers 13790 # num instructions consuming a value
472system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle
473system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back
474system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit

466system.cpu.iew.exec_stores 2300 # Number of stores executed
467system.cpu.iew.exec_rate 0.407666 # Inst execution rate
468system.cpu.iew.wb_sent 23107 # cumulative count of insts sent to commit
469system.cpu.iew.wb_count 22611 # cumulative count of insts written-back
470system.cpu.iew.wb_producers 10526 # num instructions producing a value
471system.cpu.iew.wb_consumers 13786 # num instructions consuming a value
472system.cpu.iew.wb_rate 0.388639 # insts written-back per cycle
473system.cpu.iew.wb_fanout 0.763528 # average fanout of values written-back
474system.cpu.commit.commitSquashedInsts 15913 # The number of squashed insts skipped by commit

475system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
476system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted

477system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle
479system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle

477system.cpu.commit.committed_per_cycle::samples 32637 # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::mean 0.464565 # Number of insts commited each cycle
479system.cpu.commit.committed_per_cycle::stdev 1.243420 # Number of insts commited each cycle

480system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

481system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle
482system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle
485system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle
486system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle

481system.cpu.commit.committed_per_cycle::0 25892 79.33% 79.33% # Number of insts commited each cycle
482system.cpu.commit.committed_per_cycle::1 3639 11.15% 90.48% # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::2 1211 3.71% 94.19% # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::3 601 1.84% 96.04% # Number of insts commited each cycle
485system.cpu.commit.committed_per_cycle::4 338 1.04% 97.07% # Number of insts commited each cycle
486system.cpu.commit.committed_per_cycle::5 300 0.92% 97.99% # Number of insts commited each cycle

487system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle

488system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle

488system.cpu.commit.committed_per_cycle::7 54 0.17% 99.30% # Number of insts commited each cycle

489system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle
490system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
491system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
492system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

493system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle

493system.cpu.commit.committed_per_cycle::total 32637 # Number of insts commited each cycle

494system.cpu.commit.committedInsts 15162 # Number of instructions committed
495system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
496system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
497system.cpu.commit.refs 3673 # Number of memory references committed
498system.cpu.commit.loads 2225 # Number of loads committed
499system.cpu.commit.membars 0 # Number of memory barriers committed
500system.cpu.commit.branches 3358 # Number of branches committed
501system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.

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532system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
533system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
534system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
535system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
536system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
537system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
538system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
539system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached

540system.cpu.rob.rob_reads 62581 # The number of ROB reads
541system.cpu.rob.rob_writes 65380 # The number of ROB writes
542system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself
543system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling

540system.cpu.rob.rob_reads 62661 # The number of ROB reads
541system.cpu.rob.rob_writes 65377 # The number of ROB writes
542system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself
543system.cpu.idleCycles 22404 # Total number of cycles that the CPU has spent unscheduled due to idling

544system.cpu.committedInsts 14436 # Number of Instructions Simulated
545system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated

546system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction
547system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads
548system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle
549system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads
550system.cpu.int_regfile_reads 36850 # number of integer regfile reads
551system.cpu.int_regfile_writes 20548 # number of integer regfile writes
552system.cpu.misc_regfile_reads 8142 # number of misc regfile reads

546system.cpu.cpi 4.030202 # CPI: Cycles Per Instruction
547system.cpu.cpi_total 4.030202 # CPI: Total CPI of All Threads
548system.cpu.ipc 0.248127 # IPC: Instructions Per Cycle
549system.cpu.ipc_total 0.248127 # IPC: Total IPC of All Threads
550system.cpu.int_regfile_reads 36851 # number of integer regfile reads
551system.cpu.int_regfile_writes 20552 # number of integer regfile writes
552system.cpu.misc_regfile_reads 8143 # number of misc regfile reads

553system.cpu.misc_regfile_writes 569 # number of misc regfile writes

554system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states

554system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states

555system.cpu.dcache.tags.replacements 0 # number of replacements

556system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use

556system.cpu.dcache.tags.tagsinuse 99.825953 # Cycle average of tags in use

557system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks.
558system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
559system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks.
560system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

561system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor
562system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy
563system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy

561system.cpu.dcache.tags.occ_blocks::cpu.data 99.825953 # Average occupied blocks per requestor
562system.cpu.dcache.tags.occ_percent::cpu.data 0.024372 # Average percentage of cache occupancy
563system.cpu.dcache.tags.occ_percent::total 0.024372 # Average percentage of cache occupancy

564system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
565system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
566system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
567system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
568system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses
569system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses

570system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states

570system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states

571system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits
572system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits
573system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
574system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
575system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
576system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
577system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits
578system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits
579system.cpu.dcache.overall_hits::cpu.data 4642 # number of overall hits
580system.cpu.dcache.overall_hits::total 4642 # number of overall hits
581system.cpu.dcache.ReadReq_misses::cpu.data 140 # number of ReadReq misses
582system.cpu.dcache.ReadReq_misses::total 140 # number of ReadReq misses
583system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
584system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
585system.cpu.dcache.demand_misses::cpu.data 549 # number of demand (read+write) misses
586system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses
587system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses
588system.cpu.dcache.overall_misses::total 549 # number of overall misses

589system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles
590system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles
591system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles
592system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles
593system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles
594system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles
595system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles
596system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles

589system.cpu.dcache.ReadReq_miss_latency::cpu.data 9476500 # number of ReadReq miss cycles
590system.cpu.dcache.ReadReq_miss_latency::total 9476500 # number of ReadReq miss cycles
591system.cpu.dcache.WriteReq_miss_latency::cpu.data 27259981 # number of WriteReq miss cycles
592system.cpu.dcache.WriteReq_miss_latency::total 27259981 # number of WriteReq miss cycles
593system.cpu.dcache.demand_miss_latency::cpu.data 36736481 # number of demand (read+write) miss cycles
594system.cpu.dcache.demand_miss_latency::total 36736481 # number of demand (read+write) miss cycles
595system.cpu.dcache.overall_miss_latency::cpu.data 36736481 # number of overall miss cycles
596system.cpu.dcache.overall_miss_latency::total 36736481 # number of overall miss cycles

597system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses)
598system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses)
599system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
600system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
601system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
602system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
603system.cpu.dcache.demand_accesses::cpu.data 5191 # number of demand (read+write) accesses
604system.cpu.dcache.demand_accesses::total 5191 # number of demand (read+write) accesses
605system.cpu.dcache.overall_accesses::cpu.data 5191 # number of overall (read+write) accesses
606system.cpu.dcache.overall_accesses::total 5191 # number of overall (read+write) accesses
607system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037343 # miss rate for ReadReq accesses
608system.cpu.dcache.ReadReq_miss_rate::total 0.037343 # miss rate for ReadReq accesses
609system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
610system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
611system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 # miss rate for demand accesses
612system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses
613system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses
614system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses

615system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency
616system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency
617system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency
618system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency
619system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
620system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency
621system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
622system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency
623system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked

615system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67689.285714 # average ReadReq miss latency
616system.cpu.dcache.ReadReq_avg_miss_latency::total 67689.285714 # average ReadReq miss latency
617system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66650.320293 # average WriteReq miss latency
618system.cpu.dcache.WriteReq_avg_miss_latency::total 66650.320293 # average WriteReq miss latency
619system.cpu.dcache.demand_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency
620system.cpu.dcache.demand_avg_miss_latency::total 66915.265938 # average overall miss latency
621system.cpu.dcache.overall_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency
622system.cpu.dcache.overall_avg_miss_latency::total 66915.265938 # average overall miss latency
623system.cpu.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked

624system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
625system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked
626system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked

627system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked

627system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.956522 # average number of cycles each access was blocked

628system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
629system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits
630system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
631system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
632system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
633system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits
634system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits
635system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits
636system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits
637system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
638system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
639system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
640system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
641system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
642system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
643system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
644system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses

645system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles
646system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles
647system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles
648system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles
649system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles
650system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles
651system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles
652system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles

645system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5190500 # number of ReadReq MSHR miss cycles
646system.cpu.dcache.ReadReq_mshr_miss_latency::total 5190500 # number of ReadReq MSHR miss cycles
647system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6454500 # number of WriteReq MSHR miss cycles
648system.cpu.dcache.WriteReq_mshr_miss_latency::total 6454500 # number of WriteReq MSHR miss cycles
649system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11645000 # number of demand (read+write) MSHR miss cycles
650system.cpu.dcache.demand_mshr_miss_latency::total 11645000 # number of demand (read+write) MSHR miss cycles
651system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11645000 # number of overall MSHR miss cycles
652system.cpu.dcache.overall_mshr_miss_latency::total 11645000 # number of overall MSHR miss cycles

653system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses
654system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses
655system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
656system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
657system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for demand accesses
658system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses
659system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses
660system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses

661system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency
662system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency
663system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency
664system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency
665system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
666system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
667system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
668system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
669system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states

661system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79853.846154 # average ReadReq mshr miss latency
662system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79853.846154 # average ReadReq mshr miss latency
663system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77765.060241 # average WriteReq mshr miss latency
664system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77765.060241 # average WriteReq mshr miss latency
665system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency
666system.cpu.dcache.demand_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency
667system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency
668system.cpu.dcache.overall_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency
669system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states

670system.cpu.icache.tags.replacements 0 # number of replacements

671system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use

671system.cpu.icache.tags.tagsinuse 206.188252 # Cycle average of tags in use

672system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks.
673system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
674system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks.
675system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

676system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor
677system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy
678system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy

676system.cpu.icache.tags.occ_blocks::cpu.inst 206.188252 # Average occupied blocks per requestor
677system.cpu.icache.tags.occ_percent::cpu.inst 0.100678 # Average percentage of cache occupancy
678system.cpu.icache.tags.occ_percent::total 0.100678 # Average percentage of cache occupancy

679system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id

680system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
681system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id

680system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
681system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id

682system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
683system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses
684system.cpu.icache.tags.data_accesses 15425 # Number of data accesses

685system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states

685system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states

686system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits
687system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits
688system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits
689system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits
690system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits
691system.cpu.icache.overall_hits::total 6949 # number of overall hits
692system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses
693system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses
694system.cpu.icache.demand_misses::cpu.inst 581 # number of demand (read+write) misses
695system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses
696system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses
697system.cpu.icache.overall_misses::total 581 # number of overall misses

698system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles
699system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles
700system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles
701system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles
702system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles
703system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles

698system.cpu.icache.ReadReq_miss_latency::cpu.inst 40938500 # number of ReadReq miss cycles
699system.cpu.icache.ReadReq_miss_latency::total 40938500 # number of ReadReq miss cycles
700system.cpu.icache.demand_miss_latency::cpu.inst 40938500 # number of demand (read+write) miss cycles
701system.cpu.icache.demand_miss_latency::total 40938500 # number of demand (read+write) miss cycles
702system.cpu.icache.overall_miss_latency::cpu.inst 40938500 # number of overall miss cycles
703system.cpu.icache.overall_miss_latency::total 40938500 # number of overall miss cycles

704system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses)
705system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses)
706system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses
707system.cpu.icache.demand_accesses::total 7530 # number of demand (read+write) accesses
708system.cpu.icache.overall_accesses::cpu.inst 7530 # number of overall (read+write) accesses
709system.cpu.icache.overall_accesses::total 7530 # number of overall (read+write) accesses
710system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.077158 # miss rate for ReadReq accesses
711system.cpu.icache.ReadReq_miss_rate::total 0.077158 # miss rate for ReadReq accesses
712system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 # miss rate for demand accesses
713system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses
714system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses
715system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses

716system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency
717system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency
718system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
719system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency
720system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
721system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency
722system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked

716system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70462.134251 # average ReadReq miss latency
717system.cpu.icache.ReadReq_avg_miss_latency::total 70462.134251 # average ReadReq miss latency
718system.cpu.icache.demand_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency
719system.cpu.icache.demand_avg_miss_latency::total 70462.134251 # average overall miss latency
720system.cpu.icache.overall_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency
721system.cpu.icache.overall_avg_miss_latency::total 70462.134251 # average overall miss latency
722system.cpu.icache.blocked_cycles::no_mshrs 194 # number of cycles access was blocked

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724system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
725system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

726system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked

726system.cpu.icache.avg_blocked_cycles::no_mshrs 97 # average number of cycles each access was blocked

727system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
728system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits
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731system.cpu.icache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits
732system.cpu.icache.overall_mshr_hits::cpu.inst 216 # number of overall MSHR hits
733system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits
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735system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses
736system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses
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738system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
739system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses

740system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles
741system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles
742system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles
743system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles
744system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles
745system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles

740system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27977500 # number of ReadReq MSHR miss cycles
741system.cpu.icache.ReadReq_mshr_miss_latency::total 27977500 # number of ReadReq MSHR miss cycles
742system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27977500 # number of demand (read+write) MSHR miss cycles
743system.cpu.icache.demand_mshr_miss_latency::total 27977500 # number of demand (read+write) MSHR miss cycles
744system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27977500 # number of overall MSHR miss cycles
745system.cpu.icache.overall_mshr_miss_latency::total 27977500 # number of overall MSHR miss cycles

746system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for ReadReq accesses
747system.cpu.icache.ReadReq_mshr_miss_rate::total 0.048473 # mshr miss rate for ReadReq accesses
748system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for demand accesses
749system.cpu.icache.demand_mshr_miss_rate::total 0.048473 # mshr miss rate for demand accesses
750system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses
751system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses

752system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency
753system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency
754system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
755system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
756system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
757system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
758system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states

752system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76650.684932 # average ReadReq mshr miss latency
753system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76650.684932 # average ReadReq mshr miss latency
754system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency
755system.cpu.icache.demand_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency
756system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency
757system.cpu.icache.overall_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency
758system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states

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760system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use

760system.cpu.l2cache.tags.tagsinuse 305.425349 # Cycle average of tags in use

761system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.

762system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
763system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks.

762system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks.
763system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks.

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765system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor
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771system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
772system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
773system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id

765system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.546698 # Average occupied blocks per requestor
766system.cpu.l2cache.tags.occ_blocks::cpu.data 99.878652 # Average occupied blocks per requestor
767system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006273 # Average percentage of cache occupancy
768system.cpu.l2cache.tags.occ_percent::cpu.data 0.003048 # Average percentage of cache occupancy
769system.cpu.l2cache.tags.occ_percent::total 0.009321 # Average percentage of cache occupancy
770system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
771system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
772system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id
773system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id

774system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses
775system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses

776system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states

776system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states

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792system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
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848system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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890system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68700 # average ReadSharedReq mshr miss latency
891system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency
892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency
893system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency
894system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency
895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency
896system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency

897system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter.
898system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
899system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
900system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
901system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
902system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

903system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states

903system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states

904system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution
905system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
906system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
907system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution
908system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
909system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
910system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
911system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes)

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926system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
927system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram
928system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks)
929system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
930system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks)
931system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
932system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks)
933system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)

934system.membus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states

934system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
935system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
936system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
937system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
938system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
939system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
940system.membus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states

935system.membus.trans_dist::ReadResp 426 # Transaction distribution
936system.membus.trans_dist::ReadExReq 83 # Transaction distribution
937system.membus.trans_dist::ReadExResp 83 # Transaction distribution
938system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution
939system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes)
940system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes)
941system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes)
942system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes)

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947system.membus.snoop_fanout::stdev 0 # Request fanout histogram
948system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
949system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram
950system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
951system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
952system.membus.snoop_fanout::min_value 0 # Request fanout histogram
953system.membus.snoop_fanout::max_value 0 # Request fanout histogram
954system.membus.snoop_fanout::total 511 # Request fanout histogram

941system.membus.trans_dist::ReadResp 426 # Transaction distribution
942system.membus.trans_dist::ReadExReq 83 # Transaction distribution
943system.membus.trans_dist::ReadExResp 83 # Transaction distribution
944system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution
945system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes)
946system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes)
947system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes)
948system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes)

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953system.membus.snoop_fanout::stdev 0 # Request fanout histogram
954system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
955system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram
956system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
957system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
958system.membus.snoop_fanout::min_value 0 # Request fanout histogram
959system.membus.snoop_fanout::max_value 0 # Request fanout histogram
960system.membus.snoop_fanout::total 511 # Request fanout histogram

955system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks)
956system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
957system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks)

961system.membus.reqLayer0.occupancy 623000 # Layer occupancy (ticks)
962system.membus.reqLayer0.utilization 2.1 # Layer utilization (%)
963system.membus.respLayer1.occupancy 2693500 # Layer occupancy (ticks)