| stats.txt (11507:be6065c1d8d2) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000029 # Number of seconds simulated 4sim_ticks 28845500 # Number of ticks simulated 5final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000029 # Number of seconds simulated 4sim_ticks 28845500 # Number of ticks simulated 5final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 50478 # Simulator instruction rate (inst/s) 8host_op_rate 50473 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 100846842 # Simulator tick rate (ticks/s) 10host_mem_usage 247864 # Number of bytes of host memory used 11host_seconds 0.29 # Real time elapsed on the host | 7host_inst_rate 97927 # Simulator instruction rate (inst/s) 8host_op_rate 97921 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 195651101 # Simulator tick rate (ticks/s) 10host_mem_usage 293060 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 18system.physmem.bytes_read::total 32640 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 510 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 244system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ) 245system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ) 246system.physmem_1.averagePower 820.243027 # Core power per rank (mW) 247system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states 248system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states 251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 19system.physmem.bytes_read::total 32640 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 510 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ) 247system.physmem_1.averagePower 820.243027 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states 249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states |
|
| 252system.cpu.branchPred.lookups 12618 # Number of BP lookups 253system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted 254system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect 255system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups 256system.cpu.branchPred.BTBHits 0 # Number of BTB hits 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 258system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 259system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target. 260system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. 261system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups. 262system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits. 263system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses. 264system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches. 265system.cpu_clk_domain.clock 500 # Clock period in ticks 266system.cpu.workload.num_syscalls 18 # Number of system calls | 254system.cpu.branchPred.lookups 12618 # Number of BP lookups 255system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted 256system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect 257system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups 258system.cpu.branchPred.BTBHits 0 # Number of BTB hits 259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 260system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 261system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target. 262system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. 263system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups. 264system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits. 265system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses. 266system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches. 267system.cpu_clk_domain.clock 500 # Clock period in ticks 268system.cpu.workload.num_syscalls 18 # Number of system calls |
| 269system.cpu.pwrStateResidencyTicks::ON 28845500 # Cumulative time (in ticks) in various power states |
|
| 267system.cpu.numCycles 57692 # number of cpu cycles simulated 268system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 269system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 270system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss 271system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed 272system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered 273system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken 274system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked --- 268 unchanged lines hidden (view full) --- 543system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction 544system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads 545system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle 546system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads 547system.cpu.int_regfile_reads 36850 # number of integer regfile reads 548system.cpu.int_regfile_writes 20548 # number of integer regfile writes 549system.cpu.misc_regfile_reads 8142 # number of misc regfile reads 550system.cpu.misc_regfile_writes 569 # number of misc regfile writes | 270system.cpu.numCycles 57692 # number of cpu cycles simulated 271system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 272system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 273system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss 274system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed 275system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered 276system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken 277system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked --- 268 unchanged lines hidden (view full) --- 546system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction 547system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads 548system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle 549system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads 550system.cpu.int_regfile_reads 36850 # number of integer regfile reads 551system.cpu.int_regfile_writes 20548 # number of integer regfile writes 552system.cpu.misc_regfile_reads 8142 # number of misc regfile reads 553system.cpu.misc_regfile_writes 569 # number of misc regfile writes |
| 554system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states |
|
| 551system.cpu.dcache.tags.replacements 0 # number of replacements 552system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use 553system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks. 554system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 555system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks. 556system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 557system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor 558system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy 559system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy 560system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 561system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 562system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 563system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 564system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses 565system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses | 555system.cpu.dcache.tags.replacements 0 # number of replacements 556system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use 557system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks. 558system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 559system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks. 560system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 561system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor 562system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy 563system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy 564system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 565system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 566system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 567system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 568system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses 569system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses |
| 570system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states |
|
| 566system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits 567system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits 568system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 569system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 570system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 571system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 572system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits 573system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits --- 82 unchanged lines hidden (view full) --- 656system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency 657system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency 658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency 659system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency 660system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency 661system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency 662system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency 663system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency | 571system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits 572system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits 573system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 574system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 575system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 576system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 577system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits 578system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits --- 82 unchanged lines hidden (view full) --- 661system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency 662system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency 663system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency 664system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency 665system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency 666system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency 667system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency 668system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency |
| 669system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states |
|
| 664system.cpu.icache.tags.replacements 0 # number of replacements 665system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use 666system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. 667system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 668system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. 669system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 670system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor 671system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy 672system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy 673system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 674system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id 676system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id 677system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses 678system.cpu.icache.tags.data_accesses 15425 # Number of data accesses | 670system.cpu.icache.tags.replacements 0 # number of replacements 671system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use 672system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. 673system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 674system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. 675system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 676system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor 677system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy 678system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy 679system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 680system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 681system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id 682system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id 683system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses 684system.cpu.icache.tags.data_accesses 15425 # Number of data accesses |
| 685system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states |
|
| 679system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits 680system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits 681system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits 682system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits 683system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits 684system.cpu.icache.overall_hits::total 6949 # number of overall hits 685system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses 686system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 743system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses 744system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses 745system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency 746system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency 747system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency 748system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency 749system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency 750system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency | 686system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits 687system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits 688system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits 689system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits 690system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits 691system.cpu.icache.overall_hits::total 6949 # number of overall hits 692system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses 693system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 750system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses 751system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses 752system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency 753system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency 754system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency 755system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency 756system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency 757system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency |
| 758system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states |
|
| 751system.cpu.l2cache.tags.replacements 0 # number of replacements 752system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use 753system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 754system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 755system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks. 756system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 757system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor 758system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor 759system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy 760system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy 761system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy 762system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id 763system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 764system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id 765system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id 766system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses 767system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses | 759system.cpu.l2cache.tags.replacements 0 # number of replacements 760system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use 761system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 762system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 763system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks. 764system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 765system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor 766system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor 767system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy 768system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy 769system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy 770system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id 771system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 772system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id 773system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id 774system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses 775system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses |
| 776system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states |
|
| 768system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 769system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 770system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 771system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 772system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 773system.cpu.l2cache.overall_hits::total 2 # number of overall hits 774system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 775system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 886system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency 887system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency 888system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. 889system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 890system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 891system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 892system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 893system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 777system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 778system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 779system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 780system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 781system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 782system.cpu.l2cache.overall_hits::total 2 # number of overall hits 783system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 784system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses --- 110 unchanged lines hidden (view full) --- 895system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency 896system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency 897system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. 898system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 899system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 900system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 901system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 902system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 903system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states |
|
| 894system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution 895system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 896system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 897system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution 898system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution 899system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) 900system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 901system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 915system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 916system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram 917system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) 918system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 919system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) 920system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 921system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) 922system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) | 904system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution 905system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 906system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 907system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution 908system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution 909system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) 910system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 911system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 925system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 926system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram 927system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) 928system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 929system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) 930system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 931system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) 932system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 933system.membus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states |
|
| 923system.membus.trans_dist::ReadResp 426 # Transaction distribution 924system.membus.trans_dist::ReadExReq 83 # Transaction distribution 925system.membus.trans_dist::ReadExResp 83 # Transaction distribution 926system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution 927system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) 928system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) 929system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) 930system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 934system.membus.trans_dist::ReadResp 426 # Transaction distribution 935system.membus.trans_dist::ReadExReq 83 # Transaction distribution 936system.membus.trans_dist::ReadExResp 83 # Transaction distribution 937system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution 938system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) 939system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) 940system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) 941system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |