Cross Reference: /gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt

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stats.txt (11456:c0fb4435b80f)	stats.txt (11502:e273e86a873d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000029 # Number of seconds simulated 4sim_ticks 28845500 # Number of ticks simulated 5final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 68981 # Simulator instruction rate (inst/s) 8host_op_rate 68975 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 137812851 # Simulator tick rate (ticks/s) 10host_mem_usage 251992 # Number of bytes of host memory used 11host_seconds 0.21 # Real time elapsed on the host 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 18system.physmem.bytes_read::total 32640 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 510 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 511 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 105 # Per bank write bursts 45system.physmem.perBankRdBursts::1 28 # Per bank write bursts 46system.physmem.perBankRdBursts::2 53 # Per bank write bursts 47system.physmem.perBankRdBursts::3 27 # Per bank write bursts 48system.physmem.perBankRdBursts::4 23 # Per bank write bursts 49system.physmem.perBankRdBursts::5 0 # Per bank write bursts 50system.physmem.perBankRdBursts::6 32 # Per bank write bursts 51system.physmem.perBankRdBursts::7 38 # Per bank write bursts 52system.physmem.perBankRdBursts::8 7 # Per bank write bursts 53system.physmem.perBankRdBursts::9 4 # Per bank write bursts 54system.physmem.perBankRdBursts::10 2 # Per bank write bursts 55system.physmem.perBankRdBursts::11 0 # Per bank write bursts 56system.physmem.perBankRdBursts::12 57 # Per bank write bursts 57system.physmem.perBankRdBursts::13 31 # Per bank write bursts 58system.physmem.perBankRdBursts::14 63 # Per bank write bursts 59system.physmem.perBankRdBursts::15 41 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 28814000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 511 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 298 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation 202system.physmem.totQLat 3584250 # Total ticks spent queuing 203system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM 204system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers 205system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 207system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 8.86 # Data bus utilization in percentage 214system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 216system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.physmem.readRowHits 428 # Number of row buffer hits during reads 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes 220system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 56387.48 # Average gap between requests 223system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined 224system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 225system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 226system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ) 227system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 229system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ) 230system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ) 231system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ) 232system.physmem_0.averagePower 856.515480 # Core power per rank (mW) 233system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states 234system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 235system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 236system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states 237system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 238system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ) 239system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ) 240system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ) 241system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 243system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ) 244system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ) 245system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ) 246system.physmem_1.averagePower 820.243027 # Core power per rank (mW) 247system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states 248system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states 251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 252system.cpu.branchPred.lookups 12618 # Number of BP lookups 253system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted 254system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect 255system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups 256system.cpu.branchPred.BTBHits 0 # Number of BTB hits 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 258system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 259system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target. 260system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. 261system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups. 262system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits. 263system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses. 264system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches. 265system.cpu_clk_domain.clock 500 # Clock period in ticks 266system.cpu.workload.num_syscalls 18 # Number of system calls 267system.cpu.numCycles 57692 # number of cpu cycles simulated 268system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 269system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 270system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss 271system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed 272system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered 273system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken 274system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked 275system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing 276system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 277system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps 278system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR 279system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched 280system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed 281system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle 299system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle 300system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle 301system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked 302system.cpu.decode.RunCycles 7933 # Number of cycles decode is running 303system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking 304system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing 305system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode 306system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing 307system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle 308system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking 309system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst 310system.cpu.rename.RunCycles 7918 # Number of cycles rename is running 311system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking 312system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename 313system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full 314system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full 315system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed 316system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made 317system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups 318system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed 319system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing 320system.cpu.rename.serializingInsts 796 # count of serializing insts renamed 321system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed 322system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer 323system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit. 324system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit. 325system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads. 326system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores. 327system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec) 328system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ 329system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued 330system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued 331system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling 332system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph 333system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed 334system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle 351system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 352system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available 353system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available 354system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available 358system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available 359system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available 360system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available 381system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available 382system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available 383system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 384system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 385system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 386system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued 387system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued 388system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued 392system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued 393system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued 394system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued 415system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued 416system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued 417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 419system.cpu.iq.FU_type_0::total 25362 # Type of FU issued 420system.cpu.iq.rate 0.439610 # Inst issue rate 421system.cpu.iq.fu_busy_cnt 294 # FU busy when requested 422system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst) 423system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads 424system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes 425system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses 426system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 427system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 428system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses 429system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses 430system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 431system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores 432system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 433system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed 434system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 435system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations 436system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed 437system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 438system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 439system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 440system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked 441system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 442system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing 443system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking 444system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking 445system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ 446system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch 447system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions 448system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions 449system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions 450system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 451system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall 452system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations 453system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly 454system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly 455system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute 456system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions 457system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed 458system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute 459system.cpu.iew.exec_swp 0 # number of swp insts executed 460system.cpu.iew.exec_nop 1579 # number of nop insts executed 461system.cpu.iew.exec_refs 6244 # number of memory reference insts executed 462system.cpu.iew.exec_branches 5021 # Number of branches executed 463system.cpu.iew.exec_stores 2299 # Number of stores executed 464system.cpu.iew.exec_rate 0.411045 # Inst execution rate 465system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit 466system.cpu.iew.wb_count 22607 # cumulative count of insts written-back 467system.cpu.iew.wb_producers 10530 # num instructions producing a value 468system.cpu.iew.wb_consumers 13790 # num instructions consuming a value 469system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle 470system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back 471system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit 472system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 473system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted 474system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle 484system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle 491system.cpu.commit.committedInsts 15162 # Number of instructions committed 492system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 493system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 494system.cpu.commit.refs 3673 # Number of memory references committed 495system.cpu.commit.loads 2225 # Number of loads committed 496system.cpu.commit.membars 0 # Number of memory barriers committed 497system.cpu.commit.branches 3358 # Number of branches committed 498system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 499system.cpu.commit.int_insts 12174 # Number of committed integer instructions. 500system.cpu.commit.function_calls 187 # Number of function calls committed. 501system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction 502system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction 503system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction 504system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction 505system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction 506system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction 507system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction 508system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction 509system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction 510system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction 511system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction 512system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction 513system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction 514system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction 515system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction 516system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction 517system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction 518system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction 519system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction 520system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction 521system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction 522system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction 523system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction 526system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction 527system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction 531system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction 532system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 534system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 535system.cpu.commit.op_class_0::total 15162 # Class of committed instruction 536system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached 537system.cpu.rob.rob_reads 62581 # The number of ROB reads 538system.cpu.rob.rob_writes 65380 # The number of ROB writes 539system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself 540system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling 541system.cpu.committedInsts 14436 # Number of Instructions Simulated 542system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 543system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction 544system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads 545system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle 546system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads 547system.cpu.int_regfile_reads 36850 # number of integer regfile reads 548system.cpu.int_regfile_writes 20548 # number of integer regfile writes 549system.cpu.misc_regfile_reads 8142 # number of misc regfile reads 550system.cpu.misc_regfile_writes 569 # number of misc regfile writes 551system.cpu.dcache.tags.replacements 0 # number of replacements 552system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use 553system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks. 554system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 555system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks. 556system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 557system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor 558system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy 559system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy 560system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 561system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 562system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 563system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 564system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses 565system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses 566system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits 567system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits 568system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 569system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 570system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 571system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 572system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits 573system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits 574system.cpu.dcache.overall_hits::cpu.data 4642 # number of overall hits 575system.cpu.dcache.overall_hits::total 4642 # number of overall hits 576system.cpu.dcache.ReadReq_misses::cpu.data 140 # number of ReadReq misses 577system.cpu.dcache.ReadReq_misses::total 140 # number of ReadReq misses 578system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 579system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 580system.cpu.dcache.demand_misses::cpu.data 549 # number of demand (read+write) misses 581system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses 582system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses 583system.cpu.dcache.overall_misses::total 549 # number of overall misses 584system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles 585system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles 586system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles 587system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles 588system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles 589system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles 590system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles 591system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles 592system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses) 593system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses) 594system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 595system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 596system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 597system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 598system.cpu.dcache.demand_accesses::cpu.data 5191 # number of demand (read+write) accesses 599system.cpu.dcache.demand_accesses::total 5191 # number of demand (read+write) accesses 600system.cpu.dcache.overall_accesses::cpu.data 5191 # number of overall (read+write) accesses 601system.cpu.dcache.overall_accesses::total 5191 # number of overall (read+write) accesses 602system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037343 # miss rate for ReadReq accesses 603system.cpu.dcache.ReadReq_miss_rate::total 0.037343 # miss rate for ReadReq accesses 604system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 605system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses 606system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 # miss rate for demand accesses 607system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses 608system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses 609system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses 610system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency 611system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency 612system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency 613system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency 614system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency 615system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency 616system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency 617system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency 618system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked 619system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 620system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked 621system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 622system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked 623system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 624system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits 625system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits 626system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 627system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits 628system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits 629system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits 630system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits 631system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits 632system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 633system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 634system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 635system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 636system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 637system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 638system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 639system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses 640system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles 641system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles 642system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles 643system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles 644system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles 645system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles 646system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles 647system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles 648system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses 649system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses 650system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 651system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses 652system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for demand accesses 653system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses 654system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses 655system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses 656system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency 657system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency 658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency 659system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency 660system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency 661system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency 662system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency 663system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency 664system.cpu.icache.tags.replacements 0 # number of replacements 665system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use 666system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. 667system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 668system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. 669system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 670system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor 671system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy 672system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy 673system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 674system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id 676system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id 677system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses 678system.cpu.icache.tags.data_accesses 15425 # Number of data accesses 679system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits 680system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits 681system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits 682system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits 683system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits 684system.cpu.icache.overall_hits::total 6949 # number of overall hits 685system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses 686system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses 687system.cpu.icache.demand_misses::cpu.inst 581 # number of demand (read+write) misses 688system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses 689system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses 690system.cpu.icache.overall_misses::total 581 # number of overall misses 691system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles 692system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles 693system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles 694system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles 695system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles 696system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles 697system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses) 698system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses) 699system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses 700system.cpu.icache.demand_accesses::total 7530 # number of demand (read+write) accesses 701system.cpu.icache.overall_accesses::cpu.inst 7530 # number of overall (read+write) accesses 702system.cpu.icache.overall_accesses::total 7530 # number of overall (read+write) accesses 703system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.077158 # miss rate for ReadReq accesses 704system.cpu.icache.ReadReq_miss_rate::total 0.077158 # miss rate for ReadReq accesses 705system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 # miss rate for demand accesses 706system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses 707system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses 708system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses 709system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency 710system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency 711system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency 712system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency 713system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency 714system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency 715system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked 716system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 717system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 718system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 719system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked 720system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 721system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits 722system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits 723system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits 724system.cpu.icache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits 725system.cpu.icache.overall_mshr_hits::cpu.inst 216 # number of overall MSHR hits 726system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits 727system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 728system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses 729system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 730system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses 731system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 732system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses 733system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles 734system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles 735system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles 736system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles 737system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles 738system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles 739system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for ReadReq accesses 740system.cpu.icache.ReadReq_mshr_miss_rate::total 0.048473 # mshr miss rate for ReadReq accesses 741system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for demand accesses 742system.cpu.icache.demand_mshr_miss_rate::total 0.048473 # mshr miss rate for demand accesses 743system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses 744system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses 745system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency 746system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency 747system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency 748system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency 749system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency 750system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency 751system.cpu.l2cache.tags.replacements 0 # number of replacements 752system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use 753system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 754system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 755system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks. 756system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 757system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor 758system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor 759system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy 760system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy 761system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy 762system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id 763system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 764system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id 765system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id 766system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses 767system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses 768system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 769system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 770system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 771system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 772system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 773system.cpu.l2cache.overall_hits::total 2 # number of overall hits 774system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 775system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 776system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses 777system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses 778system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses 779system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses 780system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 781system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses 782system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses 783system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses 784system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses 785system.cpu.l2cache.overall_misses::total 511 # number of overall misses 786system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6452500 # number of ReadExReq miss cycles 787system.cpu.l2cache.ReadExReq_miss_latency::total 6452500 # number of ReadExReq miss cycles 788system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27176000 # number of ReadCleanReq miss cycles 789system.cpu.l2cache.ReadCleanReq_miss_latency::total 27176000 # number of ReadCleanReq miss cycles 790system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5013500 # number of ReadSharedReq miss cycles 791system.cpu.l2cache.ReadSharedReq_miss_latency::total 5013500 # number of ReadSharedReq miss cycles 792system.cpu.l2cache.demand_miss_latency::cpu.inst 27176000 # number of demand (read+write) miss cycles 793system.cpu.l2cache.demand_miss_latency::cpu.data 11466000 # number of demand (read+write) miss cycles 794system.cpu.l2cache.demand_miss_latency::total 38642000 # number of demand (read+write) miss cycles 795system.cpu.l2cache.overall_miss_latency::cpu.inst 27176000 # number of overall miss cycles 796system.cpu.l2cache.overall_miss_latency::cpu.data 11466000 # number of overall miss cycles 797system.cpu.l2cache.overall_miss_latency::total 38642000 # number of overall miss cycles 798system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 799system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 800system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses) 801system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses) 802system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) 803system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) 804system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses 805system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses 806system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses 807system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses 808system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses 809system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses 810system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 811system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 812system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses 813system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses 814system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 815system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 816system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses 817system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 818system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses 819system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses 820system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 821system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses 822system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855 # average ReadExReq miss latency 823system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855 # average ReadExReq miss latency 824system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency 825system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency 826system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231 # average ReadSharedReq miss latency 827system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231 # average ReadSharedReq miss latency 828system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency 829system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency 830system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250 # average overall miss latency 831system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency 832system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency 833system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency 834system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 835system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 836system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 837system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 838system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 839system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 840system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 841system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 842system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 843system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses 844system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses 845system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses 846system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses 847system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 848system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses 850system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 851system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses 852system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles 853system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles 854system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles 855system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles 856system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles 857system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles 858system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles 859system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles 862system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles 864system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 865system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 866system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses 867system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses 868system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 869system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 870system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses 871system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 872system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses 873system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses 874system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 875system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses 876system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency 877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency 878system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency 879system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency 880system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency 881system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency 882system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency 883system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency 884system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency 886system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency 887system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency 888system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. 889system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 890system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 891system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 892system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 893system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 894system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution 895system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 896system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 897system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution 898system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution 899system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) 900system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 901system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes) 902system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) 903system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 904system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes) 905system.cpu.toL2Bus.snoops 0 # Total snoops (count) 906system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 910system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram 911system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram 912system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 913system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 914system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 915system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 916system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram 917system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks) 918system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 919system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks) 920system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 921system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) 922system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 923system.membus.trans_dist::ReadResp 426 # Transaction distribution 924system.membus.trans_dist::ReadExReq 83 # Transaction distribution 925system.membus.trans_dist::ReadExResp 83 # Transaction distribution 926system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution 927system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes) 928system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes) 929system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes) 930system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes) 931system.membus.snoops 0 # Total snoops (count) 932system.membus.snoop_fanout::samples 511 # Request fanout histogram 933system.membus.snoop_fanout::mean 0 # Request fanout histogram 934system.membus.snoop_fanout::stdev 0 # Request fanout histogram 935system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 936system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram 937system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 938system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 939system.membus.snoop_fanout::min_value 0 # Request fanout histogram 940system.membus.snoop_fanout::max_value 0 # Request fanout histogram 941system.membus.snoop_fanout::total 511 # Request fanout histogram 942system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks) 943system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) 944system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks) 945system.membus.respLayer1.utilization 9.3 # Layer utilization (%) 946 947---------- End Simulation Statistics ----------

stats.txt (11456:c0fb4435b80f)

stats.txt (11502:e273e86a873d)

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000029 # Number of seconds simulated
4sim_ticks 28845500 # Number of ticks simulated
5final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 68981 # Simulator instruction rate (inst/s)
8host_op_rate 68975 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 137812851 # Simulator tick rate (ticks/s)
10host_mem_usage 251992 # Number of bytes of host memory used
11host_seconds 0.21 # Real time elapsed on the host
12sim_insts 14436 # Number of instructions simulated
13sim_ops 14436 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
18system.physmem.bytes_read::total 32640 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 510 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 511 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 105 # Per bank write bursts
45system.physmem.perBankRdBursts::1 28 # Per bank write bursts
46system.physmem.perBankRdBursts::2 53 # Per bank write bursts
47system.physmem.perBankRdBursts::3 27 # Per bank write bursts
48system.physmem.perBankRdBursts::4 23 # Per bank write bursts
49system.physmem.perBankRdBursts::5 0 # Per bank write bursts
50system.physmem.perBankRdBursts::6 32 # Per bank write bursts
51system.physmem.perBankRdBursts::7 38 # Per bank write bursts
52system.physmem.perBankRdBursts::8 7 # Per bank write bursts
53system.physmem.perBankRdBursts::9 4 # Per bank write bursts
54system.physmem.perBankRdBursts::10 2 # Per bank write bursts
55system.physmem.perBankRdBursts::11 0 # Per bank write bursts
56system.physmem.perBankRdBursts::12 57 # Per bank write bursts
57system.physmem.perBankRdBursts::13 31 # Per bank write bursts
58system.physmem.perBankRdBursts::14 63 # Per bank write bursts
59system.physmem.perBankRdBursts::15 41 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 28814000 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 511 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 298 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 149 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 75 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 13 17.33% 17.33% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 5 6.67% 73.33% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::768-895 8 10.67% 84.00% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::896-1023 1 1.33% 85.33% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::1024-1151 11 14.67% 100.00% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::total 75 # Bytes accessed per row activation
202system.physmem.totQLat 3584250 # Total ticks spent queuing
203system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM
204system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers
205system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst
206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
207system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst
208system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s
209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
210system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s
211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
213system.physmem.busUtil 8.86 # Data bus utilization in percentage
214system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads
215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
216system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
218system.physmem.readRowHits 428 # Number of row buffer hits during reads
219system.physmem.writeRowHits 0 # Number of row buffer hits during writes
220system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads
221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
222system.physmem.avgGap 56387.48 # Average gap between requests
223system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined
224system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
225system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
226system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ)
227system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
228system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
229system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ)
230system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
231system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ)
232system.physmem_0.averagePower 856.515480 # Core power per rank (mW)
233system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states
234system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
235system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
236system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states
237system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
238system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ)
239system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ)
240system.physmem_1.readEnergy 1396200 # Energy for read commands per rank (pJ)
241system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
242system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
243system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ)
244system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ)
245system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ)
246system.physmem_1.averagePower 820.243027 # Core power per rank (mW)
247system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states
248system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
250system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states
251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
252system.cpu.branchPred.lookups 12618 # Number of BP lookups
253system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted
254system.cpu.branchPred.condIncorrect 1475 # Number of conditional branches incorrect
255system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups
256system.cpu.branchPred.BTBHits 0 # Number of BTB hits
257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
258system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
259system.cpu.branchPred.usedRAS 736 # Number of times the RAS was used to get a target.
260system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
261system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups.
262system.cpu.branchPred.indirectHits 1844 # Number of indirect target hits.
263system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses.
264system.cpu.branchPredindirectMispredicted 897 # Number of mispredicted indirect branches.
265system.cpu_clk_domain.clock 500 # Clock period in ticks
266system.cpu.workload.num_syscalls 18 # Number of system calls
267system.cpu.numCycles 57692 # number of cpu cycles simulated
268system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
269system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
270system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss
271system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed
272system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered
273system.cpu.fetch.predictedBranches 2580 # Number of branches that fetch has predicted taken
274system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked
275system.cpu.fetch.SquashCycles 3145 # Number of cycles fetch has spent squashing
276system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
277system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
278system.cpu.fetch.IcacheWaitRetryStallCycles 25 # Number of stall cycles due to full MSHR
279system.cpu.fetch.CacheLines 7530 # Number of cache lines fetched
280system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed
281system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total)
282system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total)
283system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total)
284system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total)
287system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total)
288system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total)
294system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
297system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total)
298system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle
299system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle
300system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle
301system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked
302system.cpu.decode.RunCycles 7933 # Number of cycles decode is running
303system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking
304system.cpu.decode.SquashCycles 1572 # Number of cycles decode is squashing
305system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode
306system.cpu.rename.SquashCycles 1572 # Number of cycles rename is squashing
307system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle
308system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking
309system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst
310system.cpu.rename.RunCycles 7918 # Number of cycles rename is running
311system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking
312system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename
313system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
314system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full
315system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed
316system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made
317system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups
318system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
319system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing
320system.cpu.rename.serializingInsts 796 # count of serializing insts renamed
321system.cpu.rename.tempSerializingInsts 801 # count of temporary serializing insts renamed
322system.cpu.rename.skidInsts 4352 # count of insts added to the skid buffer
323system.cpu.memDep0.insertedLoads 4576 # Number of loads inserted to the mem dependence unit.
324system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit.
325system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads.
326system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
327system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec)
328system.cpu.iq.iqNonSpecInstsAdded 757 # Number of non-speculative instructions added to the IQ
329system.cpu.iq.iqInstsIssued 25362 # Number of instructions issued
330system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
331system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling
332system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph
333system.cpu.iq.iqSquashedNonSpecRemoved 282 # Number of squashed non-spec instructions that were removed
334system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle
335system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle
336system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle
337system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
338system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle
339system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle
340system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle
341system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle
342system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle
343system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle
344system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle
345system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle
346system.cpu.iq.issued_per_cycle::8 100 0.28% 100.00% # Number of insts issued each cycle
347system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
348system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
349system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
350system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle
351system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
352system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available
353system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available
354system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available
355system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available
356system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available
357system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available
358system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available
359system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available
360system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
361system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available
362system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available
363system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available
373system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available
374system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available
375system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available
376system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available
377system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available
378system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available
379system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available
380system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
381system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available
382system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available
383system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
384system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
385system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
386system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued
387system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued
388system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued
389system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued
390system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued
391system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued
392system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued
393system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued
394system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued
395system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued
396system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued
397system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued
407system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued
408system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued
409system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued
410system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued
411system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued
412system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued
413system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued
415system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued
416system.cpu.iq.FU_type_0::MemWrite 2506 9.88% 100.00% # Type of FU issued
417system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
418system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
419system.cpu.iq.FU_type_0::total 25362 # Type of FU issued
420system.cpu.iq.rate 0.439610 # Inst issue rate
421system.cpu.iq.fu_busy_cnt 294 # FU busy when requested
422system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst)
423system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads
424system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes
425system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses
426system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
427system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
428system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
429system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses
430system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
431system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores
432system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
433system.cpu.iew.lsq.thread0.squashedLoads 2351 # Number of loads squashed
434system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
435system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations
436system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed
437system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
438system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
439system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
440system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
441system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
442system.cpu.iew.iewSquashCycles 1572 # Number of cycles IEW is squashing
443system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking
444system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
445system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ
446system.cpu.iew.iewDispSquashedInsts 242 # Number of squashed instructions skipped by dispatch
447system.cpu.iew.iewDispLoadInsts 4576 # Number of dispatched load instructions
448system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions
449system.cpu.iew.iewDispNonSpecInsts 757 # Number of dispatched non-speculative instructions
450system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
451system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
452system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
453system.cpu.iew.predictedTakenIncorrect 211 # Number of branches that were predicted taken incorrectly
454system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly
455system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute
456system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions
457system.cpu.iew.iewExecLoadInsts 3945 # Number of load instructions executed
458system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute
459system.cpu.iew.exec_swp 0 # number of swp insts executed
460system.cpu.iew.exec_nop 1579 # number of nop insts executed
461system.cpu.iew.exec_refs 6244 # number of memory reference insts executed
462system.cpu.iew.exec_branches 5021 # Number of branches executed
463system.cpu.iew.exec_stores 2299 # Number of stores executed
464system.cpu.iew.exec_rate 0.411045 # Inst execution rate
465system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit
466system.cpu.iew.wb_count 22607 # cumulative count of insts written-back
467system.cpu.iew.wb_producers 10530 # num instructions producing a value
468system.cpu.iew.wb_consumers 13790 # num instructions consuming a value
469system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle
470system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back
471system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit
472system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
473system.cpu.commit.branchMispredicts 1475 # The number of times a branch was mispredicted
474system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle
475system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle
476system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle
477system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle
479system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle
480system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle
481system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle
482system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::6 374 1.15% 99.14% # Number of insts commited each cycle
485system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle
486system.cpu.commit.committed_per_cycle::8 228 0.70% 100.00% # Number of insts commited each cycle
487system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
488system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
489system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
490system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle
491system.cpu.commit.committedInsts 15162 # Number of instructions committed
492system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
493system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
494system.cpu.commit.refs 3673 # Number of memory references committed
495system.cpu.commit.loads 2225 # Number of loads committed
496system.cpu.commit.membars 0 # Number of memory barriers committed
497system.cpu.commit.branches 3358 # Number of branches committed
498system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
499system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
500system.cpu.commit.function_calls 187 # Number of function calls committed.
501system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
502system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
503system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
504system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
505system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
506system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
507system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
508system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
509system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
510system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
511system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
512system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
513system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
514system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
515system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
516system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
517system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
518system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
519system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
520system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
521system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
522system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
523system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
524system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
525system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
526system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
527system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
528system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
529system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
530system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
531system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
532system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
533system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
534system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
535system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
536system.cpu.commit.bw_lim_events 228 # number cycles where commit BW limit reached
537system.cpu.rob.rob_reads 62581 # The number of ROB reads
538system.cpu.rob.rob_writes 65380 # The number of ROB writes
539system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself
540system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling
541system.cpu.committedInsts 14436 # Number of Instructions Simulated
542system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
543system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction
544system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads
545system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle
546system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads
547system.cpu.int_regfile_reads 36850 # number of integer regfile reads
548system.cpu.int_regfile_writes 20548 # number of integer regfile writes
549system.cpu.misc_regfile_reads 8142 # number of misc regfile reads
550system.cpu.misc_regfile_writes 569 # number of misc regfile writes
551system.cpu.dcache.tags.replacements 0 # number of replacements
552system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use
553system.cpu.dcache.tags.total_refs 4648 # Total number of references to valid blocks.
554system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
555system.cpu.dcache.tags.avg_refs 31.835616 # Average number of references to valid blocks.
556system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
557system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor
558system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy
559system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy
560system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
561system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
562system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
563system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
564system.cpu.dcache.tags.tag_accesses 10540 # Number of tag accesses
565system.cpu.dcache.tags.data_accesses 10540 # Number of data accesses
566system.cpu.dcache.ReadReq_hits::cpu.data 3609 # number of ReadReq hits
567system.cpu.dcache.ReadReq_hits::total 3609 # number of ReadReq hits
568system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
569system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
570system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
571system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
572system.cpu.dcache.demand_hits::cpu.data 4642 # number of demand (read+write) hits
573system.cpu.dcache.demand_hits::total 4642 # number of demand (read+write) hits
574system.cpu.dcache.overall_hits::cpu.data 4642 # number of overall hits
575system.cpu.dcache.overall_hits::total 4642 # number of overall hits
576system.cpu.dcache.ReadReq_misses::cpu.data 140 # number of ReadReq misses
577system.cpu.dcache.ReadReq_misses::total 140 # number of ReadReq misses
578system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
579system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
580system.cpu.dcache.demand_misses::cpu.data 549 # number of demand (read+write) misses
581system.cpu.dcache.demand_misses::total 549 # number of demand (read+write) misses
582system.cpu.dcache.overall_misses::cpu.data 549 # number of overall misses
583system.cpu.dcache.overall_misses::total 549 # number of overall misses
584system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles
585system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles
586system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles
587system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles
588system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles
589system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles
590system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles
591system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles
592system.cpu.dcache.ReadReq_accesses::cpu.data 3749 # number of ReadReq accesses(hits+misses)
593system.cpu.dcache.ReadReq_accesses::total 3749 # number of ReadReq accesses(hits+misses)
594system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
595system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
596system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
597system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
598system.cpu.dcache.demand_accesses::cpu.data 5191 # number of demand (read+write) accesses
599system.cpu.dcache.demand_accesses::total 5191 # number of demand (read+write) accesses
600system.cpu.dcache.overall_accesses::cpu.data 5191 # number of overall (read+write) accesses
601system.cpu.dcache.overall_accesses::total 5191 # number of overall (read+write) accesses
602system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037343 # miss rate for ReadReq accesses
603system.cpu.dcache.ReadReq_miss_rate::total 0.037343 # miss rate for ReadReq accesses
604system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
605system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
606system.cpu.dcache.demand_miss_rate::cpu.data 0.105760 # miss rate for demand accesses
607system.cpu.dcache.demand_miss_rate::total 0.105760 # miss rate for demand accesses
608system.cpu.dcache.overall_miss_rate::cpu.data 0.105760 # miss rate for overall accesses
609system.cpu.dcache.overall_miss_rate::total 0.105760 # miss rate for overall accesses
610system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency
611system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency
612system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency
613system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency
614system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
615system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency
616system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
617system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency
618system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked
619system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
620system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked
621system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
622system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked
623system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
624system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits
625system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits
626system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
627system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
628system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits
629system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits
630system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits
631system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits
632system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
633system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
634system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
635system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
636system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
637system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
638system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
639system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses
640system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles
641system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles
642system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles
643system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles
644system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles
645system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles
646system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles
647system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles
648system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017338 # mshr miss rate for ReadReq accesses
649system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017338 # mshr miss rate for ReadReq accesses
650system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
651system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
652system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for demand accesses
653system.cpu.dcache.demand_mshr_miss_rate::total 0.028511 # mshr miss rate for demand accesses
654system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028511 # mshr miss rate for overall accesses
655system.cpu.dcache.overall_mshr_miss_rate::total 0.028511 # mshr miss rate for overall accesses
656system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency
657system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency
658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency
659system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency
660system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
661system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
662system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
663system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
664system.cpu.icache.tags.replacements 0 # number of replacements
665system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use
666system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks.
667system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
668system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks.
669system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
670system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor
671system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy
672system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy
673system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
674system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
675system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
676system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
677system.cpu.icache.tags.tag_accesses 15425 # Number of tag accesses
678system.cpu.icache.tags.data_accesses 15425 # Number of data accesses
679system.cpu.icache.ReadReq_hits::cpu.inst 6949 # number of ReadReq hits
680system.cpu.icache.ReadReq_hits::total 6949 # number of ReadReq hits
681system.cpu.icache.demand_hits::cpu.inst 6949 # number of demand (read+write) hits
682system.cpu.icache.demand_hits::total 6949 # number of demand (read+write) hits
683system.cpu.icache.overall_hits::cpu.inst 6949 # number of overall hits
684system.cpu.icache.overall_hits::total 6949 # number of overall hits
685system.cpu.icache.ReadReq_misses::cpu.inst 581 # number of ReadReq misses
686system.cpu.icache.ReadReq_misses::total 581 # number of ReadReq misses
687system.cpu.icache.demand_misses::cpu.inst 581 # number of demand (read+write) misses
688system.cpu.icache.demand_misses::total 581 # number of demand (read+write) misses
689system.cpu.icache.overall_misses::cpu.inst 581 # number of overall misses
690system.cpu.icache.overall_misses::total 581 # number of overall misses
691system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles
692system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles
693system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles
694system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles
695system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles
696system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles
697system.cpu.icache.ReadReq_accesses::cpu.inst 7530 # number of ReadReq accesses(hits+misses)
698system.cpu.icache.ReadReq_accesses::total 7530 # number of ReadReq accesses(hits+misses)
699system.cpu.icache.demand_accesses::cpu.inst 7530 # number of demand (read+write) accesses
700system.cpu.icache.demand_accesses::total 7530 # number of demand (read+write) accesses
701system.cpu.icache.overall_accesses::cpu.inst 7530 # number of overall (read+write) accesses
702system.cpu.icache.overall_accesses::total 7530 # number of overall (read+write) accesses
703system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.077158 # miss rate for ReadReq accesses
704system.cpu.icache.ReadReq_miss_rate::total 0.077158 # miss rate for ReadReq accesses
705system.cpu.icache.demand_miss_rate::cpu.inst 0.077158 # miss rate for demand accesses
706system.cpu.icache.demand_miss_rate::total 0.077158 # miss rate for demand accesses
707system.cpu.icache.overall_miss_rate::cpu.inst 0.077158 # miss rate for overall accesses
708system.cpu.icache.overall_miss_rate::total 0.077158 # miss rate for overall accesses
709system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency
710system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency
711system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
712system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency
713system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
714system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency
715system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked
716system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
717system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
718system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
719system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked
720system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
721system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits
722system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits
723system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits
724system.cpu.icache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits
725system.cpu.icache.overall_mshr_hits::cpu.inst 216 # number of overall MSHR hits
726system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits
727system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses
728system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses
729system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses
730system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
731system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
732system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
733system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles
734system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles
735system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles
736system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles
737system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles
738system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles
739system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for ReadReq accesses
740system.cpu.icache.ReadReq_mshr_miss_rate::total 0.048473 # mshr miss rate for ReadReq accesses
741system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for demand accesses
742system.cpu.icache.demand_mshr_miss_rate::total 0.048473 # mshr miss rate for demand accesses
743system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses
744system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses
745system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency
746system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency
747system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
748system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
749system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
750system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
751system.cpu.l2cache.tags.replacements 0 # number of replacements
752system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use
753system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
754system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
755system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks.
756system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
757system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor
758system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor
759system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy
760system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy
761system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy
762system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id
763system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
764system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
765system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
766system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses
767system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses
768system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
769system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
770system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
771system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
772system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
773system.cpu.l2cache.overall_hits::total 2 # number of overall hits
774system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
775system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
776system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses
777system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses
778system.cpu.l2cache.ReadSharedReq_misses::cpu.data 65 # number of ReadSharedReq misses
779system.cpu.l2cache.ReadSharedReq_misses::total 65 # number of ReadSharedReq misses
780system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
781system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses
782system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses
783system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
784system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses
785system.cpu.l2cache.overall_misses::total 511 # number of overall misses
786system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6452500 # number of ReadExReq miss cycles
787system.cpu.l2cache.ReadExReq_miss_latency::total 6452500 # number of ReadExReq miss cycles
788system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27176000 # number of ReadCleanReq miss cycles
789system.cpu.l2cache.ReadCleanReq_miss_latency::total 27176000 # number of ReadCleanReq miss cycles
790system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5013500 # number of ReadSharedReq miss cycles
791system.cpu.l2cache.ReadSharedReq_miss_latency::total 5013500 # number of ReadSharedReq miss cycles
792system.cpu.l2cache.demand_miss_latency::cpu.inst 27176000 # number of demand (read+write) miss cycles
793system.cpu.l2cache.demand_miss_latency::cpu.data 11466000 # number of demand (read+write) miss cycles
794system.cpu.l2cache.demand_miss_latency::total 38642000 # number of demand (read+write) miss cycles
795system.cpu.l2cache.overall_miss_latency::cpu.inst 27176000 # number of overall miss cycles
796system.cpu.l2cache.overall_miss_latency::cpu.data 11466000 # number of overall miss cycles
797system.cpu.l2cache.overall_miss_latency::total 38642000 # number of overall miss cycles
798system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
799system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
800system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses)
801system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses)
802system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses)
803system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses)
804system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses
805system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
806system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses
807system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses
808system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
809system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses
810system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
811system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
812system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses
813system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses
814system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
815system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
816system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses
817system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
818system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses
819system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses
820system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
821system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses
822system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855 # average ReadExReq miss latency
823system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855 # average ReadExReq miss latency
824system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency
825system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency
826system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231 # average ReadSharedReq miss latency
827system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231 # average ReadSharedReq miss latency
828system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency
829system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency
830system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250 # average overall miss latency
831system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency
832system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency
833system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency
834system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
835system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
836system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
837system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
838system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
839system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
840system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
841system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
842system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses
843system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses
844system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses
845system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses
846system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses
847system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
848system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses
849system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
850system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
851system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses
852system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles
853system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles
854system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles
855system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles
856system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles
857system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles
858system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles
859system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles
860system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles
861system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles
862system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles
863system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles
864system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
865system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
866system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses
867system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses
868system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
869system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
870system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses
871system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
872system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses
873system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses
874system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
875system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses
876system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency
877system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency
878system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency
879system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency
880system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency
881system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency
882system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
883system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
884system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
885system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
886system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
887system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
888system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter.
889system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
890system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
891system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
892system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
893system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
894system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution
895system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
896system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
897system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution
898system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution
899system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
900system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes)
901system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes)
902system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
903system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
904system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes)
905system.cpu.toL2Bus.snoops 0 # Total snoops (count)
906system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram
907system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram
908system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram
909system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
910system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram
911system.cpu.toL2Bus.snoop_fanout::1 2 0.39% 100.00% # Request fanout histogram
912system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
913system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
914system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
915system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
916system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram
917system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks)
918system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
919system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks)
920system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
921system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks)
922system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
923system.membus.trans_dist::ReadResp 426 # Transaction distribution
924system.membus.trans_dist::ReadExReq 83 # Transaction distribution
925system.membus.trans_dist::ReadExResp 83 # Transaction distribution
926system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution
927system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes)
928system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes)
929system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes)
930system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes)
931system.membus.snoops 0 # Total snoops (count)
932system.membus.snoop_fanout::samples 511 # Request fanout histogram
933system.membus.snoop_fanout::mean 0 # Request fanout histogram
934system.membus.snoop_fanout::stdev 0 # Request fanout histogram
935system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
936system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram
937system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
938system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
939system.membus.snoop_fanout::min_value 0 # Request fanout histogram
940system.membus.snoop_fanout::max_value 0 # Request fanout histogram
941system.membus.snoop_fanout::total 511 # Request fanout histogram
942system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks)
943system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
944system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks)
945system.membus.respLayer1.utilization 9.3 # Layer utilization (%)
946
947---------- End Simulation Statistics ----------