| stats.txt (11440:76b5639162af) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000029 # Number of seconds simulated 4sim_ticks 28845500 # Number of ticks simulated 5final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000029 # Number of seconds simulated 4sim_ticks 28845500 # Number of ticks simulated 5final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 12271 # Simulator instruction rate (inst/s) 8host_op_rate 12271 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 22902062 # Simulator tick rate (ticks/s) 10host_mem_usage 227268 # Number of bytes of host memory used 11host_seconds 1.18 # Real time elapsed on the host | 7host_inst_rate 68981 # Simulator instruction rate (inst/s) 8host_op_rate 68975 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 137812851 # Simulator tick rate (ticks/s) 10host_mem_usage 251992 # Number of bytes of host memory used 11host_seconds 0.21 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 18system.physmem.bytes_read::total 32640 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory --- 596 unchanged lines hidden (view full) --- 616system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency 617system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency 618system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked 619system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 620system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked 621system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 622system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked 623system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 18system.physmem.bytes_read::total 32640 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory --- 596 unchanged lines hidden (view full) --- 616system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency 617system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency 618system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked 619system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 620system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked 621system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 622system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked 623system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 624system.cpu.dcache.fast_writes 0 # number of fast writes performed 625system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 626system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits 627system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits 628system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 629system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits 630system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits 631system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits 632system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits 633system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 658system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency 659system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency 661system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency 663system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency 665system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency | 624system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits 625system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits 626system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 627system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits 628system.cpu.dcache.demand_mshr_hits::cpu.data 401 # number of demand (read+write) MSHR hits 629system.cpu.dcache.demand_mshr_hits::total 401 # number of demand (read+write) MSHR hits 630system.cpu.dcache.overall_mshr_hits::cpu.data 401 # number of overall MSHR hits 631system.cpu.dcache.overall_mshr_hits::total 401 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 656system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency 657system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency 658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency 659system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency 660system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency 661system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency 662system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency 663system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency |
| 666system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 667system.cpu.icache.tags.replacements 0 # number of replacements 668system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use 669system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. 670system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 671system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. 672system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 673system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor 674system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 716system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency 718system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked 719system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 721system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked 723system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 664system.cpu.icache.tags.replacements 0 # number of replacements 665system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use 666system.cpu.icache.tags.total_refs 6949 # Total number of references to valid blocks. 667system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 668system.cpu.icache.tags.avg_refs 19.038356 # Average number of references to valid blocks. 669system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 670system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor 671system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 713system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency 714system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency 715system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked 716system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 717system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 718system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 719system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked 720system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 724system.cpu.icache.fast_writes 0 # number of fast writes performed 725system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 726system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits 727system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits 728system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits 729system.cpu.icache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits 730system.cpu.icache.overall_mshr_hits::cpu.inst 216 # number of overall MSHR hits 731system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits 732system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 733system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses --- 14 unchanged lines hidden (view full) --- 748system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses 749system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency 751system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency 753system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency 755system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency | 721system.cpu.icache.ReadReq_mshr_hits::cpu.inst 216 # number of ReadReq MSHR hits 722system.cpu.icache.ReadReq_mshr_hits::total 216 # number of ReadReq MSHR hits 723system.cpu.icache.demand_mshr_hits::cpu.inst 216 # number of demand (read+write) MSHR hits 724system.cpu.icache.demand_mshr_hits::total 216 # number of demand (read+write) MSHR hits 725system.cpu.icache.overall_mshr_hits::cpu.inst 216 # number of overall MSHR hits 726system.cpu.icache.overall_mshr_hits::total 216 # number of overall MSHR hits 727system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 728system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses --- 14 unchanged lines hidden (view full) --- 743system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.048473 # mshr miss rate for overall accesses 744system.cpu.icache.overall_mshr_miss_rate::total 0.048473 # mshr miss rate for overall accesses 745system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency 746system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency 747system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency 748system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency 749system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency 750system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency |
| 756system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 757system.cpu.l2cache.tags.replacements 0 # number of replacements 758system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use 759system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 760system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 761system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks. 762system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 763system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor 764system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 838system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency 839system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency 840system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 841system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 842system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 843system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 844system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 845system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 751system.cpu.l2cache.tags.replacements 0 # number of replacements 752system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use 753system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 754system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 755system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks. 756system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 757system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor 758system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor --- 73 unchanged lines hidden (view full) --- 832system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency 833system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency 834system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 835system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 836system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 837system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 838system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 839system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 846system.cpu.l2cache.fast_writes 0 # number of fast writes performed 847system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 848system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 849system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 850system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 851system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses 852system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses 853system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses 854system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses 855system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 888system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency 889system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency 890system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency 891system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency 892system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency 895system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency | 840system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 841system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 842system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 843system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses 844system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 65 # number of ReadSharedReq MSHR misses 845system.cpu.l2cache.ReadSharedReq_mshr_misses::total 65 # number of ReadSharedReq MSHR misses 846system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses 847system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 880system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency 881system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency 882system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency 883system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency 884system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency 886system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency 887system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency |
| 896system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 897system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. 898system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 899system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 900system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 901system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 902system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 903system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution 904system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution --- 52 unchanged lines hidden --- | 888system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter. 889system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 890system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 891system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 892system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 893system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 894system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution 895system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution --- 52 unchanged lines hidden --- |