| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated |
| 4sim_ticks 26943000 # Number of ticks simulated 5final_tick 26943000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 26944000 # Number of ticks simulated 5final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 30305 # Simulator instruction rate (inst/s) 8host_op_rate 30304 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56555572 # Simulator tick rate (ticks/s) 10host_mem_usage 288252 # Number of bytes of host memory used 11host_seconds 0.48 # Real time elapsed on the host | 7host_inst_rate 95332 # Simulator instruction rate (inst/s) 8host_op_rate 95323 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 177899852 # Simulator tick rate (ticks/s) 10host_mem_usage 294468 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21888 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31296 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21888 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21888 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 342 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 489 # Number of read requests responded to by this memory | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21888 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31296 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21888 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21888 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 342 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 489 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 812381695 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 349181606 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1161563300 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 812381695 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 812381695 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 812381695 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 349181606 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1161563300 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 812351544 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 349168646 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1161520190 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 812351544 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 812351544 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 812351544 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 349168646 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1161520190 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 489 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 489 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 31296 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 31296 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 489 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 489 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 31296 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 31296 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 26890000 # Total gap between requests | 78system.physmem.totGap 26891000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 489 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 114 unchanged lines hidden (view full) --- 201system.physmem.bytesPerActivate::1024-1151 10 13.70% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 73 # Bytes accessed per row activation 203system.physmem.totQLat 3681750 # Total ticks spent queuing 204system.physmem.totMemAccLat 12850500 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2445000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7529.14 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 26279.14 # Average memory access latency per DRAM burst | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 489 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 114 unchanged lines hidden (view full) --- 201system.physmem.bytesPerActivate::1024-1151 10 13.70% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 73 # Bytes accessed per row activation 203system.physmem.totQLat 3681750 # Total ticks spent queuing 204system.physmem.totMemAccLat 12850500 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2445000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 7529.14 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 26279.14 # Average memory access latency per DRAM burst |
| 209system.physmem.avgRdBW 1161.56 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgRdBW 1161.52 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1161.56 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1161.52 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 9.07 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.07 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 409 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 9.07 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.07 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 409 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 54989.78 # Average gap between requests | 223system.physmem.avgGap 54991.82 # Average gap between requests |
| 224system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 15849990 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 267750 # Energy for precharge background per rank (pJ) --- 8 unchanged lines hidden (view full) --- 240system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 15637950 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 453750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 19309500 # Total energy per rank (pJ) 247system.physmem_1.averagePower 817.549616 # Core power per rank (mW) | 224system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 15849990 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 267750 # Energy for precharge background per rank (pJ) --- 8 unchanged lines hidden (view full) --- 240system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 15637950 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 453750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 19309500 # Total energy per rank (pJ) 247system.physmem_1.averagePower 817.549616 # Core power per rank (mW) |
| 248system.physmem_1.memoryStateTime::IDLE 2039000 # Time in different power states | 248system.physmem_1.memoryStateTime::IDLE 2040000 # Time in different power states |
| 249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 22166500 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 8026 # Number of BP lookups 254system.cpu.branchPred.condPredicted 5198 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 978 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 5876 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 3165 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 53.863172 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 554 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.workload.num_syscalls 18 # Number of system calls | 249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 22166500 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 8026 # Number of BP lookups 254system.cpu.branchPred.condPredicted 5198 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 978 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 5876 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 3165 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 53.863172 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 554 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.workload.num_syscalls 18 # Number of system calls |
| 264system.cpu.numCycles 53887 # number of cpu cycles simulated | 264system.cpu.numCycles 53889 # number of cpu cycles simulated |
| 265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 267system.cpu.fetch.icacheStallCycles 13793 # Number of cycles fetch is stalled on an Icache miss | 267system.cpu.fetch.icacheStallCycles 13792 # Number of cycles fetch is stalled on an Icache miss |
| 268system.cpu.fetch.Insts 37180 # Number of instructions fetch has processed 269system.cpu.fetch.Branches 8026 # Number of branches that fetch encountered 270system.cpu.fetch.predictedBranches 3719 # Number of branches that fetch has predicted taken | 268system.cpu.fetch.Insts 37180 # Number of instructions fetch has processed 269system.cpu.fetch.Branches 8026 # Number of branches that fetch encountered 270system.cpu.fetch.predictedBranches 3719 # Number of branches that fetch has predicted taken |
| 271system.cpu.fetch.Cycles 15451 # Number of cycles fetch has run and was not squashing or blocked | 271system.cpu.fetch.Cycles 15452 # Number of cycles fetch has run and was not squashing or blocked |
| 272system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing 273system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 274system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps 275system.cpu.fetch.CacheLines 6095 # Number of cache lines fetched 276system.cpu.fetch.IcacheSquashes 549 # Number of outstanding Icache misses that were squashed 277system.cpu.fetch.rateDist::samples 31410 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::mean 1.183699 # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::stdev 2.297330 # Number of instructions fetched each cycle (Total) --- 6 unchanged lines hidden (view full) --- 286system.cpu.fetch.rateDist::5 907 2.89% 91.22% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::6 332 1.06% 92.27% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::7 377 1.20% 93.47% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::8 2050 6.53% 100.00% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::total 31410 # Number of instructions fetched each cycle (Total) | 272system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing 273system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 274system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps 275system.cpu.fetch.CacheLines 6095 # Number of cache lines fetched 276system.cpu.fetch.IcacheSquashes 549 # Number of outstanding Icache misses that were squashed 277system.cpu.fetch.rateDist::samples 31410 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::mean 1.183699 # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::stdev 2.297330 # Number of instructions fetched each cycle (Total) --- 6 unchanged lines hidden (view full) --- 286system.cpu.fetch.rateDist::5 907 2.89% 91.22% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::6 332 1.06% 92.27% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::7 377 1.20% 93.47% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::8 2050 6.53% 100.00% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::total 31410 # Number of instructions fetched each cycle (Total) |
| 294system.cpu.fetch.branchRate 0.148941 # Number of branch fetches per cycle 295system.cpu.fetch.rate 0.689962 # Number of inst fetches per cycle | 294system.cpu.fetch.branchRate 0.148936 # Number of branch fetches per cycle 295system.cpu.fetch.rate 0.689937 # Number of inst fetches per cycle |
| 296system.cpu.decode.IdleCycles 10981 # Number of cycles decode is idle 297system.cpu.decode.BlockedCycles 12209 # Number of cycles decode is blocked 298system.cpu.decode.RunCycles 6549 # Number of cycles decode is running 299system.cpu.decode.UnblockCycles 597 # Number of cycles decode is unblocking 300system.cpu.decode.SquashCycles 1074 # Number of cycles decode is squashing 301system.cpu.decode.DecodedInsts 28093 # Number of instructions handled by decode 302system.cpu.rename.SquashCycles 1074 # Number of cycles rename is squashing 303system.cpu.rename.IdleCycles 11557 # Number of cycles rename is idle --- 104 unchanged lines hidden (view full) --- 408system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued 411system.cpu.iq.FU_type_0::MemRead 3355 16.10% 89.98% # Type of FU issued 412system.cpu.iq.FU_type_0::MemWrite 2088 10.02% 100.00% # Type of FU issued 413system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 414system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 415system.cpu.iq.FU_type_0::total 20835 # Type of FU issued | 296system.cpu.decode.IdleCycles 10981 # Number of cycles decode is idle 297system.cpu.decode.BlockedCycles 12209 # Number of cycles decode is blocked 298system.cpu.decode.RunCycles 6549 # Number of cycles decode is running 299system.cpu.decode.UnblockCycles 597 # Number of cycles decode is unblocking 300system.cpu.decode.SquashCycles 1074 # Number of cycles decode is squashing 301system.cpu.decode.DecodedInsts 28093 # Number of instructions handled by decode 302system.cpu.rename.SquashCycles 1074 # Number of cycles rename is squashing 303system.cpu.rename.IdleCycles 11557 # Number of cycles rename is idle --- 104 unchanged lines hidden (view full) --- 408system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued 411system.cpu.iq.FU_type_0::MemRead 3355 16.10% 89.98% # Type of FU issued 412system.cpu.iq.FU_type_0::MemWrite 2088 10.02% 100.00% # Type of FU issued 413system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 414system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 415system.cpu.iq.FU_type_0::total 20835 # Type of FU issued |
| 416system.cpu.iq.rate 0.386642 # Inst issue rate | 416system.cpu.iq.rate 0.386628 # Inst issue rate |
| 417system.cpu.iq.fu_busy_cnt 177 # FU busy when requested 418system.cpu.iq.fu_busy_rate 0.008495 # FU busy rate (busy events/executed inst) 419system.cpu.iq.int_inst_queue_reads 73265 # Number of integer instruction queue reads 420system.cpu.iq.int_inst_queue_writes 31060 # Number of integer instruction queue writes 421system.cpu.iq.int_inst_queue_wakeup_accesses 19408 # Number of integer instruction queue wakeup accesses 422system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 423system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 424system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses --- 27 unchanged lines hidden (view full) --- 452system.cpu.iew.iewExecutedInsts 20012 # Number of executed instructions 453system.cpu.iew.iewExecLoadInsts 3241 # Number of load instructions executed 454system.cpu.iew.iewExecSquashedInsts 823 # Number of squashed instructions skipped in execute 455system.cpu.iew.exec_swp 0 # number of swp insts executed 456system.cpu.iew.exec_nop 1117 # number of nop insts executed 457system.cpu.iew.exec_refs 5240 # number of memory reference insts executed 458system.cpu.iew.exec_branches 4296 # Number of branches executed 459system.cpu.iew.exec_stores 1999 # Number of stores executed | 417system.cpu.iq.fu_busy_cnt 177 # FU busy when requested 418system.cpu.iq.fu_busy_rate 0.008495 # FU busy rate (busy events/executed inst) 419system.cpu.iq.int_inst_queue_reads 73265 # Number of integer instruction queue reads 420system.cpu.iq.int_inst_queue_writes 31060 # Number of integer instruction queue writes 421system.cpu.iq.int_inst_queue_wakeup_accesses 19408 # Number of integer instruction queue wakeup accesses 422system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 423system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 424system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses --- 27 unchanged lines hidden (view full) --- 452system.cpu.iew.iewExecutedInsts 20012 # Number of executed instructions 453system.cpu.iew.iewExecLoadInsts 3241 # Number of load instructions executed 454system.cpu.iew.iewExecSquashedInsts 823 # Number of squashed instructions skipped in execute 455system.cpu.iew.exec_swp 0 # number of swp insts executed 456system.cpu.iew.exec_nop 1117 # number of nop insts executed 457system.cpu.iew.exec_refs 5240 # number of memory reference insts executed 458system.cpu.iew.exec_branches 4296 # Number of branches executed 459system.cpu.iew.exec_stores 1999 # Number of stores executed |
| 460system.cpu.iew.exec_rate 0.371370 # Inst execution rate | 460system.cpu.iew.exec_rate 0.371356 # Inst execution rate |
| 461system.cpu.iew.wb_sent 19648 # cumulative count of insts sent to commit 462system.cpu.iew.wb_count 19408 # cumulative count of insts written-back 463system.cpu.iew.wb_producers 9326 # num instructions producing a value 464system.cpu.iew.wb_consumers 12017 # num instructions consuming a value 465system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 461system.cpu.iew.wb_sent 19648 # cumulative count of insts sent to commit 462system.cpu.iew.wb_count 19408 # cumulative count of insts written-back 463system.cpu.iew.wb_producers 9326 # num instructions producing a value 464system.cpu.iew.wb_consumers 12017 # num instructions consuming a value 465system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 466system.cpu.iew.wb_rate 0.360161 # insts written-back per cycle | 466system.cpu.iew.wb_rate 0.360148 # insts written-back per cycle |
| 467system.cpu.iew.wb_fanout 0.776067 # average fanout of values written-back 468system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 469system.cpu.commit.commitSquashedInsts 8625 # The number of squashed insts skipped by commit 470system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 471system.cpu.commit.branchMispredicts 978 # The number of times a branch was mispredicted 472system.cpu.commit.committed_per_cycle::samples 29597 # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::mean 0.512282 # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::stdev 1.339725 # Number of insts commited each cycle --- 55 unchanged lines hidden (view full) --- 530system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 531system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 532system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::total 15162 # Class of committed instruction 534system.cpu.commit.bw_lim_events 290 # number cycles where commit BW limit reached 535system.cpu.rob.rob_reads 52271 # The number of ROB reads 536system.cpu.rob.rob_writes 49405 # The number of ROB writes 537system.cpu.timesIdled 197 # Number of times that the entire CPU went into an idle state and unscheduled itself | 467system.cpu.iew.wb_fanout 0.776067 # average fanout of values written-back 468system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 469system.cpu.commit.commitSquashedInsts 8625 # The number of squashed insts skipped by commit 470system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 471system.cpu.commit.branchMispredicts 978 # The number of times a branch was mispredicted 472system.cpu.commit.committed_per_cycle::samples 29597 # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::mean 0.512282 # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::stdev 1.339725 # Number of insts commited each cycle --- 55 unchanged lines hidden (view full) --- 530system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 531system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 532system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::total 15162 # Class of committed instruction 534system.cpu.commit.bw_lim_events 290 # number cycles where commit BW limit reached 535system.cpu.rob.rob_reads 52271 # The number of ROB reads 536system.cpu.rob.rob_writes 49405 # The number of ROB writes 537system.cpu.timesIdled 197 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 538system.cpu.idleCycles 22477 # Total number of cycles that the CPU has spent unscheduled due to idling | 538system.cpu.idleCycles 22479 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 539system.cpu.committedInsts 14436 # Number of Instructions Simulated 540system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated | 539system.cpu.committedInsts 14436 # Number of Instructions Simulated 540system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated |
| 541system.cpu.cpi 3.732821 # CPI: Cycles Per Instruction 542system.cpu.cpi_total 3.732821 # CPI: Total CPI of All Threads 543system.cpu.ipc 0.267894 # IPC: Instructions Per Cycle 544system.cpu.ipc_total 0.267894 # IPC: Total IPC of All Threads | 541system.cpu.cpi 3.732959 # CPI: Cycles Per Instruction 542system.cpu.cpi_total 3.732959 # CPI: Total CPI of All Threads 543system.cpu.ipc 0.267884 # IPC: Instructions Per Cycle 544system.cpu.ipc_total 0.267884 # IPC: Total IPC of All Threads |
| 545system.cpu.int_regfile_reads 32029 # number of integer regfile reads 546system.cpu.int_regfile_writes 17799 # number of integer regfile writes 547system.cpu.misc_regfile_reads 6992 # number of misc regfile reads 548system.cpu.misc_regfile_writes 569 # number of misc regfile writes 549system.cpu.dcache.tags.replacements 0 # number of replacements | 545system.cpu.int_regfile_reads 32029 # number of integer regfile reads 546system.cpu.int_regfile_writes 17799 # number of integer regfile writes 547system.cpu.misc_regfile_reads 6992 # number of misc regfile reads 548system.cpu.misc_regfile_writes 569 # number of misc regfile writes 549system.cpu.dcache.tags.replacements 0 # number of replacements |
| 550system.cpu.dcache.tags.tagsinuse 98.068517 # Cycle average of tags in use | 550system.cpu.dcache.tags.tagsinuse 98.069813 # Cycle average of tags in use |
| 551system.cpu.dcache.tags.total_refs 4030 # Total number of references to valid blocks. 552system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 553system.cpu.dcache.tags.avg_refs 27.602740 # Average number of references to valid blocks. 554system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 551system.cpu.dcache.tags.total_refs 4030 # Total number of references to valid blocks. 552system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 553system.cpu.dcache.tags.avg_refs 27.602740 # Average number of references to valid blocks. 554system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 555system.cpu.dcache.tags.occ_blocks::cpu.data 98.068517 # Average occupied blocks per requestor | 555system.cpu.dcache.tags.occ_blocks::cpu.data 98.069813 # Average occupied blocks per requestor |
| 556system.cpu.dcache.tags.occ_percent::cpu.data 0.023943 # Average percentage of cache occupancy 557system.cpu.dcache.tags.occ_percent::total 0.023943 # Average percentage of cache occupancy 558system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 559system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 560system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 561system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 562system.cpu.dcache.tags.tag_accesses 9286 # Number of tag accesses 563system.cpu.dcache.tags.data_accesses 9286 # Number of data accesses --- 94 unchanged lines hidden (view full) --- 658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76909.638554 # average WriteReq mshr miss latency 659system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76909.638554 # average WriteReq mshr miss latency 660system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78384.353741 # average overall mshr miss latency 661system.cpu.dcache.demand_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency 662system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78384.353741 # average overall mshr miss latency 663system.cpu.dcache.overall_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency 664system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 665system.cpu.icache.tags.replacements 0 # number of replacements | 556system.cpu.dcache.tags.occ_percent::cpu.data 0.023943 # Average percentage of cache occupancy 557system.cpu.dcache.tags.occ_percent::total 0.023943 # Average percentage of cache occupancy 558system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 559system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id 560system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 561system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 562system.cpu.dcache.tags.tag_accesses 9286 # Number of tag accesses 563system.cpu.dcache.tags.data_accesses 9286 # Number of data accesses --- 94 unchanged lines hidden (view full) --- 658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76909.638554 # average WriteReq mshr miss latency 659system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76909.638554 # average WriteReq mshr miss latency 660system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78384.353741 # average overall mshr miss latency 661system.cpu.dcache.demand_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency 662system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78384.353741 # average overall mshr miss latency 663system.cpu.dcache.overall_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency 664system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 665system.cpu.icache.tags.replacements 0 # number of replacements |
| 666system.cpu.icache.tags.tagsinuse 190.286110 # Cycle average of tags in use | 666system.cpu.icache.tags.tagsinuse 190.290590 # Cycle average of tags in use |
| 667system.cpu.icache.tags.total_refs 5576 # Total number of references to valid blocks. 668system.cpu.icache.tags.sampled_refs 344 # Sample count of references to valid blocks. 669system.cpu.icache.tags.avg_refs 16.209302 # Average number of references to valid blocks. 670system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 667system.cpu.icache.tags.total_refs 5576 # Total number of references to valid blocks. 668system.cpu.icache.tags.sampled_refs 344 # Sample count of references to valid blocks. 669system.cpu.icache.tags.avg_refs 16.209302 # Average number of references to valid blocks. 670system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 671system.cpu.icache.tags.occ_blocks::cpu.inst 190.286110 # Average occupied blocks per requestor 672system.cpu.icache.tags.occ_percent::cpu.inst 0.092913 # Average percentage of cache occupancy 673system.cpu.icache.tags.occ_percent::total 0.092913 # Average percentage of cache occupancy | 671system.cpu.icache.tags.occ_blocks::cpu.inst 190.290590 # Average occupied blocks per requestor 672system.cpu.icache.tags.occ_percent::cpu.inst 0.092915 # Average percentage of cache occupancy 673system.cpu.icache.tags.occ_percent::total 0.092915 # Average percentage of cache occupancy |
| 674system.cpu.icache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id 677system.cpu.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 678system.cpu.icache.tags.tag_accesses 12534 # Number of tag accesses 679system.cpu.icache.tags.data_accesses 12534 # Number of data accesses 680system.cpu.icache.ReadReq_hits::cpu.inst 5576 # number of ReadReq hits 681system.cpu.icache.ReadReq_hits::total 5576 # number of ReadReq hits 682system.cpu.icache.demand_hits::cpu.inst 5576 # number of demand (read+write) hits 683system.cpu.icache.demand_hits::total 5576 # number of demand (read+write) hits 684system.cpu.icache.overall_hits::cpu.inst 5576 # number of overall hits 685system.cpu.icache.overall_hits::total 5576 # number of overall hits 686system.cpu.icache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses 687system.cpu.icache.ReadReq_misses::total 519 # number of ReadReq misses 688system.cpu.icache.demand_misses::cpu.inst 519 # number of demand (read+write) misses 689system.cpu.icache.demand_misses::total 519 # number of demand (read+write) misses 690system.cpu.icache.overall_misses::cpu.inst 519 # number of overall misses 691system.cpu.icache.overall_misses::total 519 # number of overall misses | 674system.cpu.icache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id 677system.cpu.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id 678system.cpu.icache.tags.tag_accesses 12534 # Number of tag accesses 679system.cpu.icache.tags.data_accesses 12534 # Number of data accesses 680system.cpu.icache.ReadReq_hits::cpu.inst 5576 # number of ReadReq hits 681system.cpu.icache.ReadReq_hits::total 5576 # number of ReadReq hits 682system.cpu.icache.demand_hits::cpu.inst 5576 # number of demand (read+write) hits 683system.cpu.icache.demand_hits::total 5576 # number of demand (read+write) hits 684system.cpu.icache.overall_hits::cpu.inst 5576 # number of overall hits 685system.cpu.icache.overall_hits::total 5576 # number of overall hits 686system.cpu.icache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses 687system.cpu.icache.ReadReq_misses::total 519 # number of ReadReq misses 688system.cpu.icache.demand_misses::cpu.inst 519 # number of demand (read+write) misses 689system.cpu.icache.demand_misses::total 519 # number of demand (read+write) misses 690system.cpu.icache.overall_misses::cpu.inst 519 # number of overall misses 691system.cpu.icache.overall_misses::total 519 # number of overall misses |
| 692system.cpu.icache.ReadReq_miss_latency::cpu.inst 36198500 # number of ReadReq miss cycles 693system.cpu.icache.ReadReq_miss_latency::total 36198500 # number of ReadReq miss cycles 694system.cpu.icache.demand_miss_latency::cpu.inst 36198500 # number of demand (read+write) miss cycles 695system.cpu.icache.demand_miss_latency::total 36198500 # number of demand (read+write) miss cycles 696system.cpu.icache.overall_miss_latency::cpu.inst 36198500 # number of overall miss cycles 697system.cpu.icache.overall_miss_latency::total 36198500 # number of overall miss cycles | 692system.cpu.icache.ReadReq_miss_latency::cpu.inst 36200500 # number of ReadReq miss cycles 693system.cpu.icache.ReadReq_miss_latency::total 36200500 # number of ReadReq miss cycles 694system.cpu.icache.demand_miss_latency::cpu.inst 36200500 # number of demand (read+write) miss cycles 695system.cpu.icache.demand_miss_latency::total 36200500 # number of demand (read+write) miss cycles 696system.cpu.icache.overall_miss_latency::cpu.inst 36200500 # number of overall miss cycles 697system.cpu.icache.overall_miss_latency::total 36200500 # number of overall miss cycles |
| 698system.cpu.icache.ReadReq_accesses::cpu.inst 6095 # number of ReadReq accesses(hits+misses) 699system.cpu.icache.ReadReq_accesses::total 6095 # number of ReadReq accesses(hits+misses) 700system.cpu.icache.demand_accesses::cpu.inst 6095 # number of demand (read+write) accesses 701system.cpu.icache.demand_accesses::total 6095 # number of demand (read+write) accesses 702system.cpu.icache.overall_accesses::cpu.inst 6095 # number of overall (read+write) accesses 703system.cpu.icache.overall_accesses::total 6095 # number of overall (read+write) accesses 704system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085152 # miss rate for ReadReq accesses 705system.cpu.icache.ReadReq_miss_rate::total 0.085152 # miss rate for ReadReq accesses 706system.cpu.icache.demand_miss_rate::cpu.inst 0.085152 # miss rate for demand accesses 707system.cpu.icache.demand_miss_rate::total 0.085152 # miss rate for demand accesses 708system.cpu.icache.overall_miss_rate::cpu.inst 0.085152 # miss rate for overall accesses 709system.cpu.icache.overall_miss_rate::total 0.085152 # miss rate for overall accesses | 698system.cpu.icache.ReadReq_accesses::cpu.inst 6095 # number of ReadReq accesses(hits+misses) 699system.cpu.icache.ReadReq_accesses::total 6095 # number of ReadReq accesses(hits+misses) 700system.cpu.icache.demand_accesses::cpu.inst 6095 # number of demand (read+write) accesses 701system.cpu.icache.demand_accesses::total 6095 # number of demand (read+write) accesses 702system.cpu.icache.overall_accesses::cpu.inst 6095 # number of overall (read+write) accesses 703system.cpu.icache.overall_accesses::total 6095 # number of overall (read+write) accesses 704system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085152 # miss rate for ReadReq accesses 705system.cpu.icache.ReadReq_miss_rate::total 0.085152 # miss rate for ReadReq accesses 706system.cpu.icache.demand_miss_rate::cpu.inst 0.085152 # miss rate for demand accesses 707system.cpu.icache.demand_miss_rate::total 0.085152 # miss rate for demand accesses 708system.cpu.icache.overall_miss_rate::cpu.inst 0.085152 # miss rate for overall accesses 709system.cpu.icache.overall_miss_rate::total 0.085152 # miss rate for overall accesses |
| 710system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69746.628131 # average ReadReq miss latency 711system.cpu.icache.ReadReq_avg_miss_latency::total 69746.628131 # average ReadReq miss latency 712system.cpu.icache.demand_avg_miss_latency::cpu.inst 69746.628131 # average overall miss latency 713system.cpu.icache.demand_avg_miss_latency::total 69746.628131 # average overall miss latency 714system.cpu.icache.overall_avg_miss_latency::cpu.inst 69746.628131 # average overall miss latency 715system.cpu.icache.overall_avg_miss_latency::total 69746.628131 # average overall miss latency | 710system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69750.481696 # average ReadReq miss latency 711system.cpu.icache.ReadReq_avg_miss_latency::total 69750.481696 # average ReadReq miss latency 712system.cpu.icache.demand_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency 713system.cpu.icache.demand_avg_miss_latency::total 69750.481696 # average overall miss latency 714system.cpu.icache.overall_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency 715system.cpu.icache.overall_avg_miss_latency::total 69750.481696 # average overall miss latency |
| 716system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 717system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 718system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 719system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 721system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 722system.cpu.icache.fast_writes 0 # number of fast writes performed 723system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 728system.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits 729system.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits 730system.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses 731system.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses 732system.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 733system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses 734system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 735system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses | 716system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 717system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 718system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 719system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 721system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 722system.cpu.icache.fast_writes 0 # number of fast writes performed 723system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 728system.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits 729system.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits 730system.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses 731system.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses 732system.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 733system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses 734system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 735system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses |
| 736system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26530000 # number of ReadReq MSHR miss cycles 737system.cpu.icache.ReadReq_mshr_miss_latency::total 26530000 # number of ReadReq MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26530000 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.demand_mshr_miss_latency::total 26530000 # number of demand (read+write) MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26530000 # number of overall MSHR miss cycles 741system.cpu.icache.overall_mshr_miss_latency::total 26530000 # number of overall MSHR miss cycles | 736system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26532000 # number of ReadReq MSHR miss cycles 737system.cpu.icache.ReadReq_mshr_miss_latency::total 26532000 # number of ReadReq MSHR miss cycles 738system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26532000 # number of demand (read+write) MSHR miss cycles 739system.cpu.icache.demand_mshr_miss_latency::total 26532000 # number of demand (read+write) MSHR miss cycles 740system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26532000 # number of overall MSHR miss cycles 741system.cpu.icache.overall_mshr_miss_latency::total 26532000 # number of overall MSHR miss cycles |
| 742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for ReadReq accesses 743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.056440 # mshr miss rate for ReadReq accesses 744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for demand accesses 745system.cpu.icache.demand_mshr_miss_rate::total 0.056440 # mshr miss rate for demand accesses 746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for overall accesses 747system.cpu.icache.overall_mshr_miss_rate::total 0.056440 # mshr miss rate for overall accesses | 742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for ReadReq accesses 743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.056440 # mshr miss rate for ReadReq accesses 744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for demand accesses 745system.cpu.icache.demand_mshr_miss_rate::total 0.056440 # mshr miss rate for demand accesses 746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for overall accesses 747system.cpu.icache.overall_mshr_miss_rate::total 0.056440 # mshr miss rate for overall accesses |
| 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77122.093023 # average ReadReq mshr miss latency 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77122.093023 # average ReadReq mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77122.093023 # average overall mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::total 77122.093023 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77122.093023 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::total 77122.093023 # average overall mshr miss latency | 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77127.906977 # average ReadReq mshr miss latency 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77127.906977 # average ReadReq mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency |
| 754system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 755system.cpu.l2cache.tags.replacements 0 # number of replacements | 754system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 755system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 756system.cpu.l2cache.tags.tagsinuse 223.995330 # Cycle average of tags in use | 756system.cpu.l2cache.tags.tagsinuse 224.000415 # Cycle average of tags in use |
| 757system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 758system.cpu.l2cache.tags.sampled_refs 405 # Sample count of references to valid blocks. 759system.cpu.l2cache.tags.avg_refs 0.004938 # Average number of references to valid blocks. 760system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 757system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 758system.cpu.l2cache.tags.sampled_refs 405 # Sample count of references to valid blocks. 759system.cpu.l2cache.tags.avg_refs 0.004938 # Average number of references to valid blocks. 760system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 761system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.659398 # Average occupied blocks per requestor 762system.cpu.l2cache.tags.occ_blocks::cpu.data 34.335932 # Average occupied blocks per requestor | 761system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.663901 # Average occupied blocks per requestor 762system.cpu.l2cache.tags.occ_blocks::cpu.data 34.336514 # Average occupied blocks per requestor |
| 763system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005788 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_percent::cpu.data 0.001048 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_percent::total 0.006836 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id 767system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id 769system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012360 # Percentage of cache occupancy per task id 770system.cpu.l2cache.tags.tag_accesses 4416 # Number of tag accesses --- 116 unchanged lines hidden (view full) --- 887system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68968.750000 # average ReadSharedReq mshr miss latency 888system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66001.461988 # average overall mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency 890system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency 891system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66001.461988 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency 894system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 763system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005788 # Average percentage of cache occupancy 764system.cpu.l2cache.tags.occ_percent::cpu.data 0.001048 # Average percentage of cache occupancy 765system.cpu.l2cache.tags.occ_percent::total 0.006836 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id 767system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 768system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id 769system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012360 # Percentage of cache occupancy per task id 770system.cpu.l2cache.tags.tag_accesses 4416 # Number of tag accesses --- 116 unchanged lines hidden (view full) --- 887system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68968.750000 # average ReadSharedReq mshr miss latency 888system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66001.461988 # average overall mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency 890system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency 891system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66001.461988 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency 894system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 895system.cpu.toL2Bus.snoop_filter.tot_requests 491 # Total number of requests made to the snoop filter. 896system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data. 897system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 898system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 899system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 900system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 895system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution 896system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 897system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 898system.cpu.toL2Bus.trans_dist::ReadCleanReq 344 # Transaction distribution 899system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution 900system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes) 901system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 902system.cpu.toL2Bus.pkt_count::total 981 # Packet count per connected master and slave (bytes) 903system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes) 904system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 905system.cpu.toL2Bus.pkt_size::total 31360 # Cumulative packet size per connected master and slave (bytes) 906system.cpu.toL2Bus.snoops 0 # Total snoops (count) 907system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram | 901system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution 902system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 903system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 904system.cpu.toL2Bus.trans_dist::ReadCleanReq 344 # Transaction distribution 905system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution 906system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes) 907system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 908system.cpu.toL2Bus.pkt_count::total 981 # Packet count per connected master and slave (bytes) 909system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes) 910system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 911system.cpu.toL2Bus.pkt_size::total 31360 # Cumulative packet size per connected master and slave (bytes) 912system.cpu.toL2Bus.snoops 0 # Total snoops (count) 913system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram |
| 908system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 914system.cpu.toL2Bus.snoop_fanout::mean 0.004073 # Request fanout histogram 915system.cpu.toL2Bus.snoop_fanout::stdev 0.063757 # Request fanout histogram |
| 910system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 916system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 911system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 912system.cpu.toL2Bus.snoop_fanout::1 491 100.00% 100.00% # Request fanout histogram | 917system.cpu.toL2Bus.snoop_fanout::0 489 99.59% 99.59% # Request fanout histogram 918system.cpu.toL2Bus.snoop_fanout::1 2 0.41% 100.00% # Request fanout histogram |
| 913system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 914system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 919system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 920system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 915system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 921system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 916system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 917system.cpu.toL2Bus.snoop_fanout::total 491 # Request fanout histogram 918system.cpu.toL2Bus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) 919system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 920system.cpu.toL2Bus.respLayer0.occupancy 516000 # Layer occupancy (ticks) 921system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 922system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) 923system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) --- 25 unchanged lines hidden --- | 922system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 923system.cpu.toL2Bus.snoop_fanout::total 491 # Request fanout histogram 924system.cpu.toL2Bus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) 925system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 926system.cpu.toL2Bus.respLayer0.occupancy 516000 # Layer occupancy (ticks) 927system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 928system.cpu.toL2Bus.respLayer1.occupancy 219000 # Layer occupancy (ticks) 929system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) --- 25 unchanged lines hidden --- |