| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated 4sim_ticks 27482500 # Number of ticks simulated 5final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 86365 # Simulator instruction rate (inst/s) 8host_op_rate 86358 # Simulator op (including micro ops) rate (op/s) --- 519 unchanged lines hidden (view full) --- 528system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction 530system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction 531system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 532system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 534system.cpu.commit.op_class_0::total 15162 # Class of committed instruction 535system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated 4sim_ticks 27482500 # Number of ticks simulated 5final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 86365 # Simulator instruction rate (inst/s) 8host_op_rate 86358 # Simulator op (including micro ops) rate (op/s) --- 519 unchanged lines hidden (view full) --- 528system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction 530system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction 531system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 532system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 534system.cpu.commit.op_class_0::total 15162 # Class of committed instruction 535system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached |
| 536system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 537system.cpu.rob.rob_reads 54715 # The number of ROB reads 538system.cpu.rob.rob_writes 52974 # The number of ROB writes 539system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself 540system.cpu.idleCycles 22544 # Total number of cycles that the CPU has spent unscheduled due to idling 541system.cpu.committedInsts 14436 # Number of Instructions Simulated 542system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 543system.cpu.cpi 3.807564 # CPI: Cycles Per Instruction 544system.cpu.cpi_total 3.807564 # CPI: Total CPI of All Threads --- 396 unchanged lines hidden --- | 536system.cpu.rob.rob_reads 54715 # The number of ROB reads 537system.cpu.rob.rob_writes 52974 # The number of ROB writes 538system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself 539system.cpu.idleCycles 22544 # Total number of cycles that the CPU has spent unscheduled due to idling 540system.cpu.committedInsts 14436 # Number of Instructions Simulated 541system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 542system.cpu.cpi 3.807564 # CPI: Cycles Per Instruction 543system.cpu.cpi_total 3.807564 # CPI: Total CPI of All Threads --- 396 unchanged lines hidden --- |