| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25944000 # Number of ticks simulated 5final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000027 # Number of seconds simulated 4sim_ticks 27482500 # Number of ticks simulated 5final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 95549 # Simulator instruction rate (inst/s) 8host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 171686089 # Simulator tick rate (ticks/s) 10host_mem_usage 292480 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host | 7host_inst_rate 86365 # Simulator instruction rate (inst/s) 8host_op_rate 86358 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 164391633 # Simulator tick rate (ticks/s) 10host_mem_usage 291648 # Number of bytes of host memory used 11host_seconds 0.17 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31488 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 22016 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 492 # Number of read requests responded to by this memory | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31488 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 22016 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 492 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 848596978 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 365094049 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1213691027 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 848596978 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 848596978 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 848596978 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 365094049 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1213691027 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 801091604 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 344655690 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1145747294 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 801091604 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 801091604 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 801091604 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 344655690 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1145747294 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 492 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 31488 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 31488 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 492 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 31488 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 31488 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 25892500 # Total gap between requests | 78system.physmem.totGap 27431000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 492 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 492 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 96system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 77 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 72 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 404.444444 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 264.526762 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 350.678412 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 12 16.67% 16.67% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 24 33.33% 50.00% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 7 9.72% 59.72% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.56% 65.28% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 5.56% 70.83% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 4.17% 75.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation 203system.physmem.totQLat 2786000 # Total ticks spent queuing 204system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 404.732394 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 270.110571 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 339.824701 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 13 18.31% 18.31% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 18 25.35% 43.66% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 9 12.68% 56.34% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 7 9.86% 66.20% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 7 9.86% 76.06% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 1.41% 77.46% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 4 5.63% 83.10% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 2.82% 85.92% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 10 14.08% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation 203system.physmem.totQLat 3613750 # Total ticks spent queuing 204system.physmem.totMemAccLat 12838750 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 7345.02 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 26095.02 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1145.75 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1145.75 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.physmem.busUtil 9.48 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.48 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 8.95 # Data bus utilization in percentage 215system.physmem.busUtilRead 8.95 # Data bus utilization in percentage for reads |
| 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 411 # Number of row buffer hits during reads | 219system.physmem.readRowHits 412 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads | 221system.physmem.readRowHitRate 83.74 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 52627.03 # Average gap between requests 224system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) | 223system.physmem.avgGap 55754.07 # Average gap between requests 224system.physmem.pageHitRate 83.74 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2059200 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) |
| 230system.physmem_0.actBackEnergy 16044930 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 96750 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 20252445 # Total energy per rank (pJ) 233system.physmem_0.averagePower 857.473194 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 279250 # Time in different power states | 230system.physmem_0.actBackEnergy 15743115 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 361500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 20156895 # Total energy per rank (pJ) 233system.physmem_0.averagePower 853.427679 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 520250 # Time in different power states |
| 235system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 235system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 22761250 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 22332250 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) |
| 244system.physmem_1.actBackEnergy 14873580 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 1124250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 19192260 # Total energy per rank (pJ) 247system.physmem_1.averagePower 812.585763 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 2246250 # Time in different power states | 244system.physmem_1.actBackEnergy 15564420 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 518250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 19277100 # Total energy per rank (pJ) 247system.physmem_1.averagePower 816.177825 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 2637000 # Time in different power states |
| 249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 21062250 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 22058500 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.cpu.branchPred.lookups 8578 # Number of BP lookups 254system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 3046 # Number of BTB hits | 253system.cpu.branchPred.lookups 8538 # Number of BP lookups 254system.cpu.branchPred.condPredicted 5461 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1059 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 5976 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 3053 # Number of BTB hits |
| 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 259system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target. | 259system.cpu.branchPred.BTBHitPct 51.087684 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 609 # Number of times the RAS was used to get a target. |
| 261system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.workload.num_syscalls 18 # Number of system calls | 261system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.workload.num_syscalls 18 # Number of system calls |
| 264system.cpu.numCycles 51889 # number of cpu cycles simulated | 264system.cpu.numCycles 54966 # number of cpu cycles simulated |
| 265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 267system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss 268system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed 269system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered 270system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken 271system.cpu.fetch.Cycles 16187 # Number of cycles fetch has run and was not squashing or blocked | 267system.cpu.fetch.icacheStallCycles 14246 # Number of cycles fetch is stalled on an Icache miss 268system.cpu.fetch.Insts 40057 # Number of instructions fetch has processed 269system.cpu.fetch.Branches 8538 # Number of branches that fetch encountered 270system.cpu.fetch.predictedBranches 3662 # Number of branches that fetch has predicted taken 271system.cpu.fetch.Cycles 15957 # Number of cycles fetch has run and was not squashing or blocked |
| 272system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing 273system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 272system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing 273system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 274system.cpu.fetch.PendingTrapStallCycles 1000 # Number of stall cycles due to pending traps | 274system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps |
| 275system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR | 275system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR |
| 276system.cpu.fetch.CacheLines 6453 # Number of cache lines fetched 277system.cpu.fetch.IcacheSquashes 567 # Number of outstanding Icache misses that were squashed 278system.cpu.fetch.rateDist::samples 32510 # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::mean 1.239619 # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::stdev 2.385650 # Number of instructions fetched each cycle (Total) | 276system.cpu.fetch.CacheLines 6438 # Number of cache lines fetched 277system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed 278system.cpu.fetch.rateDist::samples 32422 # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::mean 1.235488 # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::stdev 2.378208 # Number of instructions fetched each cycle (Total) |
| 281system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 281system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 282system.cpu.fetch.rateDist::0 20972 64.51% 64.51% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::1 5490 16.89% 81.40% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::2 661 2.03% 83.43% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::3 508 1.56% 84.99% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::4 826 2.54% 87.53% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::5 909 2.80% 90.33% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::6 334 1.03% 91.36% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::7 369 1.14% 92.49% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::8 2441 7.51% 100.00% # Number of instructions fetched each cycle (Total) | 282system.cpu.fetch.rateDist::0 20898 64.46% 64.46% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::1 5494 16.95% 81.40% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::2 685 2.11% 83.51% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::3 505 1.56% 85.07% # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::4 819 2.53% 87.60% # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.rateDist::5 909 2.80% 90.40% # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::6 334 1.03% 91.43% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::7 371 1.14% 92.58% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::8 2407 7.42% 100.00% # Number of instructions fetched each cycle (Total) |
| 291system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 291system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 294system.cpu.fetch.rateDist::total 32510 # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.branchRate 0.165314 # Number of branch fetches per cycle 296system.cpu.fetch.rate 0.776658 # Number of inst fetches per cycle 297system.cpu.decode.IdleCycles 11331 # Number of cycles decode is idle 298system.cpu.decode.BlockedCycles 12526 # Number of cycles decode is blocked 299system.cpu.decode.RunCycles 6844 # Number of cycles decode is running 300system.cpu.decode.UnblockCycles 654 # Number of cycles decode is unblocking | 294system.cpu.fetch.rateDist::total 32422 # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.branchRate 0.155332 # Number of branch fetches per cycle 296system.cpu.fetch.rate 0.728760 # Number of inst fetches per cycle 297system.cpu.decode.IdleCycles 11347 # Number of cycles decode is idle 298system.cpu.decode.BlockedCycles 12433 # Number of cycles decode is blocked 299system.cpu.decode.RunCycles 6847 # Number of cycles decode is running 300system.cpu.decode.UnblockCycles 640 # Number of cycles decode is unblocking |
| 301system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing | 301system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing |
| 302system.cpu.decode.DecodedInsts 30561 # Number of instructions handled by decode | 302system.cpu.decode.DecodedInsts 30502 # Number of instructions handled by decode |
| 303system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing | 303system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing |
| 304system.cpu.rename.IdleCycles 11931 # Number of cycles rename is idle 305system.cpu.rename.BlockCycles 1436 # Number of cycles rename is blocking 306system.cpu.rename.serializeStallCycles 10087 # count of cycles rename stalled for serializing inst 307system.cpu.rename.RunCycles 6918 # Number of cycles rename is running 308system.cpu.rename.UnblockCycles 983 # Number of cycles rename is unblocking 309system.cpu.rename.RenamedInsts 27740 # Number of instructions processed by rename 310system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 311system.cpu.rename.SQFullEvents 585 # Number of times rename has blocked due to SQ full 312system.cpu.rename.RenamedOperands 25096 # Number of destination operands rename has renamed 313system.cpu.rename.RenameLookups 51799 # Number of register rename lookups that rename has made 314system.cpu.rename.int_rename_lookups 42923 # Number of integer rename lookups | 304system.cpu.rename.IdleCycles 11955 # Number of cycles rename is idle 305system.cpu.rename.BlockCycles 1146 # Number of cycles rename is blocking 306system.cpu.rename.serializeStallCycles 9859 # count of cycles rename stalled for serializing inst 307system.cpu.rename.RunCycles 6898 # Number of cycles rename is running 308system.cpu.rename.UnblockCycles 1409 # Number of cycles rename is unblocking 309system.cpu.rename.RenamedInsts 27684 # Number of instructions processed by rename 310system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 311system.cpu.rename.SQFullEvents 1012 # Number of times rename has blocked due to SQ full 312system.cpu.rename.RenamedOperands 25054 # Number of destination operands rename has renamed 313system.cpu.rename.RenameLookups 51692 # Number of register rename lookups that rename has made 314system.cpu.rename.int_rename_lookups 42838 # Number of integer rename lookups |
| 315system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed | 315system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed |
| 316system.cpu.rename.UndoneMaps 11277 # Number of HB maps that are undone due to squashing 317system.cpu.rename.serializingInsts 768 # count of serializing insts renamed | 316system.cpu.rename.UndoneMaps 11235 # Number of HB maps that are undone due to squashing 317system.cpu.rename.serializingInsts 767 # count of serializing insts renamed |
| 318system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed | 318system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed |
| 319system.cpu.rename.skidInsts 3783 # count of insts added to the skid buffer 320system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit. | 319system.cpu.rename.skidInsts 3842 # count of insts added to the skid buffer 320system.cpu.memDep0.insertedLoads 3673 # Number of loads inserted to the mem dependence unit. |
| 321system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit. 322system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. 323system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 321system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit. 322system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. 323system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 324system.cpu.iq.iqInstsAdded 23657 # Number of instructions added to the IQ (excludes non-spec) | 324system.cpu.iq.iqInstsAdded 23655 # Number of instructions added to the IQ (excludes non-spec) |
| 325system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ | 325system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ |
| 326system.cpu.iq.iqInstsIssued 21921 # Number of instructions issued 327system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued 328system.cpu.iq.iqSquashedInstsExamined 9156 # Number of squashed instructions iterated over during squash; mainly for profiling 329system.cpu.iq.iqSquashedOperandsExamined 6522 # Number of squashed operands that are examined and possibly removed from graph | 326system.cpu.iq.iqInstsIssued 21924 # Number of instructions issued 327system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued 328system.cpu.iq.iqSquashedInstsExamined 9151 # Number of squashed instructions iterated over during squash; mainly for profiling 329system.cpu.iq.iqSquashedOperandsExamined 6501 # Number of squashed operands that are examined and possibly removed from graph |
| 330system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed | 330system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed |
| 331system.cpu.iq.issued_per_cycle::samples 32510 # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::mean 0.674285 # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::stdev 1.426342 # Number of insts issued each cycle | 331system.cpu.iq.issued_per_cycle::samples 32422 # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::mean 0.676208 # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::stdev 1.425800 # Number of insts issued each cycle |
| 334system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 334system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 335system.cpu.iq.issued_per_cycle::0 24124 74.20% 74.20% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::1 3065 9.43% 83.63% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::2 1561 4.80% 88.43% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::3 1482 4.56% 92.99% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::4 945 2.91% 95.90% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::5 726 2.23% 98.13% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::6 412 1.27% 99.40% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::7 154 0.47% 99.87% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::8 41 0.13% 100.00% # Number of insts issued each cycle | 335system.cpu.iq.issued_per_cycle::0 24009 74.05% 74.05% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::1 3087 9.52% 83.57% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::2 1572 4.85% 88.42% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::3 1483 4.57% 93.00% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::4 954 2.94% 95.94% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::5 709 2.19% 98.12% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::6 413 1.27% 99.40% # Number of insts issued each cycle 342system.cpu.iq.issued_per_cycle::7 155 0.48% 99.88% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::8 40 0.12% 100.00% # Number of insts issued each cycle |
| 344system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 344system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 347system.cpu.iq.issued_per_cycle::total 32510 # Number of insts issued each cycle | 347system.cpu.iq.issued_per_cycle::total 32422 # Number of insts issued each cycle |
| 348system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 348system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 349system.cpu.iq.fu_full::IntAlu 112 49.56% 49.56% # attempts to use FU when none available 350system.cpu.iq.fu_full::IntMult 0 0.00% 49.56% # attempts to use FU when none available 351system.cpu.iq.fu_full::IntDiv 0 0.00% 49.56% # attempts to use FU when none available 352system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.56% # attempts to use FU when none available 353system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.56% # attempts to use FU when none available 354system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.56% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatMult 0 0.00% 49.56% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.56% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.56% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.56% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.56% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.56% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.56% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.56% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.56% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdMult 0 0.00% 49.56% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.56% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdShift 0 0.00% 49.56% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.56% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.56% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.56% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.56% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.56% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.56% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.56% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.56% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.56% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.56% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.56% # attempts to use FU when none available 378system.cpu.iq.fu_full::MemRead 49 21.68% 71.24% # attempts to use FU when none available 379system.cpu.iq.fu_full::MemWrite 65 28.76% 100.00% # attempts to use FU when none available | 349system.cpu.iq.fu_full::IntAlu 111 49.33% 49.33% # attempts to use FU when none available 350system.cpu.iq.fu_full::IntMult 0 0.00% 49.33% # attempts to use FU when none available 351system.cpu.iq.fu_full::IntDiv 0 0.00% 49.33% # attempts to use FU when none available 352system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.33% # attempts to use FU when none available 353system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.33% # attempts to use FU when none available 354system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.33% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatMult 0 0.00% 49.33% # attempts to use FU when none available 356system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.33% # attempts to use FU when none available 357system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.33% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.33% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.33% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.33% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.33% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.33% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.33% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdMult 0 0.00% 49.33% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.33% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdShift 0 0.00% 49.33% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.33% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.33% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.33% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.33% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.33% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.33% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.33% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.33% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.33% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.33% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.33% # attempts to use FU when none available 378system.cpu.iq.fu_full::MemRead 49 21.78% 71.11% # attempts to use FU when none available 379system.cpu.iq.fu_full::MemWrite 65 28.89% 100.00% # attempts to use FU when none available |
| 380system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 381system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 382system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 380system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 381system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 382system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 383system.cpu.iq.FU_type_0::IntAlu 16292 74.32% 74.32% # Type of FU issued 384system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued 385system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued 386system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued 387system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued 388system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued 412system.cpu.iq.FU_type_0::MemRead 3506 15.99% 90.32% # Type of FU issued | 383system.cpu.iq.FU_type_0::IntAlu 16300 74.35% 74.35% # Type of FU issued 384system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.35% # Type of FU issued 385system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.35% # Type of FU issued 386system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.35% # Type of FU issued 387system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.35% # Type of FU issued 388system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.35% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.35% # Type of FU issued 390system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.35% # Type of FU issued 391system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.35% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.35% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.35% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.35% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.35% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.35% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.35% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.35% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.35% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.35% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.35% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.35% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.35% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.35% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.35% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.35% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.35% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.35% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.35% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.35% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.35% # Type of FU issued 412system.cpu.iq.FU_type_0::MemRead 3501 15.97% 90.32% # Type of FU issued |
| 413system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued 414system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 415system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 413system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued 414system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 415system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 416system.cpu.iq.FU_type_0::total 21921 # Type of FU issued 417system.cpu.iq.rate 0.422459 # Inst issue rate 418system.cpu.iq.fu_busy_cnt 226 # FU busy when requested 419system.cpu.iq.fu_busy_rate 0.010310 # FU busy rate (busy events/executed inst) 420system.cpu.iq.int_inst_queue_reads 76635 # Number of integer instruction queue reads 421system.cpu.iq.int_inst_queue_writes 33566 # Number of integer instruction queue writes 422system.cpu.iq.int_inst_queue_wakeup_accesses 20237 # Number of integer instruction queue wakeup accesses | 416system.cpu.iq.FU_type_0::total 21924 # Type of FU issued 417system.cpu.iq.rate 0.398865 # Inst issue rate 418system.cpu.iq.fu_busy_cnt 225 # FU busy when requested 419system.cpu.iq.fu_busy_rate 0.010263 # FU busy rate (busy events/executed inst) 420system.cpu.iq.int_inst_queue_reads 76549 # Number of integer instruction queue reads 421system.cpu.iq.int_inst_queue_writes 33558 # Number of integer instruction queue writes 422system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses |
| 423system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 424system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 425system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 423system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 424system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 425system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 426system.cpu.iq.int_alu_accesses 22147 # Number of integer alu accesses | 426system.cpu.iq.int_alu_accesses 22149 # Number of integer alu accesses |
| 427system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 428system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores 429system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 427system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 428system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores 429system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 430system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed | 430system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed |
| 431system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed | 431system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed |
| 432system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations | 432system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations |
| 433system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed 434system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 435system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 433system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed 434system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 435system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 436system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 437system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked | 436system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 437system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked |
| 438system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 439system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing | 438system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 439system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing |
| 440system.cpu.iew.iewBlockCycles 1122 # Number of cycles IEW is blocking 441system.cpu.iew.iewUnblockCycles 322 # Number of cycles IEW is unblocking 442system.cpu.iew.iewDispatchedInsts 25510 # Number of instructions dispatched to IQ 443system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch 444system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions | 440system.cpu.iew.iewBlockCycles 1147 # Number of cycles IEW is blocking 441system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking 442system.cpu.iew.iewDispatchedInsts 25507 # Number of instructions dispatched to IQ 443system.cpu.iew.iewDispSquashedInsts 203 # Number of squashed instructions skipped by dispatch 444system.cpu.iew.iewDispLoadInsts 3673 # Number of dispatched load instructions |
| 445system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions 446system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions 447system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall | 445system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions 446system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions 447system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall |
| 448system.cpu.iew.iewLSQFullEvents 318 # Number of times the LSQ has become full, causing a stall 449system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations | 448system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall 449system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations |
| 450system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly | 450system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly |
| 451system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly 452system.cpu.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute 453system.cpu.iew.iewExecutedInsts 20909 # Number of executed instructions 454system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed 455system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute | 451system.cpu.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly 452system.cpu.iew.branchMispredicts 1194 # Number of branch mispredicts detected at execute 453system.cpu.iew.iewExecutedInsts 20914 # Number of executed instructions 454system.cpu.iew.iewExecLoadInsts 3347 # Number of load instructions executed 455system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute |
| 456system.cpu.iew.exec_swp 0 # number of swp insts executed | 456system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 457system.cpu.iew.exec_nop 1127 # number of nop insts executed 458system.cpu.iew.exec_refs 5373 # number of memory reference insts executed 459system.cpu.iew.exec_branches 4425 # Number of branches executed | 457system.cpu.iew.exec_nop 1126 # number of nop insts executed 458system.cpu.iew.exec_refs 5371 # number of memory reference insts executed 459system.cpu.iew.exec_branches 4427 # Number of branches executed |
| 460system.cpu.iew.exec_stores 2024 # Number of stores executed | 460system.cpu.iew.exec_stores 2024 # Number of stores executed |
| 461system.cpu.iew.exec_rate 0.402956 # Inst execution rate 462system.cpu.iew.wb_sent 20494 # cumulative count of insts sent to commit 463system.cpu.iew.wb_count 20237 # cumulative count of insts written-back 464system.cpu.iew.wb_producers 9846 # num instructions producing a value 465system.cpu.iew.wb_consumers 12767 # num instructions consuming a value | 461system.cpu.iew.exec_rate 0.380490 # Inst execution rate 462system.cpu.iew.wb_sent 20501 # cumulative count of insts sent to commit 463system.cpu.iew.wb_count 20244 # cumulative count of insts written-back 464system.cpu.iew.wb_producers 9848 # num instructions producing a value 465system.cpu.iew.wb_consumers 12670 # num instructions consuming a value |
| 466system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 466system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 467system.cpu.iew.wb_rate 0.390006 # insts written-back per cycle 468system.cpu.iew.wb_fanout 0.771207 # average fanout of values written-back | 467system.cpu.iew.wb_rate 0.368300 # insts written-back per cycle 468system.cpu.iew.wb_fanout 0.777269 # average fanout of values written-back |
| 469system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 469system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 470system.cpu.commit.commitSquashedInsts 10297 # The number of squashed insts skipped by commit | 470system.cpu.commit.commitSquashedInsts 10287 # The number of squashed insts skipped by commit |
| 471system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards | 471system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards |
| 472system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted 473system.cpu.commit.committed_per_cycle::samples 30446 # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::mean 0.497996 # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::stdev 1.310786 # Number of insts commited each cycle | 472system.cpu.commit.branchMispredicts 1059 # The number of times a branch was mispredicted 473system.cpu.commit.committed_per_cycle::samples 30361 # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::mean 0.499391 # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::stdev 1.308685 # Number of insts commited each cycle |
| 476system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 476system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 477system.cpu.commit.committed_per_cycle::0 23926 78.59% 78.59% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::1 3430 11.27% 89.85% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::2 1163 3.82% 93.67% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::3 612 2.01% 95.68% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::4 344 1.13% 96.81% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::5 240 0.79% 97.60% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::6 396 1.30% 98.90% # Number of insts commited each cycle | 477system.cpu.commit.committed_per_cycle::0 23816 78.44% 78.44% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::1 3429 11.29% 89.74% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::2 1193 3.93% 93.67% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::3 637 2.10% 95.76% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::4 331 1.09% 96.85% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::5 224 0.74% 97.59% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::6 397 1.31% 98.90% # Number of insts commited each cycle |
| 484system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle | 484system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle |
| 485system.cpu.commit.committed_per_cycle::8 273 0.90% 100.00% # Number of insts commited each cycle | 485system.cpu.commit.committed_per_cycle::8 272 0.90% 100.00% # Number of insts commited each cycle |
| 486system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 486system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 487system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 489system.cpu.commit.committed_per_cycle::total 30446 # Number of insts commited each cycle | 489system.cpu.commit.committed_per_cycle::total 30361 # Number of insts commited each cycle |
| 490system.cpu.commit.committedInsts 15162 # Number of instructions committed 491system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 492system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 493system.cpu.commit.refs 3673 # Number of memory references committed 494system.cpu.commit.loads 2225 # Number of loads committed 495system.cpu.commit.membars 0 # Number of memory barriers committed 496system.cpu.commit.branches 3358 # Number of branches committed 497system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 527system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction 530system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction 531system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 532system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 534system.cpu.commit.op_class_0::total 15162 # Class of committed instruction | 490system.cpu.commit.committedInsts 15162 # Number of instructions committed 491system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 492system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 493system.cpu.commit.refs 3673 # Number of memory references committed 494system.cpu.commit.loads 2225 # Number of loads committed 495system.cpu.commit.membars 0 # Number of memory barriers committed 496system.cpu.commit.branches 3358 # Number of branches committed 497system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 527system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction 530system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction 531system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 532system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 533system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 534system.cpu.commit.op_class_0::total 15162 # Class of committed instruction |
| 535system.cpu.commit.bw_lim_events 273 # number cycles where commit BW limit reached | 535system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached |
| 536system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 536system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 537system.cpu.rob.rob_reads 54809 # The number of ROB reads 538system.cpu.rob.rob_writes 52997 # The number of ROB writes 539system.cpu.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself 540system.cpu.idleCycles 19379 # Total number of cycles that the CPU has spent unscheduled due to idling | 537system.cpu.rob.rob_reads 54715 # The number of ROB reads 538system.cpu.rob.rob_writes 52974 # The number of ROB writes 539system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself 540system.cpu.idleCycles 22544 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 541system.cpu.committedInsts 14436 # Number of Instructions Simulated 542system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated | 541system.cpu.committedInsts 14436 # Number of Instructions Simulated 542system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated |
| 543system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction 544system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads 545system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle 546system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads 547system.cpu.int_regfile_reads 33401 # number of integer regfile reads 548system.cpu.int_regfile_writes 18599 # number of integer regfile writes 549system.cpu.misc_regfile_reads 7136 # number of misc regfile reads | 543system.cpu.cpi 3.807564 # CPI: Cycles Per Instruction 544system.cpu.cpi_total 3.807564 # CPI: Total CPI of All Threads 545system.cpu.ipc 0.262635 # IPC: Instructions Per Cycle 546system.cpu.ipc_total 0.262635 # IPC: Total IPC of All Threads 547system.cpu.int_regfile_reads 33408 # number of integer regfile reads 548system.cpu.int_regfile_writes 18606 # number of integer regfile writes 549system.cpu.misc_regfile_reads 7133 # number of misc regfile reads |
| 550system.cpu.misc_regfile_writes 569 # number of misc regfile writes 551system.cpu.dcache.tags.replacements 0 # number of replacements | 550system.cpu.misc_regfile_writes 569 # number of misc regfile writes 551system.cpu.dcache.tags.replacements 0 # number of replacements |
| 552system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use 553system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. | 552system.cpu.dcache.tags.tagsinuse 98.556611 # Cycle average of tags in use 553system.cpu.dcache.tags.total_refs 4125 # Total number of references to valid blocks. |
| 554system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. | 554system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. |
| 555system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. | 555system.cpu.dcache.tags.avg_refs 28.061224 # Average number of references to valid blocks. |
| 556system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 556system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 557system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor 558system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy 559system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy | 557system.cpu.dcache.tags.occ_blocks::cpu.data 98.556611 # Average occupied blocks per requestor 558system.cpu.dcache.tags.occ_percent::cpu.data 0.024062 # Average percentage of cache occupancy 559system.cpu.dcache.tags.occ_percent::total 0.024062 # Average percentage of cache occupancy |
| 560system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 561system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 562system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 563system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id | 560system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 561system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 562system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 563system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id |
| 564system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses 565system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses 566system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits 567system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits | 564system.cpu.dcache.tags.tag_accesses 9489 # Number of tag accesses 565system.cpu.dcache.tags.data_accesses 9489 # Number of data accesses 566system.cpu.dcache.ReadReq_hits::cpu.data 3086 # number of ReadReq hits 567system.cpu.dcache.ReadReq_hits::total 3086 # number of ReadReq hits |
| 568system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 569system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 570system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 571system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits | 568system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 569system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 570system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 571system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits |
| 572system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits 573system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits 574system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits 575system.cpu.dcache.overall_hits::total 4118 # number of overall hits 576system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses 577system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses | 572system.cpu.dcache.demand_hits::cpu.data 4119 # number of demand (read+write) hits 573system.cpu.dcache.demand_hits::total 4119 # number of demand (read+write) hits 574system.cpu.dcache.overall_hits::cpu.data 4119 # number of overall hits 575system.cpu.dcache.overall_hits::total 4119 # number of overall hits 576system.cpu.dcache.ReadReq_misses::cpu.data 137 # number of ReadReq misses 577system.cpu.dcache.ReadReq_misses::total 137 # number of ReadReq misses |
| 578system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 579system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses | 578system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 579system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses |
| 580system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses 581system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses 582system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses 583system.cpu.dcache.overall_misses::total 548 # number of overall misses 584system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles 585system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles 586system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles 587system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles 588system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles 589system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles 590system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles 591system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles 592system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) 593system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) | 580system.cpu.dcache.demand_misses::cpu.data 546 # number of demand (read+write) misses 581system.cpu.dcache.demand_misses::total 546 # number of demand (read+write) misses 582system.cpu.dcache.overall_misses::cpu.data 546 # number of overall misses 583system.cpu.dcache.overall_misses::total 546 # number of overall misses 584system.cpu.dcache.ReadReq_miss_latency::cpu.data 9397000 # number of ReadReq miss cycles 585system.cpu.dcache.ReadReq_miss_latency::total 9397000 # number of ReadReq miss cycles 586system.cpu.dcache.WriteReq_miss_latency::cpu.data 27538481 # number of WriteReq miss cycles 587system.cpu.dcache.WriteReq_miss_latency::total 27538481 # number of WriteReq miss cycles 588system.cpu.dcache.demand_miss_latency::cpu.data 36935481 # number of demand (read+write) miss cycles 589system.cpu.dcache.demand_miss_latency::total 36935481 # number of demand (read+write) miss cycles 590system.cpu.dcache.overall_miss_latency::cpu.data 36935481 # number of overall miss cycles 591system.cpu.dcache.overall_miss_latency::total 36935481 # number of overall miss cycles 592system.cpu.dcache.ReadReq_accesses::cpu.data 3223 # number of ReadReq accesses(hits+misses) 593system.cpu.dcache.ReadReq_accesses::total 3223 # number of ReadReq accesses(hits+misses) |
| 594system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 595system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 596system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 597system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) | 594system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 595system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 596system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 597system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) |
| 598system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses 599system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses 600system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses 601system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses 602system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses 603system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses | 598system.cpu.dcache.demand_accesses::cpu.data 4665 # number of demand (read+write) accesses 599system.cpu.dcache.demand_accesses::total 4665 # number of demand (read+write) accesses 600system.cpu.dcache.overall_accesses::cpu.data 4665 # number of overall (read+write) accesses 601system.cpu.dcache.overall_accesses::total 4665 # number of overall (read+write) accesses 602system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042507 # miss rate for ReadReq accesses 603system.cpu.dcache.ReadReq_miss_rate::total 0.042507 # miss rate for ReadReq accesses |
| 604system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 605system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses | 604system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 605system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses |
| 606system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses 607system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses 608system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses 609system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses 610system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency 611system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency 612system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency 613system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency 614system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency 615system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency 616system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency 617system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency 618system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked | 606system.cpu.dcache.demand_miss_rate::cpu.data 0.117042 # miss rate for demand accesses 607system.cpu.dcache.demand_miss_rate::total 0.117042 # miss rate for demand accesses 608system.cpu.dcache.overall_miss_rate::cpu.data 0.117042 # miss rate for overall accesses 609system.cpu.dcache.overall_miss_rate::total 0.117042 # miss rate for overall accesses 610system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68591.240876 # average ReadReq miss latency 611system.cpu.dcache.ReadReq_avg_miss_latency::total 68591.240876 # average ReadReq miss latency 612system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67331.249389 # average WriteReq miss latency 613system.cpu.dcache.WriteReq_avg_miss_latency::total 67331.249389 # average WriteReq miss latency 614system.cpu.dcache.demand_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency 615system.cpu.dcache.demand_avg_miss_latency::total 67647.401099 # average overall miss latency 616system.cpu.dcache.overall_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency 617system.cpu.dcache.overall_avg_miss_latency::total 67647.401099 # average overall miss latency 618system.cpu.dcache.blocked_cycles::no_mshrs 1052 # number of cycles access was blocked |
| 619system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 619system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 620system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked | 620system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked |
| 621system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 621system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 622system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked | 622system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.818182 # average number of cycles each access was blocked |
| 623system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 624system.cpu.dcache.fast_writes 0 # number of fast writes performed 625system.cpu.dcache.cache_copies 0 # number of cache copies performed | 623system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 624system.cpu.dcache.fast_writes 0 # number of fast writes performed 625system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 626system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits 627system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits | 626system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits 627system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits |
| 628system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 629system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits | 628system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 629system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits |
| 630system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits 631system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits 632system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits 633system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits | 630system.cpu.dcache.demand_mshr_hits::cpu.data 398 # number of demand (read+write) MSHR hits 631system.cpu.dcache.demand_mshr_hits::total 398 # number of demand (read+write) MSHR hits 632system.cpu.dcache.overall_mshr_hits::cpu.data 398 # number of overall MSHR hits 633system.cpu.dcache.overall_mshr_hits::total 398 # number of overall MSHR hits |
| 634system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 635system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 636system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 637system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 638system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 639system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 640system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 641system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses | 634system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 635system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 636system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 637system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 638system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 639system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 640system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 641system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses |
| 642system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles 643system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles 644system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles 645system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles 646system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles 647system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles 648system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles 649system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles 650system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses | 642system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5143250 # number of ReadReq MSHR miss cycles 643system.cpu.dcache.ReadReq_mshr_miss_latency::total 5143250 # number of ReadReq MSHR miss cycles 644system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6389250 # number of WriteReq MSHR miss cycles 645system.cpu.dcache.WriteReq_mshr_miss_latency::total 6389250 # number of WriteReq MSHR miss cycles 646system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11532500 # number of demand (read+write) MSHR miss cycles 647system.cpu.dcache.demand_mshr_miss_latency::total 11532500 # number of demand (read+write) MSHR miss cycles 648system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11532500 # number of overall MSHR miss cycles 649system.cpu.dcache.overall_mshr_miss_latency::total 11532500 # number of overall MSHR miss cycles 650system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020168 # mshr miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020168 # mshr miss rate for ReadReq accesses |
| 652system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses | 652system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses |
| 654system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses 655system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses 656system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses 657system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses 658system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency 659system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency 661system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency 663system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency 665system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency | 654system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for demand accesses 655system.cpu.dcache.demand_mshr_miss_rate::total 0.031726 # mshr miss rate for demand accesses 656system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for overall accesses 657system.cpu.dcache.overall_mshr_miss_rate::total 0.031726 # mshr miss rate for overall accesses 658system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79126.923077 # average ReadReq mshr miss latency 659system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79126.923077 # average ReadReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76978.915663 # average WriteReq mshr miss latency 661system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76978.915663 # average WriteReq mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency 663system.cpu.dcache.demand_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency 665system.cpu.dcache.overall_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency |
| 666system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 667system.cpu.icache.tags.replacements 0 # number of replacements | 666system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 667system.cpu.icache.tags.replacements 0 # number of replacements |
| 668system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use 669system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. | 668system.cpu.icache.tags.tagsinuse 190.975563 # Cycle average of tags in use 669system.cpu.icache.tags.total_refs 5904 # Total number of references to valid blocks. |
| 670system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. | 670system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. |
| 671system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. | 671system.cpu.icache.tags.avg_refs 17.063584 # Average number of references to valid blocks. |
| 672system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 672system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 673system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor 674system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy 675system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy | 673system.cpu.icache.tags.occ_blocks::cpu.inst 190.975563 # Average occupied blocks per requestor 674system.cpu.icache.tags.occ_percent::cpu.inst 0.093250 # Average percentage of cache occupancy 675system.cpu.icache.tags.occ_percent::total 0.093250 # Average percentage of cache occupancy |
| 676system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id | 676system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id |
| 677system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 678system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id | 677system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id 678system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id |
| 679system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id | 679system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id |
| 680system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses 681system.cpu.icache.tags.data_accesses 13252 # Number of data accesses 682system.cpu.icache.ReadReq_hits::cpu.inst 5925 # number of ReadReq hits 683system.cpu.icache.ReadReq_hits::total 5925 # number of ReadReq hits 684system.cpu.icache.demand_hits::cpu.inst 5925 # number of demand (read+write) hits 685system.cpu.icache.demand_hits::total 5925 # number of demand (read+write) hits 686system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits 687system.cpu.icache.overall_hits::total 5925 # number of overall hits 688system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses 689system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses 690system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses 691system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses 692system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses 693system.cpu.icache.overall_misses::total 528 # number of overall misses 694system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles 695system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles 696system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles 697system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles 698system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles 699system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles 700system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses) 702system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses 703system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses 704system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses 705system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses 706system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses 707system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses 708system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses 709system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses 710system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses 711system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses 712system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency 713system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency 714system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency 715system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency 718system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked | 680system.cpu.icache.tags.tag_accesses 13222 # Number of tag accesses 681system.cpu.icache.tags.data_accesses 13222 # Number of data accesses 682system.cpu.icache.ReadReq_hits::cpu.inst 5904 # number of ReadReq hits 683system.cpu.icache.ReadReq_hits::total 5904 # number of ReadReq hits 684system.cpu.icache.demand_hits::cpu.inst 5904 # number of demand (read+write) hits 685system.cpu.icache.demand_hits::total 5904 # number of demand (read+write) hits 686system.cpu.icache.overall_hits::cpu.inst 5904 # number of overall hits 687system.cpu.icache.overall_hits::total 5904 # number of overall hits 688system.cpu.icache.ReadReq_misses::cpu.inst 534 # number of ReadReq misses 689system.cpu.icache.ReadReq_misses::total 534 # number of ReadReq misses 690system.cpu.icache.demand_misses::cpu.inst 534 # number of demand (read+write) misses 691system.cpu.icache.demand_misses::total 534 # number of demand (read+write) misses 692system.cpu.icache.overall_misses::cpu.inst 534 # number of overall misses 693system.cpu.icache.overall_misses::total 534 # number of overall misses 694system.cpu.icache.ReadReq_miss_latency::cpu.inst 37367000 # number of ReadReq miss cycles 695system.cpu.icache.ReadReq_miss_latency::total 37367000 # number of ReadReq miss cycles 696system.cpu.icache.demand_miss_latency::cpu.inst 37367000 # number of demand (read+write) miss cycles 697system.cpu.icache.demand_miss_latency::total 37367000 # number of demand (read+write) miss cycles 698system.cpu.icache.overall_miss_latency::cpu.inst 37367000 # number of overall miss cycles 699system.cpu.icache.overall_miss_latency::total 37367000 # number of overall miss cycles 700system.cpu.icache.ReadReq_accesses::cpu.inst 6438 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.ReadReq_accesses::total 6438 # number of ReadReq accesses(hits+misses) 702system.cpu.icache.demand_accesses::cpu.inst 6438 # number of demand (read+write) accesses 703system.cpu.icache.demand_accesses::total 6438 # number of demand (read+write) accesses 704system.cpu.icache.overall_accesses::cpu.inst 6438 # number of overall (read+write) accesses 705system.cpu.icache.overall_accesses::total 6438 # number of overall (read+write) accesses 706system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082945 # miss rate for ReadReq accesses 707system.cpu.icache.ReadReq_miss_rate::total 0.082945 # miss rate for ReadReq accesses 708system.cpu.icache.demand_miss_rate::cpu.inst 0.082945 # miss rate for demand accesses 709system.cpu.icache.demand_miss_rate::total 0.082945 # miss rate for demand accesses 710system.cpu.icache.overall_miss_rate::cpu.inst 0.082945 # miss rate for overall accesses 711system.cpu.icache.overall_miss_rate::total 0.082945 # miss rate for overall accesses 712system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69975.655431 # average ReadReq miss latency 713system.cpu.icache.ReadReq_avg_miss_latency::total 69975.655431 # average ReadReq miss latency 714system.cpu.icache.demand_avg_miss_latency::cpu.inst 69975.655431 # average overall miss latency 715system.cpu.icache.demand_avg_miss_latency::total 69975.655431 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::cpu.inst 69975.655431 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::total 69975.655431 # average overall miss latency 718system.cpu.icache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked |
| 719system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 721system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 719system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 721system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 722system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked | 722system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked |
| 723system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu.icache.fast_writes 0 # number of fast writes performed 725system.cpu.icache.cache_copies 0 # number of cache copies performed | 723system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu.icache.fast_writes 0 # number of fast writes performed 725system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 726system.cpu.icache.ReadReq_mshr_hits::cpu.inst 182 # number of ReadReq MSHR hits 727system.cpu.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits 728system.cpu.icache.demand_mshr_hits::cpu.inst 182 # number of demand (read+write) MSHR hits 729system.cpu.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits 730system.cpu.icache.overall_mshr_hits::cpu.inst 182 # number of overall MSHR hits 731system.cpu.icache.overall_mshr_hits::total 182 # number of overall MSHR hits | 726system.cpu.icache.ReadReq_mshr_hits::cpu.inst 188 # number of ReadReq MSHR hits 727system.cpu.icache.ReadReq_mshr_hits::total 188 # number of ReadReq MSHR hits 728system.cpu.icache.demand_mshr_hits::cpu.inst 188 # number of demand (read+write) MSHR hits 729system.cpu.icache.demand_mshr_hits::total 188 # number of demand (read+write) MSHR hits 730system.cpu.icache.overall_mshr_hits::cpu.inst 188 # number of overall MSHR hits 731system.cpu.icache.overall_mshr_hits::total 188 # number of overall MSHR hits |
| 732system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses 733system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses 734system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses 735system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses 736system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses 737system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses | 732system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses 733system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses 734system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses 735system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses 736system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses 737system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses |
| 738system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles 739system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles 740system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles 741system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles 742system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles 743system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles 744system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses 745system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses 746system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses 747system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses 748system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses 749system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency 751system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency 753system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency 755system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency | 738system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26526250 # number of ReadReq MSHR miss cycles 739system.cpu.icache.ReadReq_mshr_miss_latency::total 26526250 # number of ReadReq MSHR miss cycles 740system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26526250 # number of demand (read+write) MSHR miss cycles 741system.cpu.icache.demand_mshr_miss_latency::total 26526250 # number of demand (read+write) MSHR miss cycles 742system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26526250 # number of overall MSHR miss cycles 743system.cpu.icache.overall_mshr_miss_latency::total 26526250 # number of overall MSHR miss cycles 744system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for ReadReq accesses 745system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053743 # mshr miss rate for ReadReq accesses 746system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for demand accesses 747system.cpu.icache.demand_mshr_miss_rate::total 0.053743 # mshr miss rate for demand accesses 748system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for overall accesses 749system.cpu.icache.overall_mshr_miss_rate::total 0.053743 # mshr miss rate for overall accesses 750system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76665.462428 # average ReadReq mshr miss latency 751system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76665.462428 # average ReadReq mshr miss latency 752system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency 753system.cpu.icache.demand_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency 754system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency 755system.cpu.icache.overall_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency |
| 756system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 757system.cpu.l2cache.tags.replacements 0 # number of replacements | 756system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 757system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 758system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use | 758system.cpu.l2cache.tags.tagsinuse 224.896195 # Cycle average of tags in use |
| 759system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 760system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks. 761system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks. 762system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 759system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 760system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks. 761system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks. 762system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 763system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor 764system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor 765system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy 767system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy | 763system.cpu.l2cache.tags.occ_blocks::cpu.inst 190.368376 # Average occupied blocks per requestor 764system.cpu.l2cache.tags.occ_blocks::cpu.data 34.527819 # Average occupied blocks per requestor 765system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005810 # Average percentage of cache occupancy 766system.cpu.l2cache.tags.occ_percent::cpu.data 0.001054 # Average percentage of cache occupancy 767system.cpu.l2cache.tags.occ_percent::total 0.006863 # Average percentage of cache occupancy |
| 768system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id | 768system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id |
| 769system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 770system.cpu.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id | 769system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id 770system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id |
| 771system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id 772system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses 773system.cpu.l2cache.tags.data_accesses 4443 # Number of data accesses 774system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 775system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 776system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 777system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 778system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits --- 4 unchanged lines hidden (view full) --- 783system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 784system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 785system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 786system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses 787system.cpu.l2cache.demand_misses::total 492 # number of demand (read+write) misses 788system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 789system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses 790system.cpu.l2cache.overall_misses::total 492 # number of overall misses | 771system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id 772system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses 773system.cpu.l2cache.tags.data_accesses 4443 # Number of data accesses 774system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 775system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 776system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 777system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 778system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits --- 4 unchanged lines hidden (view full) --- 783system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 784system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 785system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 786system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses 787system.cpu.l2cache.demand_misses::total 492 # number of demand (read+write) misses 788system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 789system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses 790system.cpu.l2cache.overall_misses::total 492 # number of overall misses |
| 791system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles 792system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles 793system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles 794system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles 795system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles 796system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles 797system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles 798system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles 799system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles 800system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles 801system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles | 791system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26158750 # number of ReadReq miss cycles 792system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5078750 # number of ReadReq miss cycles 793system.cpu.l2cache.ReadReq_miss_latency::total 31237500 # number of ReadReq miss cycles 794system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6304750 # number of ReadExReq miss cycles 795system.cpu.l2cache.ReadExReq_miss_latency::total 6304750 # number of ReadExReq miss cycles 796system.cpu.l2cache.demand_miss_latency::cpu.inst 26158750 # number of demand (read+write) miss cycles 797system.cpu.l2cache.demand_miss_latency::cpu.data 11383500 # number of demand (read+write) miss cycles 798system.cpu.l2cache.demand_miss_latency::total 37542250 # number of demand (read+write) miss cycles 799system.cpu.l2cache.overall_miss_latency::cpu.inst 26158750 # number of overall miss cycles 800system.cpu.l2cache.overall_miss_latency::cpu.data 11383500 # number of overall miss cycles 801system.cpu.l2cache.overall_miss_latency::total 37542250 # number of overall miss cycles |
| 802system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses) 803system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) 804system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) 805system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 806system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 807system.cpu.l2cache.demand_accesses::cpu.inst 346 # number of demand (read+write) accesses 808system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses 809system.cpu.l2cache.demand_accesses::total 494 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 816system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 817system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 818system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses 819system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 820system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses 821system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses 822system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 823system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses | 802system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses) 803system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) 804system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) 805system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 806system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 807system.cpu.l2cache.demand_accesses::cpu.inst 346 # number of demand (read+write) accesses 808system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses 809system.cpu.l2cache.demand_accesses::total 494 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 816system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 817system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 818system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses 819system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 820system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses 821system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses 822system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 823system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses |
| 824system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency 825system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency 826system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency 827system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency 828system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency 829system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency 830system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency 831system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency 832system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency 833system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency 834system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency | 824system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76042.877907 # average ReadReq miss latency 825system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78134.615385 # average ReadReq miss latency 826system.cpu.l2cache.ReadReq_avg_miss_latency::total 76375.305623 # average ReadReq miss latency 827system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75960.843373 # average ReadExReq miss latency 828system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75960.843373 # average ReadExReq miss latency 829system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency 830system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency 831system.cpu.l2cache.demand_avg_miss_latency::total 76305.386179 # average overall miss latency 832system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency 833system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency 834system.cpu.l2cache.overall_avg_miss_latency::total 76305.386179 # average overall miss latency |
| 835system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 836system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 837system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 838system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 839system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 840system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu.l2cache.fast_writes 0 # number of fast writes performed 842system.cpu.l2cache.cache_copies 0 # number of cache copies performed 843system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses 844system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 845system.cpu.l2cache.ReadReq_mshr_misses::total 409 # number of ReadReq MSHR misses 846system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 847system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 848system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 850system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses 851system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 852system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 853system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses | 835system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 836system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 837system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 838system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 839system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 840system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 841system.cpu.l2cache.fast_writes 0 # number of fast writes performed 842system.cpu.l2cache.cache_copies 0 # number of cache copies performed 843system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses 844system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 845system.cpu.l2cache.ReadReq_mshr_misses::total 409 # number of ReadReq MSHR misses 846system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 847system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 848system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 849system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 850system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses 851system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 852system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 853system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses |
| 854system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles 855system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles 856system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles 857system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles 858system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles 859system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles 862system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles 864system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles | 854system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21861250 # number of ReadReq MSHR miss cycles 855system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4272750 # number of ReadReq MSHR miss cycles 856system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26134000 # number of ReadReq MSHR miss cycles 857system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5278250 # number of ReadExReq MSHR miss cycles 858system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5278250 # number of ReadExReq MSHR miss cycles 859system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21861250 # number of demand (read+write) MSHR miss cycles 860system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles 861system.cpu.l2cache.demand_mshr_miss_latency::total 31412250 # number of demand (read+write) MSHR miss cycles 862system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21861250 # number of overall MSHR miss cycles 863system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles 864system.cpu.l2cache.overall_mshr_miss_latency::total 31412250 # number of overall MSHR miss cycles |
| 865system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses 866system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 867system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses 868system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 869system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 870system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses 871system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 872system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses 873system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses 874system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 875system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses | 865system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses 866system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 867system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses 868system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 869system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 870system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses 871system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 872system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses 873system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses 874system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 875system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses |
| 876system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency 877system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency 878system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency 879system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency 880system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency 882system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency 883system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency 886system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency | 876system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63550.145349 # average ReadReq mshr miss latency 877system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65734.615385 # average ReadReq mshr miss latency 878system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63897.310513 # average ReadReq mshr miss latency 879system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63593.373494 # average ReadExReq mshr miss latency 880system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63593.373494 # average ReadExReq mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency 882system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency 883system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency 886system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency |
| 887system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 888system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 892system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) 893system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) 894system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) --- 8 unchanged lines hidden (view full) --- 903system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 904system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram 905system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram 910system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) | 887system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 888system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 892system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) 893system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) 894system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) --- 8 unchanged lines hidden (view full) --- 903system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 904system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram 905system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram 910system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) |
| 911system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 912system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) 913system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 914system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) | 911system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 912system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) 913system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 914system.cpu.toL2Bus.respLayer1.occupancy 245000 # Layer occupancy (ticks) |
| 915system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 916system.membus.trans_dist::ReadReq 409 # Transaction distribution 917system.membus.trans_dist::ReadResp 408 # Transaction distribution 918system.membus.trans_dist::ReadExReq 83 # Transaction distribution 919system.membus.trans_dist::ReadExResp 83 # Transaction distribution 920system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) 921system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) 922system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 927system.membus.snoop_fanout::stdev 0 # Request fanout histogram 928system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 929system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram 930system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 931system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 932system.membus.snoop_fanout::min_value 0 # Request fanout histogram 933system.membus.snoop_fanout::max_value 0 # Request fanout histogram 934system.membus.snoop_fanout::total 492 # Request fanout histogram | 915system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 916system.membus.trans_dist::ReadReq 409 # Transaction distribution 917system.membus.trans_dist::ReadResp 408 # Transaction distribution 918system.membus.trans_dist::ReadExReq 83 # Transaction distribution 919system.membus.trans_dist::ReadExResp 83 # Transaction distribution 920system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) 921system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) 922system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 927system.membus.snoop_fanout::stdev 0 # Request fanout histogram 928system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 929system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram 930system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 931system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 932system.membus.snoop_fanout::min_value 0 # Request fanout histogram 933system.membus.snoop_fanout::max_value 0 # Request fanout histogram 934system.membus.snoop_fanout::total 492 # Request fanout histogram |
| 935system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) 936system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 937system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) 938system.membus.respLayer1.utilization 17.7 # Layer utilization (%) | 935system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) 936system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) 937system.membus.respLayer1.occupancy 2599750 # Layer occupancy (ticks) 938system.membus.respLayer1.utilization 9.5 # Layer utilization (%) |
| 939 940---------- End Simulation Statistics ---------- | 939 940---------- End Simulation Statistics ---------- |