| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25944000 # Number of ticks simulated 5final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25944000 # Number of ticks simulated 5final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 15615 # Simulator instruction rate (inst/s) 8host_op_rate 15615 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 28062245 # Simulator tick rate (ticks/s) 10host_mem_usage 236980 # Number of bytes of host memory used 11host_seconds 0.92 # Real time elapsed on the host | 7host_inst_rate 95549 # Simulator instruction rate (inst/s) 8host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 171686089 # Simulator tick rate (ticks/s) 10host_mem_usage 292480 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31488 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory --- 197 unchanged lines hidden (view full) --- 217system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 411 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 52627.03 # Average gap between requests 224system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31488 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory --- 197 unchanged lines hidden (view full) --- 217system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 411 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 52627.03 # Average gap between requests 224system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined |
| 225system.physmem.memoryStateTime::IDLE 279250 # Time in different power states 226system.physmem.memoryStateTime::REF 780000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 22761250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.physmem.actEnergy::0 309960 # Energy for activate commands per rank (pJ) 231system.physmem.actEnergy::1 226800 # Energy for activate commands per rank (pJ) 232system.physmem.preEnergy::0 169125 # Energy for precharge commands per rank (pJ) 233system.physmem.preEnergy::1 123750 # Energy for precharge commands per rank (pJ) 234system.physmem.readEnergy::0 2106000 # Energy for read commands per rank (pJ) 235system.physmem.readEnergy::1 1318200 # Energy for read commands per rank (pJ) 236system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 237system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 238system.physmem.refreshEnergy::0 1525680 # Energy for refresh commands per rank (pJ) 239system.physmem.refreshEnergy::1 1525680 # Energy for refresh commands per rank (pJ) 240system.physmem.actBackEnergy::0 16044930 # Energy for active background per rank (pJ) 241system.physmem.actBackEnergy::1 14873580 # Energy for active background per rank (pJ) 242system.physmem.preBackEnergy::0 96750 # Energy for precharge background per rank (pJ) 243system.physmem.preBackEnergy::1 1124250 # Energy for precharge background per rank (pJ) 244system.physmem.totalEnergy::0 20252445 # Total energy per rank (pJ) 245system.physmem.totalEnergy::1 19192260 # Total energy per rank (pJ) 246system.physmem.averagePower::0 857.473194 # Core power per rank (mW) 247system.physmem.averagePower::1 812.585763 # Core power per rank (mW) 248system.membus.trans_dist::ReadReq 409 # Transaction distribution 249system.membus.trans_dist::ReadResp 408 # Transaction distribution 250system.membus.trans_dist::ReadExReq 83 # Transaction distribution 251system.membus.trans_dist::ReadExResp 83 # Transaction distribution 252system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) 253system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) 254system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) 255system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) 256system.membus.snoops 0 # Total snoops (count) 257system.membus.snoop_fanout::samples 492 # Request fanout histogram 258system.membus.snoop_fanout::mean 0 # Request fanout histogram 259system.membus.snoop_fanout::stdev 0 # Request fanout histogram 260system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 261system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram 262system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 263system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 264system.membus.snoop_fanout::min_value 0 # Request fanout histogram 265system.membus.snoop_fanout::max_value 0 # Request fanout histogram 266system.membus.snoop_fanout::total 492 # Request fanout histogram 267system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) 268system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 269system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) 270system.membus.respLayer1.utilization 17.7 # Layer utilization (%) 271system.cpu_clk_domain.clock 500 # Clock period in ticks | 225system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 16044930 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 96750 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 20252445 # Total energy per rank (pJ) 233system.physmem_0.averagePower 857.473194 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 279250 # Time in different power states 235system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 22761250 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 14873580 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 1124250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 19192260 # Total energy per rank (pJ) 247system.physmem_1.averagePower 812.585763 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 2246250 # Time in different power states 249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 21062250 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 272system.cpu.branchPred.lookups 8578 # Number of BP lookups 273system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted 274system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect 275system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups 276system.cpu.branchPred.BTBHits 3046 # Number of BTB hits 277system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 278system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage 279system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target. 280system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. | 253system.cpu.branchPred.lookups 8578 # Number of BP lookups 254system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 3046 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. |
| 262system.cpu_clk_domain.clock 500 # Clock period in ticks |
|
| 281system.cpu.workload.num_syscalls 18 # Number of system calls 282system.cpu.numCycles 51889 # number of cpu cycles simulated 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 285system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken --- 272 unchanged lines hidden (view full) --- 561system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction 562system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads 563system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle 564system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads 565system.cpu.int_regfile_reads 33401 # number of integer regfile reads 566system.cpu.int_regfile_writes 18599 # number of integer regfile writes 567system.cpu.misc_regfile_reads 7136 # number of misc regfile reads 568system.cpu.misc_regfile_writes 569 # number of misc regfile writes | 263system.cpu.workload.num_syscalls 18 # Number of system calls 264system.cpu.numCycles 51889 # number of cpu cycles simulated 265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 267system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss 268system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed 269system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered 270system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken --- 272 unchanged lines hidden (view full) --- 543system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction 544system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads 545system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle 546system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads 547system.cpu.int_regfile_reads 33401 # number of integer regfile reads 548system.cpu.int_regfile_writes 18599 # number of integer regfile writes 549system.cpu.misc_regfile_reads 7136 # number of misc regfile reads 550system.cpu.misc_regfile_writes 569 # number of misc regfile writes |
| 569system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution 570system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution 571system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 572system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 573system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) 574system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) 575system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) 576system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) 577system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 578system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) 579system.cpu.toL2Bus.snoops 0 # Total snoops (count) 580system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram 581system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 582system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 583system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 584system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 585system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram 586system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 587system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 588system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 589system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 590system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram 591system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) 592system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 593system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) 594system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 595system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) 596system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) | 551system.cpu.dcache.tags.replacements 0 # number of replacements 552system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use 553system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. 554system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 555system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. 556system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 557system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor 558system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy 559system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy 560system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 561system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 562system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 563system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 564system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses 565system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses 566system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits 567system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits 568system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 569system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 570system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 571system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 572system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits 573system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits 574system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits 575system.cpu.dcache.overall_hits::total 4118 # number of overall hits 576system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses 577system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses 578system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 579system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 580system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses 581system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses 582system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses 583system.cpu.dcache.overall_misses::total 548 # number of overall misses 584system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles 585system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles 586system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles 587system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles 588system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles 589system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles 590system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles 591system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles 592system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) 593system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) 594system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 595system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 596system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 597system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 598system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses 599system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses 600system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses 601system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses 602system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses 603system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses 604system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 605system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses 606system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses 607system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses 608system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses 609system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses 610system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency 611system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency 612system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency 613system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency 614system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency 615system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency 616system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency 617system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency 618system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked 619system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 620system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked 621system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 622system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked 623system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 624system.cpu.dcache.fast_writes 0 # number of fast writes performed 625system.cpu.dcache.cache_copies 0 # number of cache copies performed 626system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits 627system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 628system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 629system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits 630system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits 631system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits 632system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits 633system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits 634system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 635system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 636system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 637system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 638system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 639system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 640system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 641system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses 642system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles 643system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles 644system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles 645system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles 646system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles 647system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles 648system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles 649system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles 650system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses 651system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses 652system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 653system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses 654system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses 655system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses 656system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses 657system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses 658system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency 659system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency 660system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency 661system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency 662system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency 663system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency 664system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency 665system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency 666system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 597system.cpu.icache.tags.replacements 0 # number of replacements 598system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use 599system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. 600system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. 601system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. 602system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 603system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor 604system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy --- 205 unchanged lines hidden (view full) --- 810system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency 811system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency 812system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency 813system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency 814system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency 815system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency 816system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency 817system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 667system.cpu.icache.tags.replacements 0 # number of replacements 668system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use 669system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. 670system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. 671system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. 672system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 673system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor 674system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy --- 205 unchanged lines hidden (view full) --- 880system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency 881system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency 882system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency 883system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency 884system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency 885system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency 886system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency 887system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 818system.cpu.dcache.tags.replacements 0 # number of replacements 819system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use 820system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. 821system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 822system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. 823system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 824system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor 825system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy 826system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy 827system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 828system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 829system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 830system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 831system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses 832system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses 833system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits 834system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits 835system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits 836system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits 837system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits 838system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits 839system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits 840system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits 841system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits 842system.cpu.dcache.overall_hits::total 4118 # number of overall hits 843system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses 844system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses 845system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 846system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 847system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses 848system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses 849system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses 850system.cpu.dcache.overall_misses::total 548 # number of overall misses 851system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles 852system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles 853system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles 854system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles 855system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles 856system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles 857system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles 858system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles 859system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) 860system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) 861system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 862system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 863system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 864system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 865system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses 866system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses 867system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses 868system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses 869system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses 870system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses 871system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 872system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses 873system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses 874system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses 875system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses 876system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses 877system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency 878system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency 879system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency 880system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency 881system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency 882system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency 883system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency 884system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency 885system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked 886system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 887system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked 888system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 889system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked 890system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 891system.cpu.dcache.fast_writes 0 # number of fast writes performed 892system.cpu.dcache.cache_copies 0 # number of cache copies performed 893system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits 894system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 895system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 896system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits 897system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits 898system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits 899system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits 900system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits 901system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 902system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 903system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 904system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 905system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 906system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 907system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 908system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses 909system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles 910system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles 911system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles 912system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles 913system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles 914system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles 915system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles 916system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles 917system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses 918system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses 919system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 920system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses 921system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses 922system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses 923system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses 924system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses 925system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency 926system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency 927system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency 928system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency 929system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency 930system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency 931system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency 932system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency 933system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 888system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 892system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) 893system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) 894system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) 895system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) 896system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 897system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) 898system.cpu.toL2Bus.snoops 0 # Total snoops (count) 899system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram 900system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 901system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 902system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 903system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 904system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram 905system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 907system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 908system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 909system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram 910system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) 911system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 912system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) 913system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 914system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) 915system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 916system.membus.trans_dist::ReadReq 409 # Transaction distribution 917system.membus.trans_dist::ReadResp 408 # Transaction distribution 918system.membus.trans_dist::ReadExReq 83 # Transaction distribution 919system.membus.trans_dist::ReadExResp 83 # Transaction distribution 920system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) 921system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) 922system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) 923system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) 924system.membus.snoops 0 # Total snoops (count) 925system.membus.snoop_fanout::samples 492 # Request fanout histogram 926system.membus.snoop_fanout::mean 0 # Request fanout histogram 927system.membus.snoop_fanout::stdev 0 # Request fanout histogram 928system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 929system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram 930system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 931system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 932system.membus.snoop_fanout::min_value 0 # Request fanout histogram 933system.membus.snoop_fanout::max_value 0 # Request fanout histogram 934system.membus.snoop_fanout::total 492 # Request fanout histogram 935system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) 936system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 937system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) 938system.membus.respLayer1.utilization 17.7 # Layer utilization (%) |
| 934 935---------- End Simulation Statistics ---------- | 939 940---------- End Simulation Statistics ---------- |