| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25944000 # Number of ticks simulated 5final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25944000 # Number of ticks simulated 5final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 14664 # Simulator instruction rate (inst/s) 8host_op_rate 14664 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26353337 # Simulator tick rate (ticks/s) 10host_mem_usage 237548 # Number of bytes of host memory used 11host_seconds 0.98 # Real time elapsed on the host | 7host_inst_rate 79125 # Simulator instruction rate (inst/s) 8host_op_rate 79119 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 142180718 # Simulator tick rate (ticks/s) 10host_mem_usage 289004 # Number of bytes of host memory used 11host_seconds 0.18 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31488 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory --- 66 unchanged lines hidden (view full) --- 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31488 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory --- 66 unchanged lines hidden (view full) --- 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see |
| 94system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 91 unchanged lines hidden (view full) --- 195system.physmem.bytesPerActivate::256-383 7 9.72% 59.72% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.56% 65.28% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 5.56% 70.83% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 4.17% 75.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation | 96system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 91 unchanged lines hidden (view full) --- 195system.physmem.bytesPerActivate::256-383 7 9.72% 59.72% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.56% 65.28% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 5.56% 70.83% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 4.17% 75.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation |
| 203system.physmem.totQLat 2648500 # Total ticks spent queuing 204system.physmem.totMemAccLat 11873500 # Total ticks spent from burst creation until serviced by the DRAM | 203system.physmem.totQLat 2786000 # Total ticks spent queuing 204system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 5383.13 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 24133.13 # Average memory access latency per DRAM burst | 208system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst |
| 209system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 9.48 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.48 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 52627.03 # Average gap between requests 224system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 279250 # Time in different power states 226system.physmem.memoryStateTime::REF 780000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 22761250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 209system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 9.48 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.48 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 52627.03 # Average gap between requests 224system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 279250 # Time in different power states 226system.physmem.memoryStateTime::REF 780000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 22761250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 230system.membus.throughput 1211224175 # Throughput (bytes/s) | |
| 231system.membus.trans_dist::ReadReq 409 # Transaction distribution 232system.membus.trans_dist::ReadResp 408 # Transaction distribution 233system.membus.trans_dist::ReadExReq 83 # Transaction distribution 234system.membus.trans_dist::ReadExResp 83 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) | 230system.membus.trans_dist::ReadReq 409 # Transaction distribution 231system.membus.trans_dist::ReadResp 408 # Transaction distribution 232system.membus.trans_dist::ReadExReq 83 # Transaction distribution 233system.membus.trans_dist::ReadExResp 83 # Transaction distribution 234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes) |
| 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 31424 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 236system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes) 237system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes) 238system.membus.snoops 0 # Total snoops (count) 239system.membus.snoop_fanout::samples 492 # Request fanout histogram 240system.membus.snoop_fanout::mean 0 # Request fanout histogram 241system.membus.snoop_fanout::stdev 0 # Request fanout histogram 242system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 243system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram 244system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 245system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 246system.membus.snoop_fanout::min_value 0 # Request fanout histogram 247system.membus.snoop_fanout::max_value 0 # Request fanout histogram 248system.membus.snoop_fanout::total 492 # Request fanout histogram |
| 241system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) 242system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 243system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 17.7 # Layer utilization (%) 245system.cpu_clk_domain.clock 500 # Clock period in ticks 246system.cpu.branchPred.lookups 8578 # Number of BP lookups 247system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect --- 286 unchanged lines hidden (view full) --- 535system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction 536system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads 537system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle 538system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads 539system.cpu.int_regfile_reads 33400 # number of integer regfile reads 540system.cpu.int_regfile_writes 18599 # number of integer regfile writes 541system.cpu.misc_regfile_reads 7136 # number of misc regfile reads 542system.cpu.misc_regfile_writes 569 # number of misc regfile writes | 249system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) 250system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 251system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) 252system.membus.respLayer1.utilization 17.7 # Layer utilization (%) 253system.cpu_clk_domain.clock 500 # Clock period in ticks 254system.cpu.branchPred.lookups 8578 # Number of BP lookups 255system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted 256system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect --- 286 unchanged lines hidden (view full) --- 543system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction 544system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads 545system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle 546system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads 547system.cpu.int_regfile_reads 33400 # number of integer regfile reads 548system.cpu.int_regfile_writes 18599 # number of integer regfile writes 549system.cpu.misc_regfile_reads 7136 # number of misc regfile reads 550system.cpu.misc_regfile_writes 569 # number of misc regfile writes |
| 543system.cpu.toL2Bus.throughput 1216157879 # Throughput (bytes/s) | |
| 544system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution 545system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution 546system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 547system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 548system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) 549system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) 550system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) | 551system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution 552system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 554system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 555system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) 556system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes) 557system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes) |
| 551system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) 552system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 553system.cpu.toL2Bus.tot_pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) 554system.cpu.toL2Bus.data_through_bus 31552 # Total data (bytes) 555system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 558system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) 559system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 560system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) 561system.cpu.toL2Bus.snoops 0 # Total snoops (count) 562system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram 563system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 564system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 565system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 566system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 567system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram 568system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 569system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 570system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 571system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 572system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram |
| 556system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) 557system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 558system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) 559system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 560system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) 561system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 562system.cpu.icache.tags.replacements 0 # number of replacements | 573system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) 574system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 575system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) 576system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 577system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) 578system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 579system.cpu.icache.tags.replacements 0 # number of replacements |
| 563system.cpu.icache.tags.tagsinuse 192.510615 # Cycle average of tags in use | 580system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use |
| 564system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. 565system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. 566system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. 567system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 581system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. 582system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. 583system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. 584system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 568system.cpu.icache.tags.occ_blocks::cpu.inst 192.510615 # Average occupied blocks per requestor | 585system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor |
| 569system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy 570system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy 571system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id 572system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 573system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id 574system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id 575system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses 576system.cpu.icache.tags.data_accesses 13252 # Number of data accesses --- 4 unchanged lines hidden (view full) --- 581system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits 582system.cpu.icache.overall_hits::total 5925 # number of overall hits 583system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses 584system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses 585system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses 586system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses 587system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses 588system.cpu.icache.overall_misses::total 528 # number of overall misses | 586system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy 587system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy 588system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 590system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id 591system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id 592system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses 593system.cpu.icache.tags.data_accesses 13252 # Number of data accesses --- 4 unchanged lines hidden (view full) --- 598system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits 599system.cpu.icache.overall_hits::total 5925 # number of overall hits 600system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses 601system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses 602system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses 603system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses 604system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses 605system.cpu.icache.overall_misses::total 528 # number of overall misses |
| 589system.cpu.icache.ReadReq_miss_latency::cpu.inst 32454000 # number of ReadReq miss cycles 590system.cpu.icache.ReadReq_miss_latency::total 32454000 # number of ReadReq miss cycles 591system.cpu.icache.demand_miss_latency::cpu.inst 32454000 # number of demand (read+write) miss cycles 592system.cpu.icache.demand_miss_latency::total 32454000 # number of demand (read+write) miss cycles 593system.cpu.icache.overall_miss_latency::cpu.inst 32454000 # number of overall miss cycles 594system.cpu.icache.overall_miss_latency::total 32454000 # number of overall miss cycles | 606system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles 607system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles 608system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles 609system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles 610system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles 611system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles |
| 595system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses) 596system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses) 597system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses 598system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses 599system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses 600system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses 601system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses 602system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses 603system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses 604system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses 605system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses 606system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses | 612system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses) 613system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses) 614system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses 615system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses 616system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses 617system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses 618system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses 619system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses 620system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses 621system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses 622system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses 623system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses |
| 607system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61465.909091 # average ReadReq miss latency 608system.cpu.icache.ReadReq_avg_miss_latency::total 61465.909091 # average ReadReq miss latency 609system.cpu.icache.demand_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency 610system.cpu.icache.demand_avg_miss_latency::total 61465.909091 # average overall miss latency 611system.cpu.icache.overall_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency 612system.cpu.icache.overall_avg_miss_latency::total 61465.909091 # average overall miss latency | 624system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency 625system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency 626system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency 627system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency 628system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency 629system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency |
| 613system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked 614system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 615system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 616system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 617system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked 618system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 619system.cpu.icache.fast_writes 0 # number of fast writes performed 620system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 625system.cpu.icache.overall_mshr_hits::cpu.inst 182 # number of overall MSHR hits 626system.cpu.icache.overall_mshr_hits::total 182 # number of overall MSHR hits 627system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses 628system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses 629system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses 630system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses 631system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses 632system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses | 630system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked 631system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 633system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 634system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked 635system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.icache.fast_writes 0 # number of fast writes performed 637system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 642system.cpu.icache.overall_mshr_hits::cpu.inst 182 # number of overall MSHR hits 643system.cpu.icache.overall_mshr_hits::total 182 # number of overall MSHR hits 644system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses 645system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses 646system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses 647system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses 648system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses 649system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses |
| 633system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23048750 # number of ReadReq MSHR miss cycles 634system.cpu.icache.ReadReq_mshr_miss_latency::total 23048750 # number of ReadReq MSHR miss cycles 635system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23048750 # number of demand (read+write) MSHR miss cycles 636system.cpu.icache.demand_mshr_miss_latency::total 23048750 # number of demand (read+write) MSHR miss cycles 637system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23048750 # number of overall MSHR miss cycles 638system.cpu.icache.overall_mshr_miss_latency::total 23048750 # number of overall MSHR miss cycles | 650system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles 651system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles 652system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles 653system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles 654system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles 655system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles |
| 639system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses 640system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses 641system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses 642system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses 643system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses 644system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses | 656system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses 657system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses 658system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses 659system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses 660system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses 661system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses |
| 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66614.884393 # average ReadReq mshr miss latency 646system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66614.884393 # average ReadReq mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency 648system.cpu.icache.demand_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency 650system.cpu.icache.overall_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency | 662system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency 663system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency 664system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency 665system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency 666system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency 667system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency |
| 651system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 652system.cpu.l2cache.tags.replacements 0 # number of replacements 653system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use 654system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 655system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks. 656system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks. 657system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 668system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 669system.cpu.l2cache.tags.replacements 0 # number of replacements 670system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use 671system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 672system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks. 673system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks. 674system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 658system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902478 # Average occupied blocks per requestor 659system.cpu.l2cache.tags.occ_blocks::cpu.data 34.634175 # Average occupied blocks per requestor | 675system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor 676system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor |
| 660system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy 661system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy 662system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy 663system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id 664system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 665system.cpu.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 666system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id 667system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses --- 10 unchanged lines hidden (view full) --- 678system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 679system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 680system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 681system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses 682system.cpu.l2cache.demand_misses::total 492 # number of demand (read+write) misses 683system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 684system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses 685system.cpu.l2cache.overall_misses::total 492 # number of overall misses | 677system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy 678system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy 679system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy 680system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id 681system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 682system.cpu.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id 683system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id 684system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses --- 10 unchanged lines hidden (view full) --- 695system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 696system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 697system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 698system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses 699system.cpu.l2cache.demand_misses::total 492 # number of demand (read+write) misses 700system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 701system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses 702system.cpu.l2cache.overall_misses::total 492 # number of overall misses |
| 686system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22682250 # number of ReadReq miss cycles 687system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4667500 # number of ReadReq miss cycles | 703system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles 704system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles |
| 688system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles 689system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles 690system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles | 705system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles 706system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles 707system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles |
| 691system.cpu.l2cache.demand_miss_latency::cpu.inst 22682250 # number of demand (read+write) miss cycles 692system.cpu.l2cache.demand_miss_latency::cpu.data 10818500 # number of demand (read+write) miss cycles | 708system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles 709system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles |
| 693system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles | 710system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles |
| 694system.cpu.l2cache.overall_miss_latency::cpu.inst 22682250 # number of overall miss cycles 695system.cpu.l2cache.overall_miss_latency::cpu.data 10818500 # number of overall miss cycles | 711system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles 712system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles |
| 696system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles 697system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses) 698system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) 699system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) 700system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 701system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 702system.cpu.l2cache.demand_accesses::cpu.inst 346 # number of demand (read+write) accesses 703system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses --- 7 unchanged lines hidden (view full) --- 711system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 712system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 713system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses 714system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 715system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses 716system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses 717system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 718system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses | 713system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles 714system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses) 715system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) 716system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) 717system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 718system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 719system.cpu.l2cache.demand_accesses::cpu.inst 346 # number of demand (read+write) accesses 720system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses --- 7 unchanged lines hidden (view full) --- 728system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 729system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 730system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses 731system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 732system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses 733system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses 734system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 735system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses |
| 719system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.773256 # average ReadReq miss latency 720system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71807.692308 # average ReadReq miss latency | 736system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency 737system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency |
| 721system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency 722system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency 723system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency | 738system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency 739system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency 740system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency |
| 724system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency 725system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency | 741system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency 742system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency |
| 726system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency | 743system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency |
| 727system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency 728system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency | 744system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency 745system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency |
| 729system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency 730system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 731system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 732system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 733system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 734system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 735system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 736system.cpu.l2cache.fast_writes 0 # number of fast writes performed --- 4 unchanged lines hidden (view full) --- 741system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 742system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 743system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 744system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 745system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses 746system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 747system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 748system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses | 746system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency 747system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 748system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 749system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 750system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 751system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 752system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 753system.cpu.l2cache.fast_writes 0 # number of fast writes performed --- 4 unchanged lines hidden (view full) --- 758system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 759system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 760system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 761system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 762system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses 763system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 764system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 765system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses |
| 749system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18356250 # number of ReadReq MSHR miss cycles 750system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3880500 # number of ReadReq MSHR miss cycles | 766system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles 767system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles |
| 751system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles 752system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles 753system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles | 768system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles 769system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles 770system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles |
| 754system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18356250 # number of demand (read+write) MSHR miss cycles 755system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9012000 # number of demand (read+write) MSHR miss cycles | 771system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles 772system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles |
| 756system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles | 773system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles |
| 757system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18356250 # number of overall MSHR miss cycles 758system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9012000 # number of overall MSHR miss cycles | 774system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles 775system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles |
| 759system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles 760system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses 761system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 762system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses 763system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 764system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 765system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses 766system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 767system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses 768system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses 769system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 770system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses | 776system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles 777system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses 778system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 779system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses 780system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 781system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 782system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses 783system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 784system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses 785system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses 786system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 787system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses |
| 771system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53361.191860 # average ReadReq mshr miss latency 772system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59700 # average ReadReq mshr miss latency | 788system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency 789system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency |
| 773system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency 774system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency 775system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency | 790system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency 791system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency 792system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency |
| 776system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency | 793system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency 794system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency |
| 778system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency | 795system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency |
| 779system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency | 796system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency 797system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency |
| 781system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency 782system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 783system.cpu.dcache.tags.replacements 0 # number of replacements | 798system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency 799system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 800system.cpu.dcache.tags.replacements 0 # number of replacements |
| 784system.cpu.dcache.tags.tagsinuse 98.823641 # Cycle average of tags in use | 801system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use |
| 785system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. 786system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 787system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. 788system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 802system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. 803system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 804system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. 805system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 789system.cpu.dcache.tags.occ_blocks::cpu.data 98.823641 # Average occupied blocks per requestor | 806system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor |
| 790system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy 791system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy 792system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 793system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 794system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 795system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 796system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses 797system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses --- 10 unchanged lines hidden (view full) --- 808system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses 809system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses 810system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 811system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 812system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses 813system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses 814system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses 815system.cpu.dcache.overall_misses::total 548 # number of overall misses | 807system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy 808system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy 809system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 810system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 811system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id 812system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 813system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses 814system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses --- 10 unchanged lines hidden (view full) --- 825system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses 826system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses 827system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 828system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 829system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses 830system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses 831system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses 832system.cpu.dcache.overall_misses::total 548 # number of overall misses |
| 816system.cpu.dcache.ReadReq_miss_latency::cpu.data 8661750 # number of ReadReq miss cycles 817system.cpu.dcache.ReadReq_miss_latency::total 8661750 # number of ReadReq miss cycles | 833system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles 834system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles |
| 818system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles 819system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles | 835system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles 836system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles |
| 820system.cpu.dcache.demand_miss_latency::cpu.data 34754974 # number of demand (read+write) miss cycles 821system.cpu.dcache.demand_miss_latency::total 34754974 # number of demand (read+write) miss cycles 822system.cpu.dcache.overall_miss_latency::cpu.data 34754974 # number of overall miss cycles 823system.cpu.dcache.overall_miss_latency::total 34754974 # number of overall miss cycles | 837system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles 838system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles 839system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles 840system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles |
| 824system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) 825system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) 826system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 827system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 828system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 829system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 830system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses 831system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses 832system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses 833system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses 834system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses 835system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses 836system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 837system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses 838system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses 839system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses 840system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses 841system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses | 841system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) 842system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) 843system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 844system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 845system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 846system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 847system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses 848system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses 849system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses 850system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses 851system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses 852system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses 853system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 854system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses 855system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses 856system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses 857system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses 858system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses |
| 842system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62314.748201 # average ReadReq miss latency 843system.cpu.dcache.ReadReq_avg_miss_latency::total 62314.748201 # average ReadReq miss latency | 859system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency 860system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency |
| 844system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency 845system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency | 861system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency 862system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency |
| 846system.cpu.dcache.demand_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency 847system.cpu.dcache.demand_avg_miss_latency::total 63421.485401 # average overall miss latency 848system.cpu.dcache.overall_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency 849system.cpu.dcache.overall_avg_miss_latency::total 63421.485401 # average overall miss latency | 863system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency 864system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency 865system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency 866system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency |
| 850system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked 851system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 852system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked 853system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 854system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked 855system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 856system.cpu.dcache.fast_writes 0 # number of fast writes performed 857system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 866system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 867system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 868system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 869system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 870system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 871system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 872system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 873system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses | 867system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked 868system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 869system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked 870system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 871system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked 872system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 873system.cpu.dcache.fast_writes 0 # number of fast writes performed 874system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 883system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 884system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 885system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 886system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 887system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses 888system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses 889system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses 890system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses |
| 874system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4732000 # number of ReadReq MSHR miss cycles 875system.cpu.dcache.ReadReq_mshr_miss_latency::total 4732000 # number of ReadReq MSHR miss cycles | 891system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles 892system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles |
| 876system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles 877system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles | 893system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles 894system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles |
| 878system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10967500 # number of demand (read+write) MSHR miss cycles 879system.cpu.dcache.demand_mshr_miss_latency::total 10967500 # number of demand (read+write) MSHR miss cycles 880system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10967500 # number of overall MSHR miss cycles 881system.cpu.dcache.overall_mshr_miss_latency::total 10967500 # number of overall MSHR miss cycles | 895system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles 896system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles 897system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles 898system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles |
| 882system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses 883system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses 884system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 885system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses 886system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses 887system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses 888system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses 889system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses | 899system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses 900system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses 901system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 902system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses 903system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses 904system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses 905system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses 906system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses |
| 890system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72800 # average ReadReq mshr miss latency 891system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72800 # average ReadReq mshr miss latency | 907system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency 908system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency |
| 892system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency 893system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency | 909system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency 910system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency |
| 894system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency 895system.cpu.dcache.demand_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency 896system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency 897system.cpu.dcache.overall_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency | 911system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency 912system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency 913system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency 914system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency |
| 898system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 899 900---------- End Simulation Statistics ---------- | 915system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 916 917---------- End Simulation Statistics ---------- |