| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated |
| 4sim_ticks 26743500 # Number of ticks simulated 5final_tick 26743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 26706500 # Number of ticks simulated 5final_tick 26706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 53060 # Simulator instruction rate (inst/s) 8host_op_rate 53057 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 98286640 # Simulator tick rate (ticks/s) 10host_mem_usage 272776 # Number of bytes of host memory used 11host_seconds 0.27 # Real time elapsed on the host | 7host_inst_rate 64712 # Simulator instruction rate (inst/s) 8host_op_rate 64708 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 119701044 # Simulator tick rate (ticks/s) 10host_mem_usage 272800 # Number of bytes of host memory used 11host_seconds 0.22 # Real time elapsed on the host |
| 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30848 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 482 # Number of read requests responded to by this memory | 12sim_insts 14436 # Number of instructions simulated 13sim_ops 14436 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30848 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 482 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 801690130 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 351786415 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1153476546 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 801690130 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 801690130 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 801690130 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 351786415 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1153476546 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 802800816 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 352273791 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1155074607 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 802800816 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 802800816 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 802800816 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 352273791 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1155074607 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 482 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 482 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 26582500 # Total gap between requests | 78system.physmem.totGap 26545500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 482 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 482 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 283 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 140 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 95system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 448 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 298.774659 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 377.002918 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 5 12.20% 12.20% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 12 29.27% 41.46% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 7 17.07% 58.54% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 2 4.88% 63.41% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 2 4.88% 68.29% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 2.44% 70.73% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 4.88% 75.61% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 10 24.39% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation 202system.physmem.totQLat 2269000 # Total ticks spent queuing 203system.physmem.totMemAccLat 11609000 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 70 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 403.200000 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 265.551535 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 347.027861 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 12 17.14% 17.14% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 22 31.43% 48.57% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 9 12.86% 61.43% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 3 4.29% 65.71% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 5.71% 71.43% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 4.29% 75.71% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 6 8.57% 84.29% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 1.43% 85.71% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 10 14.29% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 70 # Bytes accessed per row activation 203system.physmem.totQLat 2602000 # Total ticks spent queuing 204system.physmem.totMemAccLat 11639500 # Total ticks spent from burst creation until serviced by the DRAM |
| 204system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers |
| 205system.physmem.totBankLat 6930000 # Total ticks spent accessing banks 206system.physmem.avgQLat 4707.47 # Average queueing delay per DRAM burst 207system.physmem.avgBankLat 14377.59 # Average bank access latency per DRAM burst | 206system.physmem.avgQLat 5398.34 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 24085.06 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1153.48 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 24148.34 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1155.07 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 1153.48 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1155.07 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 9.01 # Data bus utilization in percentage 216system.physmem.busUtilRead 9.01 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 9.02 # Data bus utilization in percentage 215system.physmem.busUtilRead 9.02 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 403 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.51 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 403 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 83.61 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 55150.41 # Average gap between requests | 223system.physmem.avgGap 55073.65 # Average gap between requests |
| 225system.physmem.pageHitRate 83.61 # Row buffer hit rate, read and write combined | 224system.physmem.pageHitRate 83.61 # Row buffer hit rate, read and write combined |
| 226system.physmem.prechargeAllPercent 5.72 # Percentage of time for which DRAM has all the banks in precharge state 227system.membus.throughput 1153476546 # Throughput (bytes/s) | 225system.physmem.memoryStateTime::IDLE 1553250 # Time in different power states 226system.physmem.memoryStateTime::REF 780000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 21299250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 1155074607 # Throughput (bytes/s) |
| 228system.membus.trans_dist::ReadReq 399 # Transaction distribution 229system.membus.trans_dist::ReadResp 399 # Transaction distribution 230system.membus.trans_dist::ReadExReq 83 # Transaction distribution 231system.membus.trans_dist::ReadExResp 83 # Transaction distribution 232system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes) 233system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 234system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes) 235system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 236system.membus.data_through_bus 30848 # Total data (bytes) 237system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 231system.membus.trans_dist::ReadReq 399 # Transaction distribution 232system.membus.trans_dist::ReadResp 399 # Transaction distribution 233system.membus.trans_dist::ReadExReq 83 # Transaction distribution 234system.membus.trans_dist::ReadExResp 83 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 964 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30848 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 30848 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 238system.membus.reqLayer0.occupancy 607500 # Layer occupancy (ticks) | 241system.membus.reqLayer0.occupancy 606500 # Layer occupancy (ticks) |
| 239system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) | 242system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) |
| 240system.membus.respLayer1.occupancy 4495000 # Layer occupancy (ticks) | 243system.membus.respLayer1.occupancy 4499500 # Layer occupancy (ticks) |
| 241system.membus.respLayer1.utilization 16.8 # Layer utilization (%) 242system.cpu_clk_domain.clock 500 # Clock period in ticks | 244system.membus.respLayer1.utilization 16.8 # Layer utilization (%) 245system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 243system.cpu.branchPred.lookups 6710 # Number of BP lookups 244system.cpu.branchPred.condPredicted 4453 # Number of conditional branches predicted | 246system.cpu.branchPred.lookups 6716 # Number of BP lookups 247system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted |
| 245system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect | 248system.cpu.branchPred.condIncorrect 1076 # Number of conditional branches incorrect |
| 246system.cpu.branchPred.BTBLookups 5017 # Number of BTB lookups | 249system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups |
| 247system.cpu.branchPred.BTBHits 2432 # Number of BTB hits 248system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 250system.cpu.branchPred.BTBHits 2432 # Number of BTB hits 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 249system.cpu.branchPred.BTBHitPct 48.475184 # BTB Hit Percentage | 252system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage |
| 250system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. 251system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. 252system.cpu.workload.num_syscalls 18 # Number of system calls | 253system.cpu.branchPred.usedRAS 444 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions. 255system.cpu.workload.num_syscalls 18 # Number of system calls |
| 253system.cpu.numCycles 53488 # number of cpu cycles simulated | 256system.cpu.numCycles 53414 # number of cpu cycles simulated |
| 254system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 255system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 257system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 258system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 256system.cpu.fetch.icacheStallCycles 12425 # Number of cycles fetch is stalled on an Icache miss 257system.cpu.fetch.Insts 31097 # Number of instructions fetch has processed 258system.cpu.fetch.Branches 6710 # Number of branches that fetch encountered | 259system.cpu.fetch.icacheStallCycles 12411 # Number of cycles fetch is stalled on an Icache miss 260system.cpu.fetch.Insts 31121 # Number of instructions fetch has processed 261system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered |
| 259system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken | 262system.cpu.fetch.predictedBranches 2876 # Number of branches that fetch has predicted taken |
| 260system.cpu.fetch.Cycles 9129 # Number of cycles fetch has run and was not squashing or blocked 261system.cpu.fetch.SquashCycles 3043 # Number of cycles fetch has spent squashing 262system.cpu.fetch.BlockedCycles 9229 # Number of cycles fetch has spent blocked | 263system.cpu.fetch.Cycles 9132 # Number of cycles fetch has run and was not squashing or blocked 264system.cpu.fetch.SquashCycles 3044 # Number of cycles fetch has spent squashing 265system.cpu.fetch.BlockedCycles 9191 # Number of cycles fetch has spent blocked |
| 263system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 264system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps | 266system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 267system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps |
| 265system.cpu.fetch.CacheLines 5378 # Number of cache lines fetched | 268system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched |
| 266system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed | 269system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed |
| 267system.cpu.fetch.rateDist::samples 33579 # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::mean 0.926085 # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::stdev 2.119056 # Number of instructions fetched each cycle (Total) | 270system.cpu.fetch.rateDist::samples 33531 # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::mean 0.928126 # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::stdev 2.121319 # Number of instructions fetched each cycle (Total) |
| 270system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 273system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 271system.cpu.fetch.rateDist::0 24450 72.81% 72.81% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::1 4510 13.43% 86.24% # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::2 474 1.41% 87.66% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::3 392 1.17% 88.82% # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::4 680 2.03% 90.85% # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::5 706 2.10% 92.95% # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::6 235 0.70% 93.65% # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::7 253 0.75% 94.40% # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::8 1879 5.60% 100.00% # Number of instructions fetched each cycle (Total) | 274system.cpu.fetch.rateDist::0 24399 72.77% 72.77% # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::1 4510 13.45% 86.22% # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::2 474 1.41% 87.63% # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::3 392 1.17% 88.80% # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::4 680 2.03% 90.83% # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::5 706 2.11% 92.93% # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::6 235 0.70% 93.63% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::7 253 0.75% 94.39% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::8 1882 5.61% 100.00% # Number of instructions fetched each cycle (Total) |
| 280system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 283system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 283system.cpu.fetch.rateDist::total 33579 # Number of instructions fetched each cycle (Total) 284system.cpu.fetch.branchRate 0.125449 # Number of branch fetches per cycle 285system.cpu.fetch.rate 0.581383 # Number of inst fetches per cycle 286system.cpu.decode.IdleCycles 12934 # Number of cycles decode is idle 287system.cpu.decode.BlockedCycles 10235 # Number of cycles decode is blocked 288system.cpu.decode.RunCycles 8342 # Number of cycles decode is running 289system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking 290system.cpu.decode.SquashCycles 1871 # Number of cycles decode is squashing 291system.cpu.decode.DecodedInsts 28992 # Number of instructions handled by decode 292system.cpu.rename.SquashCycles 1871 # Number of cycles rename is squashing 293system.cpu.rename.IdleCycles 13577 # Number of cycles rename is idle 294system.cpu.rename.BlockCycles 435 # Number of cycles rename is blocking 295system.cpu.rename.serializeStallCycles 9274 # count of cycles rename stalled for serializing inst 296system.cpu.rename.RunCycles 7946 # Number of cycles rename is running 297system.cpu.rename.UnblockCycles 476 # Number of cycles rename is unblocking 298system.cpu.rename.RenamedInsts 26641 # Number of instructions processed by rename | 286system.cpu.fetch.rateDist::total 33531 # Number of instructions fetched each cycle (Total) 287system.cpu.fetch.branchRate 0.125735 # Number of branch fetches per cycle 288system.cpu.fetch.rate 0.582638 # Number of inst fetches per cycle 289system.cpu.decode.IdleCycles 12927 # Number of cycles decode is idle 290system.cpu.decode.BlockedCycles 10191 # Number of cycles decode is blocked 291system.cpu.decode.RunCycles 8340 # Number of cycles decode is running 292system.cpu.decode.UnblockCycles 201 # Number of cycles decode is unblocking 293system.cpu.decode.SquashCycles 1872 # Number of cycles decode is squashing 294system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode 295system.cpu.rename.SquashCycles 1872 # Number of cycles rename is squashing 296system.cpu.rename.IdleCycles 13569 # Number of cycles rename is idle 297system.cpu.rename.BlockCycles 456 # Number of cycles rename is blocking 298system.cpu.rename.serializeStallCycles 9204 # count of cycles rename stalled for serializing inst 299system.cpu.rename.RunCycles 7948 # Number of cycles rename is running 300system.cpu.rename.UnblockCycles 482 # Number of cycles rename is unblocking 301system.cpu.rename.RenamedInsts 26657 # Number of instructions processed by rename |
| 299system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full | 302system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full |
| 300system.cpu.rename.LSQFullEvents 148 # Number of times rename has blocked due to LSQ full 301system.cpu.rename.RenamedOperands 23939 # Number of destination operands rename has renamed 302system.cpu.rename.RenameLookups 49429 # Number of register rename lookups that rename has made 303system.cpu.rename.int_rename_lookups 40899 # Number of integer rename lookups | 303system.cpu.rename.LSQFullEvents 152 # Number of times rename has blocked due to LSQ full 304system.cpu.rename.RenamedOperands 23951 # Number of destination operands rename has renamed 305system.cpu.rename.RenameLookups 49456 # Number of register rename lookups that rename has made 306system.cpu.rename.int_rename_lookups 40918 # Number of integer rename lookups |
| 304system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed | 307system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed |
| 305system.cpu.rename.UndoneMaps 10120 # Number of HB maps that are undone due to squashing | 308system.cpu.rename.UndoneMaps 10132 # Number of HB maps that are undone due to squashing |
| 306system.cpu.rename.serializingInsts 691 # count of serializing insts renamed 307system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed | 309system.cpu.rename.serializingInsts 691 # count of serializing insts renamed 310system.cpu.rename.tempSerializingInsts 694 # count of temporary serializing insts renamed |
| 308system.cpu.rename.skidInsts 2745 # count of insts added to the skid buffer 309system.cpu.memDep0.insertedLoads 3528 # Number of loads inserted to the mem dependence unit. 310system.cpu.memDep0.insertedStores 2282 # Number of stores inserted to the mem dependence unit. | 311system.cpu.rename.skidInsts 2747 # count of insts added to the skid buffer 312system.cpu.memDep0.insertedLoads 3529 # Number of loads inserted to the mem dependence unit. 313system.cpu.memDep0.insertedStores 2285 # Number of stores inserted to the mem dependence unit. |
| 311system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 312system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 314system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 315system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 313system.cpu.iq.iqInstsAdded 22511 # Number of instructions added to the IQ (excludes non-spec) | 316system.cpu.iq.iqInstsAdded 22517 # Number of instructions added to the IQ (excludes non-spec) |
| 314system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ | 317system.cpu.iq.iqNonSpecInstsAdded 655 # Number of non-speculative instructions added to the IQ |
| 315system.cpu.iq.iqInstsIssued 21117 # Number of instructions issued | 318system.cpu.iq.iqInstsIssued 21121 # Number of instructions issued |
| 316system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued | 319system.cpu.iq.iqSquashedInstsIssued 97 # Number of squashed instructions issued |
| 317system.cpu.iq.iqSquashedInstsExamined 7892 # Number of squashed instructions iterated over during squash; mainly for profiling 318system.cpu.iq.iqSquashedOperandsExamined 5484 # Number of squashed operands that are examined and possibly removed from graph | 320system.cpu.iq.iqSquashedInstsExamined 7903 # Number of squashed instructions iterated over during squash; mainly for profiling 321system.cpu.iq.iqSquashedOperandsExamined 5498 # Number of squashed operands that are examined and possibly removed from graph |
| 319system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed | 322system.cpu.iq.iqSquashedNonSpecRemoved 180 # Number of squashed non-spec instructions that were removed |
| 320system.cpu.iq.issued_per_cycle::samples 33579 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::mean 0.628875 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::stdev 1.255627 # Number of insts issued each cycle | 323system.cpu.iq.issued_per_cycle::samples 33531 # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::mean 0.629895 # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::stdev 1.256216 # Number of insts issued each cycle |
| 323system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 326system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 324system.cpu.iq.issued_per_cycle::0 24339 72.48% 72.48% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::1 3553 10.58% 83.06% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::2 2322 6.92% 89.98% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::3 1704 5.07% 95.05% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::4 887 2.64% 97.69% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::5 469 1.40% 99.09% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::6 240 0.71% 99.81% # Number of insts issued each cycle | 327system.cpu.iq.issued_per_cycle::0 24281 72.41% 72.41% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::1 3570 10.65% 83.06% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::2 2315 6.90% 89.96% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::3 1704 5.08% 95.05% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::4 886 2.64% 97.69% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::5 470 1.40% 99.09% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::6 240 0.72% 99.81% # Number of insts issued each cycle |
| 331system.cpu.iq.issued_per_cycle::7 45 0.13% 99.94% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 334system.cpu.iq.issued_per_cycle::7 45 0.13% 99.94% # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::8 20 0.06% 100.00% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 336system.cpu.iq.issued_per_cycle::total 33579 # Number of insts issued each cycle | 339system.cpu.iq.issued_per_cycle::total 33531 # Number of insts issued each cycle |
| 337system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 338system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available 339system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available 340system.cpu.iq.fu_full::IntDiv 0 0.00% 31.29% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.29% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.29% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.29% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatMult 0 0.00% 31.29% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 364system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.29% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.29% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.29% # attempts to use FU when none available 367system.cpu.iq.fu_full::MemRead 26 17.69% 48.98% # attempts to use FU when none available 368system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # attempts to use FU when none available 369system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 370system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 371system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 340system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 341system.cpu.iq.fu_full::IntAlu 46 31.29% 31.29% # attempts to use FU when none available 342system.cpu.iq.fu_full::IntMult 0 0.00% 31.29% # attempts to use FU when none available 343system.cpu.iq.fu_full::IntDiv 0 0.00% 31.29% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.29% # attempts to use FU when none available 345system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.29% # attempts to use FU when none available 346system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.29% # attempts to use FU when none available 347system.cpu.iq.fu_full::FloatMult 0 0.00% 31.29% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 367system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.29% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.29% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.29% # attempts to use FU when none available 370system.cpu.iq.fu_full::MemRead 26 17.69% 48.98% # attempts to use FU when none available 371system.cpu.iq.fu_full::MemWrite 75 51.02% 100.00% # attempts to use FU when none available 372system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 373system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 374system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 372system.cpu.iq.FU_type_0::IntAlu 15648 74.10% 74.10% # Type of FU issued | 375system.cpu.iq.FU_type_0::IntAlu 15650 74.10% 74.10% # Type of FU issued |
| 373system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued 374system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued 375system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued 376system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.10% # Type of FU issued 377system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.10% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.10% # Type of FU issued 379system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.10% # Type of FU issued 380system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.10% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 393system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.10% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.10% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.10% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.10% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued | 376system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.10% # Type of FU issued 377system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.10% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.10% # Type of FU issued 379system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.10% # Type of FU issued 380system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.10% # Type of FU issued 381system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.10% # Type of FU issued 382system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.10% # Type of FU issued 383system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.10% # Type of FU issued --- 12 unchanged lines hidden (view full) --- 396system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.10% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.10% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.10% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.10% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.10% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.10% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.10% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.10% # Type of FU issued |
| 401system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.02% # Type of FU issued 402system.cpu.iq.FU_type_0::MemWrite 2107 9.98% 100.00% # Type of FU issued | 404system.cpu.iq.FU_type_0::MemRead 3362 15.92% 90.01% # Type of FU issued 405system.cpu.iq.FU_type_0::MemWrite 2109 9.99% 100.00% # Type of FU issued |
| 403system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 404system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 406system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 407system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 405system.cpu.iq.FU_type_0::total 21117 # Type of FU issued 406system.cpu.iq.rate 0.394799 # Inst issue rate | 408system.cpu.iq.FU_type_0::total 21121 # Type of FU issued 409system.cpu.iq.rate 0.395421 # Inst issue rate |
| 407system.cpu.iq.fu_busy_cnt 147 # FU busy when requested | 410system.cpu.iq.fu_busy_cnt 147 # FU busy when requested |
| 408system.cpu.iq.fu_busy_rate 0.006961 # FU busy rate (busy events/executed inst) 409system.cpu.iq.int_inst_queue_reads 76057 # Number of integer instruction queue reads 410system.cpu.iq.int_inst_queue_writes 31084 # Number of integer instruction queue writes | 411system.cpu.iq.fu_busy_rate 0.006960 # FU busy rate (busy events/executed inst) 412system.cpu.iq.int_inst_queue_reads 76017 # Number of integer instruction queue reads 413system.cpu.iq.int_inst_queue_writes 31101 # Number of integer instruction queue writes |
| 411system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses 412system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 413system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 414system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses | 414system.cpu.iq.int_inst_queue_wakeup_accesses 19522 # Number of integer instruction queue wakeup accesses 415system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads 416system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes 417system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses |
| 415system.cpu.iq.int_alu_accesses 21264 # Number of integer alu accesses | 418system.cpu.iq.int_alu_accesses 21268 # Number of integer alu accesses |
| 416system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 417system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores 418system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 419system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses 420system.cpu.iew.lsq.thread0.forwLoads 29 # Number of loads that had data forwarded from stores 421system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 419system.cpu.iew.lsq.thread0.squashedLoads 1303 # Number of loads squashed | 422system.cpu.iew.lsq.thread0.squashedLoads 1304 # Number of loads squashed |
| 420system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 421system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations | 423system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 424system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations |
| 422system.cpu.iew.lsq.thread0.squashedStores 834 # Number of stores squashed | 425system.cpu.iew.lsq.thread0.squashedStores 837 # Number of stores squashed |
| 423system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 424system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 425system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled | 426system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 427system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 428system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled |
| 426system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked | 429system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked |
| 427system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 430system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 428system.cpu.iew.iewSquashCycles 1871 # Number of cycles IEW is squashing 429system.cpu.iew.iewBlockCycles 286 # Number of cycles IEW is blocking 430system.cpu.iew.iewUnblockCycles 14 # Number of cycles IEW is unblocking 431system.cpu.iew.iewDispatchedInsts 24299 # Number of instructions dispatched to IQ 432system.cpu.iew.iewDispSquashedInsts 399 # Number of squashed instructions skipped by dispatch 433system.cpu.iew.iewDispLoadInsts 3528 # Number of dispatched load instructions 434system.cpu.iew.iewDispStoreInsts 2282 # Number of dispatched store instructions | 431system.cpu.iew.iewSquashCycles 1872 # Number of cycles IEW is squashing 432system.cpu.iew.iewBlockCycles 300 # Number of cycles IEW is blocking 433system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 434system.cpu.iew.iewDispatchedInsts 24306 # Number of instructions dispatched to IQ 435system.cpu.iew.iewDispSquashedInsts 403 # Number of squashed instructions skipped by dispatch 436system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions 437system.cpu.iew.iewDispStoreInsts 2285 # Number of dispatched store instructions |
| 435system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions 436system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 437system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 438system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations 439system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly 440system.cpu.iew.predictedNotTakenIncorrect 946 # Number of branches that were predicted not taken incorrectly 441system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute 442system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions 443system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed | 438system.cpu.iew.iewDispNonSpecInsts 655 # Number of dispatched non-speculative instructions 439system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 440system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 441system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations 442system.cpu.iew.predictedTakenIncorrect 264 # Number of branches that were predicted taken incorrectly 443system.cpu.iew.predictedNotTakenIncorrect 946 # Number of branches that were predicted not taken incorrectly 444system.cpu.iew.branchMispredicts 1210 # Number of branch mispredicts detected at execute 445system.cpu.iew.iewExecutedInsts 20074 # Number of executed instructions 446system.cpu.iew.iewExecLoadInsts 3202 # Number of load instructions executed |
| 444system.cpu.iew.iewExecSquashedInsts 1043 # Number of squashed instructions skipped in execute | 447system.cpu.iew.iewExecSquashedInsts 1047 # Number of squashed instructions skipped in execute |
| 445system.cpu.iew.exec_swp 0 # number of swp insts executed | 448system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 446system.cpu.iew.exec_nop 1133 # number of nop insts executed | 449system.cpu.iew.exec_nop 1134 # number of nop insts executed |
| 447system.cpu.iew.exec_refs 5224 # number of memory reference insts executed 448system.cpu.iew.exec_branches 4239 # Number of branches executed 449system.cpu.iew.exec_stores 2022 # Number of stores executed | 450system.cpu.iew.exec_refs 5224 # number of memory reference insts executed 451system.cpu.iew.exec_branches 4239 # Number of branches executed 452system.cpu.iew.exec_stores 2022 # Number of stores executed |
| 450system.cpu.iew.exec_rate 0.375299 # Inst execution rate | 453system.cpu.iew.exec_rate 0.375819 # Inst execution rate |
| 451system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit 452system.cpu.iew.wb_count 19522 # cumulative count of insts written-back | 454system.cpu.iew.wb_sent 19749 # cumulative count of insts sent to commit 455system.cpu.iew.wb_count 19522 # cumulative count of insts written-back |
| 453system.cpu.iew.wb_producers 9122 # num instructions producing a value 454system.cpu.iew.wb_consumers 11233 # num instructions consuming a value | 456system.cpu.iew.wb_producers 9116 # num instructions producing a value 457system.cpu.iew.wb_consumers 11226 # num instructions consuming a value |
| 455system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 458system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 456system.cpu.iew.wb_rate 0.364979 # insts written-back per cycle 457system.cpu.iew.wb_fanout 0.812072 # average fanout of values written-back | 459system.cpu.iew.wb_rate 0.365485 # insts written-back per cycle 460system.cpu.iew.wb_fanout 0.812043 # average fanout of values written-back |
| 458system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 461system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 459system.cpu.commit.commitSquashedInsts 9039 # The number of squashed insts skipped by commit | 462system.cpu.commit.commitSquashedInsts 9046 # The number of squashed insts skipped by commit |
| 460system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 461system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted | 463system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards 464system.cpu.commit.branchMispredicts 1076 # The number of times a branch was mispredicted |
| 462system.cpu.commit.committed_per_cycle::samples 31708 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::mean 0.478176 # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::stdev 1.176132 # Number of insts commited each cycle | 465system.cpu.commit.committed_per_cycle::samples 31659 # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::mean 0.478916 # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::stdev 1.176623 # Number of insts commited each cycle |
| 465system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 468system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 466system.cpu.commit.committed_per_cycle::0 24394 76.93% 76.93% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::1 4067 12.83% 89.76% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::2 1357 4.28% 94.04% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::3 765 2.41% 96.45% # Number of insts commited each cycle | 469system.cpu.commit.committed_per_cycle::0 24337 76.87% 76.87% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::1 4081 12.89% 89.76% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::2 1353 4.27% 94.04% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::3 763 2.41% 96.45% # Number of insts commited each cycle |
| 470system.cpu.commit.committed_per_cycle::4 348 1.10% 97.55% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::5 270 0.85% 98.40% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::6 322 1.02% 99.42% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::7 68 0.21% 99.63% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 473system.cpu.commit.committed_per_cycle::4 348 1.10% 97.55% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::5 270 0.85% 98.40% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::6 322 1.02% 99.42% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::7 68 0.21% 99.63% # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::8 117 0.37% 100.00% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 478system.cpu.commit.committed_per_cycle::total 31708 # Number of insts commited each cycle | 481system.cpu.commit.committed_per_cycle::total 31659 # Number of insts commited each cycle |
| 479system.cpu.commit.committedInsts 15162 # Number of instructions committed 480system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 481system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 482system.cpu.commit.refs 3673 # Number of memory references committed 483system.cpu.commit.loads 2225 # Number of loads committed 484system.cpu.commit.membars 0 # Number of memory barriers committed 485system.cpu.commit.branches 3358 # Number of branches committed 486system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 487system.cpu.commit.int_insts 12174 # Number of committed integer instructions. 488system.cpu.commit.function_calls 187 # Number of function calls committed. | 482system.cpu.commit.committedInsts 15162 # Number of instructions committed 483system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed 484system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 485system.cpu.commit.refs 3673 # Number of memory references committed 486system.cpu.commit.loads 2225 # Number of loads committed 487system.cpu.commit.membars 0 # Number of memory barriers committed 488system.cpu.commit.branches 3358 # Number of branches committed 489system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 490system.cpu.commit.int_insts 12174 # Number of committed integer instructions. 491system.cpu.commit.function_calls 187 # Number of function calls committed. |
| 492system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction 493system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction 494system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction 495system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction 496system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction 497system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction 498system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction 499system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction 500system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction 501system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction 502system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction 503system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction 504system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction 505system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction 506system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction 507system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction 508system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction 509system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction 510system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction 511system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction 512system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction 513system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction 514system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction 515system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction 516system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction 517system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction 518system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction 519system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction 520system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction 521system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction 522system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction 523system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction 524system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 525system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 526system.cpu.commit.op_class_0::total 15162 # Class of committed instruction |
|
| 489system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached 490system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 527system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached 528system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 491system.cpu.rob.rob_reads 54969 # The number of ROB reads 492system.cpu.rob.rob_writes 50281 # The number of ROB writes | 529system.cpu.rob.rob_reads 54927 # The number of ROB reads 530system.cpu.rob.rob_writes 50296 # The number of ROB writes |
| 493system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself | 531system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 494system.cpu.idleCycles 19909 # Total number of cycles that the CPU has spent unscheduled due to idling | 532system.cpu.idleCycles 19883 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 495system.cpu.committedInsts 14436 # Number of Instructions Simulated 496system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 497system.cpu.committedInsts_total 14436 # Number of Instructions Simulated | 533system.cpu.committedInsts 14436 # Number of Instructions Simulated 534system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated 535system.cpu.committedInsts_total 14436 # Number of Instructions Simulated |
| 498system.cpu.cpi 3.705181 # CPI: Cycles Per Instruction 499system.cpu.cpi_total 3.705181 # CPI: Total CPI of All Threads 500system.cpu.ipc 0.269892 # IPC: Instructions Per Cycle 501system.cpu.ipc_total 0.269892 # IPC: Total IPC of All Threads | 536system.cpu.cpi 3.700055 # CPI: Cycles Per Instruction 537system.cpu.cpi_total 3.700055 # CPI: Total CPI of All Threads 538system.cpu.ipc 0.270266 # IPC: Instructions Per Cycle 539system.cpu.ipc_total 0.270266 # IPC: Total IPC of All Threads |
| 502system.cpu.int_regfile_reads 32043 # number of integer regfile reads 503system.cpu.int_regfile_writes 17841 # number of integer regfile writes 504system.cpu.misc_regfile_reads 6919 # number of misc regfile reads 505system.cpu.misc_regfile_writes 569 # number of misc regfile writes | 540system.cpu.int_regfile_reads 32043 # number of integer regfile reads 541system.cpu.int_regfile_writes 17841 # number of integer regfile writes 542system.cpu.misc_regfile_reads 6919 # number of misc regfile reads 543system.cpu.misc_regfile_writes 569 # number of misc regfile writes |
| 506system.cpu.toL2Bus.throughput 1158262755 # Throughput (bytes/s) | 544system.cpu.toL2Bus.throughput 1159867448 # Throughput (bytes/s) |
| 507system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution 508system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 509system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 510system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 511system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes) 512system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 513system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes) 514system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes) 515system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 516system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) 517system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) 518system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 519system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) 520system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) | 545system.cpu.toL2Bus.trans_dist::ReadReq 401 # Transaction distribution 546system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 547system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution 548system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution 549system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 674 # Packet count per connected master and slave (bytes) 550system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) 551system.cpu.toL2Bus.pkt_count::total 968 # Packet count per connected master and slave (bytes) 552system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21568 # Cumulative packet size per connected master and slave (bytes) 553system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) 554system.cpu.toL2Bus.tot_pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) 555system.cpu.toL2Bus.data_through_bus 30976 # Total data (bytes) 556system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 557system.cpu.toL2Bus.reqLayer0.occupancy 242000 # Layer occupancy (ticks) 558system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) |
| 521system.cpu.toL2Bus.respLayer0.occupancy 562250 # Layer occupancy (ticks) | 559system.cpu.toL2Bus.respLayer0.occupancy 564000 # Layer occupancy (ticks) |
| 522system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) | 560system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) |
| 523system.cpu.toL2Bus.respLayer1.occupancy 233750 # Layer occupancy (ticks) | 561system.cpu.toL2Bus.respLayer1.occupancy 235000 # Layer occupancy (ticks) |
| 524system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 525system.cpu.icache.tags.replacements 0 # number of replacements | 562system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 563system.cpu.icache.tags.replacements 0 # number of replacements |
| 526system.cpu.icache.tags.tagsinuse 187.339200 # Cycle average of tags in use 527system.cpu.icache.tags.total_refs 4870 # Total number of references to valid blocks. | 564system.cpu.icache.tags.tagsinuse 187.422918 # Cycle average of tags in use 565system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks. |
| 528system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. | 566system.cpu.icache.tags.sampled_refs 337 # Sample count of references to valid blocks. |
| 529system.cpu.icache.tags.avg_refs 14.451039 # Average number of references to valid blocks. | 567system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks. |
| 530system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 568system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 531system.cpu.icache.tags.occ_blocks::cpu.inst 187.339200 # Average occupied blocks per requestor 532system.cpu.icache.tags.occ_percent::cpu.inst 0.091474 # Average percentage of cache occupancy 533system.cpu.icache.tags.occ_percent::total 0.091474 # Average percentage of cache occupancy | 569system.cpu.icache.tags.occ_blocks::cpu.inst 187.422918 # Average occupied blocks per requestor 570system.cpu.icache.tags.occ_percent::cpu.inst 0.091515 # Average percentage of cache occupancy 571system.cpu.icache.tags.occ_percent::total 0.091515 # Average percentage of cache occupancy |
| 534system.cpu.icache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id 535system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 536system.cpu.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id 537system.cpu.icache.tags.occ_task_id_percent::1024 0.164551 # Percentage of cache occupancy per task id | 572system.cpu.icache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id 573system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 574system.cpu.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id 575system.cpu.icache.tags.occ_task_id_percent::1024 0.164551 # Percentage of cache occupancy per task id |
| 538system.cpu.icache.tags.tag_accesses 11093 # Number of tag accesses 539system.cpu.icache.tags.data_accesses 11093 # Number of data accesses 540system.cpu.icache.ReadReq_hits::cpu.inst 4870 # number of ReadReq hits 541system.cpu.icache.ReadReq_hits::total 4870 # number of ReadReq hits 542system.cpu.icache.demand_hits::cpu.inst 4870 # number of demand (read+write) hits 543system.cpu.icache.demand_hits::total 4870 # number of demand (read+write) hits 544system.cpu.icache.overall_hits::cpu.inst 4870 # number of overall hits 545system.cpu.icache.overall_hits::total 4870 # number of overall hits 546system.cpu.icache.ReadReq_misses::cpu.inst 508 # number of ReadReq misses 547system.cpu.icache.ReadReq_misses::total 508 # number of ReadReq misses 548system.cpu.icache.demand_misses::cpu.inst 508 # number of demand (read+write) misses 549system.cpu.icache.demand_misses::total 508 # number of demand (read+write) misses 550system.cpu.icache.overall_misses::cpu.inst 508 # number of overall misses 551system.cpu.icache.overall_misses::total 508 # number of overall misses 552system.cpu.icache.ReadReq_miss_latency::cpu.inst 31654500 # number of ReadReq miss cycles 553system.cpu.icache.ReadReq_miss_latency::total 31654500 # number of ReadReq miss cycles 554system.cpu.icache.demand_miss_latency::cpu.inst 31654500 # number of demand (read+write) miss cycles 555system.cpu.icache.demand_miss_latency::total 31654500 # number of demand (read+write) miss cycles 556system.cpu.icache.overall_miss_latency::cpu.inst 31654500 # number of overall miss cycles 557system.cpu.icache.overall_miss_latency::total 31654500 # number of overall miss cycles 558system.cpu.icache.ReadReq_accesses::cpu.inst 5378 # number of ReadReq accesses(hits+misses) 559system.cpu.icache.ReadReq_accesses::total 5378 # number of ReadReq accesses(hits+misses) 560system.cpu.icache.demand_accesses::cpu.inst 5378 # number of demand (read+write) accesses 561system.cpu.icache.demand_accesses::total 5378 # number of demand (read+write) accesses 562system.cpu.icache.overall_accesses::cpu.inst 5378 # number of overall (read+write) accesses 563system.cpu.icache.overall_accesses::total 5378 # number of overall (read+write) accesses 564system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094459 # miss rate for ReadReq accesses 565system.cpu.icache.ReadReq_miss_rate::total 0.094459 # miss rate for ReadReq accesses 566system.cpu.icache.demand_miss_rate::cpu.inst 0.094459 # miss rate for demand accesses 567system.cpu.icache.demand_miss_rate::total 0.094459 # miss rate for demand accesses 568system.cpu.icache.overall_miss_rate::cpu.inst 0.094459 # miss rate for overall accesses 569system.cpu.icache.overall_miss_rate::total 0.094459 # miss rate for overall accesses 570system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62312.007874 # average ReadReq miss latency 571system.cpu.icache.ReadReq_avg_miss_latency::total 62312.007874 # average ReadReq miss latency 572system.cpu.icache.demand_avg_miss_latency::cpu.inst 62312.007874 # average overall miss latency 573system.cpu.icache.demand_avg_miss_latency::total 62312.007874 # average overall miss latency 574system.cpu.icache.overall_avg_miss_latency::cpu.inst 62312.007874 # average overall miss latency 575system.cpu.icache.overall_avg_miss_latency::total 62312.007874 # average overall miss latency | 576system.cpu.icache.tags.tag_accesses 11095 # Number of tag accesses 577system.cpu.icache.tags.data_accesses 11095 # Number of data accesses 578system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits 579system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits 580system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits 581system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits 582system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits 583system.cpu.icache.overall_hits::total 4872 # number of overall hits 584system.cpu.icache.ReadReq_misses::cpu.inst 507 # number of ReadReq misses 585system.cpu.icache.ReadReq_misses::total 507 # number of ReadReq misses 586system.cpu.icache.demand_misses::cpu.inst 507 # number of demand (read+write) misses 587system.cpu.icache.demand_misses::total 507 # number of demand (read+write) misses 588system.cpu.icache.overall_misses::cpu.inst 507 # number of overall misses 589system.cpu.icache.overall_misses::total 507 # number of overall misses 590system.cpu.icache.ReadReq_miss_latency::cpu.inst 31638750 # number of ReadReq miss cycles 591system.cpu.icache.ReadReq_miss_latency::total 31638750 # number of ReadReq miss cycles 592system.cpu.icache.demand_miss_latency::cpu.inst 31638750 # number of demand (read+write) miss cycles 593system.cpu.icache.demand_miss_latency::total 31638750 # number of demand (read+write) miss cycles 594system.cpu.icache.overall_miss_latency::cpu.inst 31638750 # number of overall miss cycles 595system.cpu.icache.overall_miss_latency::total 31638750 # number of overall miss cycles 596system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses) 597system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses) 598system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses 599system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses 600system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses 601system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses 602system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses 603system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses 604system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses 605system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses 606system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses 607system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses 608system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62403.846154 # average ReadReq miss latency 609system.cpu.icache.ReadReq_avg_miss_latency::total 62403.846154 # average ReadReq miss latency 610system.cpu.icache.demand_avg_miss_latency::cpu.inst 62403.846154 # average overall miss latency 611system.cpu.icache.demand_avg_miss_latency::total 62403.846154 # average overall miss latency 612system.cpu.icache.overall_avg_miss_latency::cpu.inst 62403.846154 # average overall miss latency 613system.cpu.icache.overall_avg_miss_latency::total 62403.846154 # average overall miss latency |
| 576system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 577system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 578system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 579system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 580system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 581system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 582system.cpu.icache.fast_writes 0 # number of fast writes performed 583system.cpu.icache.cache_copies 0 # number of cache copies performed | 614system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 615system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 616system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 617system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 618system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 619system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 620system.cpu.icache.fast_writes 0 # number of fast writes performed 621system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 584system.cpu.icache.ReadReq_mshr_hits::cpu.inst 171 # number of ReadReq MSHR hits 585system.cpu.icache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits 586system.cpu.icache.demand_mshr_hits::cpu.inst 171 # number of demand (read+write) MSHR hits 587system.cpu.icache.demand_mshr_hits::total 171 # number of demand (read+write) MSHR hits 588system.cpu.icache.overall_mshr_hits::cpu.inst 171 # number of overall MSHR hits 589system.cpu.icache.overall_mshr_hits::total 171 # number of overall MSHR hits | 622system.cpu.icache.ReadReq_mshr_hits::cpu.inst 170 # number of ReadReq MSHR hits 623system.cpu.icache.ReadReq_mshr_hits::total 170 # number of ReadReq MSHR hits 624system.cpu.icache.demand_mshr_hits::cpu.inst 170 # number of demand (read+write) MSHR hits 625system.cpu.icache.demand_mshr_hits::total 170 # number of demand (read+write) MSHR hits 626system.cpu.icache.overall_mshr_hits::cpu.inst 170 # number of overall MSHR hits 627system.cpu.icache.overall_mshr_hits::total 170 # number of overall MSHR hits |
| 590system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses 591system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses 592system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses 593system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses 594system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses 595system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses | 628system.cpu.icache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses 629system.cpu.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses 630system.cpu.icache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses 631system.cpu.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses 632system.cpu.icache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses 633system.cpu.icache.overall_mshr_misses::total 337 # number of overall MSHR misses |
| 596system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22543250 # number of ReadReq MSHR miss cycles 597system.cpu.icache.ReadReq_mshr_miss_latency::total 22543250 # number of ReadReq MSHR miss cycles 598system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22543250 # number of demand (read+write) MSHR miss cycles 599system.cpu.icache.demand_mshr_miss_latency::total 22543250 # number of demand (read+write) MSHR miss cycles 600system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22543250 # number of overall MSHR miss cycles 601system.cpu.icache.overall_mshr_miss_latency::total 22543250 # number of overall MSHR miss cycles 602system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for ReadReq accesses 603system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062663 # mshr miss rate for ReadReq accesses 604system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for demand accesses 605system.cpu.icache.demand_mshr_miss_rate::total 0.062663 # mshr miss rate for demand accesses 606system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062663 # mshr miss rate for overall accesses 607system.cpu.icache.overall_mshr_miss_rate::total 0.062663 # mshr miss rate for overall accesses 608system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66893.916914 # average ReadReq mshr miss latency 609system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66893.916914 # average ReadReq mshr miss latency 610system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66893.916914 # average overall mshr miss latency 611system.cpu.icache.demand_avg_mshr_miss_latency::total 66893.916914 # average overall mshr miss latency 612system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66893.916914 # average overall mshr miss latency 613system.cpu.icache.overall_avg_mshr_miss_latency::total 66893.916914 # average overall mshr miss latency | 634system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22516000 # number of ReadReq MSHR miss cycles 635system.cpu.icache.ReadReq_mshr_miss_latency::total 22516000 # number of ReadReq MSHR miss cycles 636system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22516000 # number of demand (read+write) MSHR miss cycles 637system.cpu.icache.demand_mshr_miss_latency::total 22516000 # number of demand (read+write) MSHR miss cycles 638system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22516000 # number of overall MSHR miss cycles 639system.cpu.icache.overall_mshr_miss_latency::total 22516000 # number of overall MSHR miss cycles 640system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses 641system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses 642system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses 643system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses 644system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses 645system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses 646system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66813.056380 # average ReadReq mshr miss latency 647system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66813.056380 # average ReadReq mshr miss latency 648system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66813.056380 # average overall mshr miss latency 649system.cpu.icache.demand_avg_mshr_miss_latency::total 66813.056380 # average overall mshr miss latency 650system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66813.056380 # average overall mshr miss latency 651system.cpu.icache.overall_avg_mshr_miss_latency::total 66813.056380 # average overall mshr miss latency |
| 614system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 615system.cpu.l2cache.tags.replacements 0 # number of replacements | 652system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 653system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 616system.cpu.l2cache.tags.tagsinuse 221.171170 # Cycle average of tags in use | 654system.cpu.l2cache.tags.tagsinuse 221.271055 # Cycle average of tags in use |
| 617system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 618system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 619system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. 620system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 655system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 656system.cpu.l2cache.tags.sampled_refs 399 # Sample count of references to valid blocks. 657system.cpu.l2cache.tags.avg_refs 0.005013 # Average number of references to valid blocks. 658system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 621system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.732473 # Average occupied blocks per requestor 622system.cpu.l2cache.tags.occ_blocks::cpu.data 34.438696 # Average occupied blocks per requestor 623system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005699 # Average percentage of cache occupancy 624system.cpu.l2cache.tags.occ_percent::cpu.data 0.001051 # Average percentage of cache occupancy 625system.cpu.l2cache.tags.occ_percent::total 0.006750 # Average percentage of cache occupancy | 659system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.815406 # Average occupied blocks per requestor 660system.cpu.l2cache.tags.occ_blocks::cpu.data 34.455649 # Average occupied blocks per requestor 661system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005701 # Average percentage of cache occupancy 662system.cpu.l2cache.tags.occ_percent::cpu.data 0.001052 # Average percentage of cache occupancy 663system.cpu.l2cache.tags.occ_percent::total 0.006753 # Average percentage of cache occupancy |
| 626system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id 627system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 628system.cpu.l2cache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id 629system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id 630system.cpu.l2cache.tags.tag_accesses 4354 # Number of tag accesses 631system.cpu.l2cache.tags.data_accesses 4354 # Number of data accesses 632system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 633system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits --- 7 unchanged lines hidden (view full) --- 641system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 642system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 643system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 644system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses 645system.cpu.l2cache.demand_misses::total 482 # number of demand (read+write) misses 646system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 647system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses 648system.cpu.l2cache.overall_misses::total 482 # number of overall misses | 664system.cpu.l2cache.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id 665system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 666system.cpu.l2cache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id 667system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012177 # Percentage of cache occupancy per task id 668system.cpu.l2cache.tags.tag_accesses 4354 # Number of tag accesses 669system.cpu.l2cache.tags.data_accesses 4354 # Number of data accesses 670system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 671system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits --- 7 unchanged lines hidden (view full) --- 679system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses 680system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses 681system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 682system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses 683system.cpu.l2cache.demand_misses::total 482 # number of demand (read+write) misses 684system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 685system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses 686system.cpu.l2cache.overall_misses::total 482 # number of overall misses |
| 649system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22186250 # number of ReadReq miss cycles 650system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4642250 # number of ReadReq miss cycles 651system.cpu.l2cache.ReadReq_miss_latency::total 26828500 # number of ReadReq miss cycles 652system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6101000 # number of ReadExReq miss cycles 653system.cpu.l2cache.ReadExReq_miss_latency::total 6101000 # number of ReadExReq miss cycles 654system.cpu.l2cache.demand_miss_latency::cpu.inst 22186250 # number of demand (read+write) miss cycles 655system.cpu.l2cache.demand_miss_latency::cpu.data 10743250 # number of demand (read+write) miss cycles 656system.cpu.l2cache.demand_miss_latency::total 32929500 # number of demand (read+write) miss cycles 657system.cpu.l2cache.overall_miss_latency::cpu.inst 22186250 # number of overall miss cycles 658system.cpu.l2cache.overall_miss_latency::cpu.data 10743250 # number of overall miss cycles 659system.cpu.l2cache.overall_miss_latency::total 32929500 # number of overall miss cycles | 687system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22159000 # number of ReadReq miss cycles 688system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4637250 # number of ReadReq miss cycles 689system.cpu.l2cache.ReadReq_miss_latency::total 26796250 # number of ReadReq miss cycles 690system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6037250 # number of ReadExReq miss cycles 691system.cpu.l2cache.ReadExReq_miss_latency::total 6037250 # number of ReadExReq miss cycles 692system.cpu.l2cache.demand_miss_latency::cpu.inst 22159000 # number of demand (read+write) miss cycles 693system.cpu.l2cache.demand_miss_latency::cpu.data 10674500 # number of demand (read+write) miss cycles 694system.cpu.l2cache.demand_miss_latency::total 32833500 # number of demand (read+write) miss cycles 695system.cpu.l2cache.overall_miss_latency::cpu.inst 22159000 # number of overall miss cycles 696system.cpu.l2cache.overall_miss_latency::cpu.data 10674500 # number of overall miss cycles 697system.cpu.l2cache.overall_miss_latency::total 32833500 # number of overall miss cycles |
| 660system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) 661system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) 662system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) 663system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 664system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 665system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses 666system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 667system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 674system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 675system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 676system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses 677system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 678system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses 679system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses 680system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 681system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses | 698system.cpu.l2cache.ReadReq_accesses::cpu.inst 337 # number of ReadReq accesses(hits+misses) 699system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) 700system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) 701system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) 702system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) 703system.cpu.l2cache.demand_accesses::cpu.inst 337 # number of demand (read+write) accesses 704system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 705system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 712system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 713system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 714system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994065 # miss rate for demand accesses 715system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 716system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses 717system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994065 # miss rate for overall accesses 718system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 719system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses |
| 682system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66227.611940 # average ReadReq miss latency 683system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72535.156250 # average ReadReq miss latency 684system.cpu.l2cache.ReadReq_avg_miss_latency::total 67239.348371 # average ReadReq miss latency 685system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73506.024096 # average ReadExReq miss latency 686system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73506.024096 # average ReadExReq miss latency 687system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66227.611940 # average overall miss latency 688system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73083.333333 # average overall miss latency 689system.cpu.l2cache.demand_avg_miss_latency::total 68318.464730 # average overall miss latency 690system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66227.611940 # average overall miss latency 691system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73083.333333 # average overall miss latency 692system.cpu.l2cache.overall_avg_miss_latency::total 68318.464730 # average overall miss latency | 720system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66146.268657 # average ReadReq miss latency 721system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72457.031250 # average ReadReq miss latency 722system.cpu.l2cache.ReadReq_avg_miss_latency::total 67158.521303 # average ReadReq miss latency 723system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72737.951807 # average ReadExReq miss latency 724system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72737.951807 # average ReadExReq miss latency 725system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66146.268657 # average overall miss latency 726system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72615.646259 # average overall miss latency 727system.cpu.l2cache.demand_avg_miss_latency::total 68119.294606 # average overall miss latency 728system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66146.268657 # average overall miss latency 729system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72615.646259 # average overall miss latency 730system.cpu.l2cache.overall_avg_miss_latency::total 68119.294606 # average overall miss latency |
| 693system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 694system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 695system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 696system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 697system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 698system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 699system.cpu.l2cache.fast_writes 0 # number of fast writes performed 700system.cpu.l2cache.cache_copies 0 # number of cache copies performed 701system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 702system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 703system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses 704system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 705system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 706system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 707system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 708system.cpu.l2cache.demand_mshr_misses::total 482 # number of demand (read+write) MSHR misses 709system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 710system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 711system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses | 731system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 732system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 733system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 734system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 735system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 736system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 737system.cpu.l2cache.fast_writes 0 # number of fast writes performed 738system.cpu.l2cache.cache_copies 0 # number of cache copies performed 739system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 740system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 741system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses 742system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses 743system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses 744system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 745system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 746system.cpu.l2cache.demand_mshr_misses::total 482 # number of demand (read+write) MSHR misses 747system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 748system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 749system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses |
| 712system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17979250 # number of ReadReq MSHR miss cycles 713system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3856250 # number of ReadReq MSHR miss cycles 714system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21835500 # number of ReadReq MSHR miss cycles 715system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5083000 # number of ReadExReq MSHR miss cycles 716system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5083000 # number of ReadExReq MSHR miss cycles 717system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17979250 # number of demand (read+write) MSHR miss cycles 718system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8939250 # number of demand (read+write) MSHR miss cycles 719system.cpu.l2cache.demand_mshr_miss_latency::total 26918500 # number of demand (read+write) MSHR miss cycles 720system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17979250 # number of overall MSHR miss cycles 721system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8939250 # number of overall MSHR miss cycles 722system.cpu.l2cache.overall_mshr_miss_latency::total 26918500 # number of overall MSHR miss cycles | 750system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17946500 # number of ReadReq MSHR miss cycles 751system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3851750 # number of ReadReq MSHR miss cycles 752system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21798250 # number of ReadReq MSHR miss cycles 753system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5016750 # number of ReadExReq MSHR miss cycles 754system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5016750 # number of ReadExReq MSHR miss cycles 755system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17946500 # number of demand (read+write) MSHR miss cycles 756system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8868500 # number of demand (read+write) MSHR miss cycles 757system.cpu.l2cache.demand_mshr_miss_latency::total 26815000 # number of demand (read+write) MSHR miss cycles 758system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17946500 # number of overall MSHR miss cycles 759system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8868500 # number of overall MSHR miss cycles 760system.cpu.l2cache.overall_mshr_miss_latency::total 26815000 # number of overall MSHR miss cycles |
| 723system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses 724system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 725system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses 726system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 727system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 728system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses 729system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 730system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses 731system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses 732system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 733system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses | 761system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for ReadReq accesses 762system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 763system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses 764system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 765system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 766system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for demand accesses 767system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 768system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses 769system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994065 # mshr miss rate for overall accesses 770system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 771system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses |
| 734system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53669.402985 # average ReadReq mshr miss latency 735system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60253.906250 # average ReadReq mshr miss latency 736system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54725.563910 # average ReadReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61240.963855 # average ReadExReq mshr miss latency 738system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61240.963855 # average ReadExReq mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53669.402985 # average overall mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60811.224490 # average overall mshr miss latency 741system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55847.510373 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53669.402985 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60811.224490 # average overall mshr miss latency 744system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55847.510373 # average overall mshr miss latency | 772system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53571.641791 # average ReadReq mshr miss latency 773system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60183.593750 # average ReadReq mshr miss latency 774system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54632.205514 # average ReadReq mshr miss latency 775system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60442.771084 # average ReadExReq mshr miss latency 776system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60442.771084 # average ReadExReq mshr miss latency 777system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53571.641791 # average overall mshr miss latency 778system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60329.931973 # average overall mshr miss latency 779system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55632.780083 # average overall mshr miss latency 780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53571.641791 # average overall mshr miss latency 781system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60329.931973 # average overall mshr miss latency 782system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55632.780083 # average overall mshr miss latency |
| 745system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 746system.cpu.dcache.tags.replacements 0 # number of replacements | 783system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 784system.cpu.dcache.tags.replacements 0 # number of replacements |
| 747system.cpu.dcache.tags.tagsinuse 99.038544 # Cycle average of tags in use | 785system.cpu.dcache.tags.tagsinuse 99.054052 # Cycle average of tags in use |
| 748system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. 749system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 750system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. 751system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 786system.cpu.dcache.tags.total_refs 4001 # Total number of references to valid blocks. 787system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. 788system.cpu.dcache.tags.avg_refs 27.217687 # Average number of references to valid blocks. 789system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 752system.cpu.dcache.tags.occ_blocks::cpu.data 99.038544 # Average occupied blocks per requestor 753system.cpu.dcache.tags.occ_percent::cpu.data 0.024179 # Average percentage of cache occupancy 754system.cpu.dcache.tags.occ_percent::total 0.024179 # Average percentage of cache occupancy | 790system.cpu.dcache.tags.occ_blocks::cpu.data 99.054052 # Average occupied blocks per requestor 791system.cpu.dcache.tags.occ_percent::cpu.data 0.024183 # Average percentage of cache occupancy 792system.cpu.dcache.tags.occ_percent::total 0.024183 # Average percentage of cache occupancy |
| 755system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 756system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 757system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 758system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 759system.cpu.dcache.tags.tag_accesses 9219 # Number of tag accesses 760system.cpu.dcache.tags.data_accesses 9219 # Number of data accesses 761system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits 762system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits --- 8 unchanged lines hidden (view full) --- 771system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses 772system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses 773system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 774system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 775system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses 776system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses 777system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses 778system.cpu.dcache.overall_misses::total 535 # number of overall misses | 793system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id 794system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 795system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 796system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id 797system.cpu.dcache.tags.tag_accesses 9219 # Number of tag accesses 798system.cpu.dcache.tags.data_accesses 9219 # Number of data accesses 799system.cpu.dcache.ReadReq_hits::cpu.data 2962 # number of ReadReq hits 800system.cpu.dcache.ReadReq_hits::total 2962 # number of ReadReq hits --- 8 unchanged lines hidden (view full) --- 809system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses 810system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses 811system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 812system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 813system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses 814system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses 815system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses 816system.cpu.dcache.overall_misses::total 535 # number of overall misses |
| 779system.cpu.dcache.ReadReq_miss_latency::cpu.data 7972250 # number of ReadReq miss cycles 780system.cpu.dcache.ReadReq_miss_latency::total 7972250 # number of ReadReq miss cycles 781system.cpu.dcache.WriteReq_miss_latency::cpu.data 25777976 # number of WriteReq miss cycles 782system.cpu.dcache.WriteReq_miss_latency::total 25777976 # number of WriteReq miss cycles 783system.cpu.dcache.demand_miss_latency::cpu.data 33750226 # number of demand (read+write) miss cycles 784system.cpu.dcache.demand_miss_latency::total 33750226 # number of demand (read+write) miss cycles 785system.cpu.dcache.overall_miss_latency::cpu.data 33750226 # number of overall miss cycles 786system.cpu.dcache.overall_miss_latency::total 33750226 # number of overall miss cycles | 817system.cpu.dcache.ReadReq_miss_latency::cpu.data 7967250 # number of ReadReq miss cycles 818system.cpu.dcache.ReadReq_miss_latency::total 7967250 # number of ReadReq miss cycles 819system.cpu.dcache.WriteReq_miss_latency::cpu.data 25697977 # number of WriteReq miss cycles 820system.cpu.dcache.WriteReq_miss_latency::total 25697977 # number of WriteReq miss cycles 821system.cpu.dcache.demand_miss_latency::cpu.data 33665227 # number of demand (read+write) miss cycles 822system.cpu.dcache.demand_miss_latency::total 33665227 # number of demand (read+write) miss cycles 823system.cpu.dcache.overall_miss_latency::cpu.data 33665227 # number of overall miss cycles 824system.cpu.dcache.overall_miss_latency::total 33665227 # number of overall miss cycles |
| 787system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) 788system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 791system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 792system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 793system.cpu.dcache.demand_accesses::cpu.data 4530 # number of demand (read+write) accesses 794system.cpu.dcache.demand_accesses::total 4530 # number of demand (read+write) accesses 795system.cpu.dcache.overall_accesses::cpu.data 4530 # number of overall (read+write) accesses 796system.cpu.dcache.overall_accesses::total 4530 # number of overall (read+write) accesses 797system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040803 # miss rate for ReadReq accesses 798system.cpu.dcache.ReadReq_miss_rate::total 0.040803 # miss rate for ReadReq accesses 799system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 800system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses 801system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 # miss rate for demand accesses 802system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses 803system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses 804system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses | 825system.cpu.dcache.ReadReq_accesses::cpu.data 3088 # number of ReadReq accesses(hits+misses) 826system.cpu.dcache.ReadReq_accesses::total 3088 # number of ReadReq accesses(hits+misses) 827system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) 828system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 829system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 830system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 831system.cpu.dcache.demand_accesses::cpu.data 4530 # number of demand (read+write) accesses 832system.cpu.dcache.demand_accesses::total 4530 # number of demand (read+write) accesses 833system.cpu.dcache.overall_accesses::cpu.data 4530 # number of overall (read+write) accesses 834system.cpu.dcache.overall_accesses::total 4530 # number of overall (read+write) accesses 835system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040803 # miss rate for ReadReq accesses 836system.cpu.dcache.ReadReq_miss_rate::total 0.040803 # miss rate for ReadReq accesses 837system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses 838system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses 839system.cpu.dcache.demand_miss_rate::cpu.data 0.118102 # miss rate for demand accesses 840system.cpu.dcache.demand_miss_rate::total 0.118102 # miss rate for demand accesses 841system.cpu.dcache.overall_miss_rate::cpu.data 0.118102 # miss rate for overall accesses 842system.cpu.dcache.overall_miss_rate::total 0.118102 # miss rate for overall accesses |
| 805system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63271.825397 # average ReadReq miss latency 806system.cpu.dcache.ReadReq_avg_miss_latency::total 63271.825397 # average ReadReq miss latency 807system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63026.836186 # average WriteReq miss latency 808system.cpu.dcache.WriteReq_avg_miss_latency::total 63026.836186 # average WriteReq miss latency 809system.cpu.dcache.demand_avg_miss_latency::cpu.data 63084.534579 # average overall miss latency 810system.cpu.dcache.demand_avg_miss_latency::total 63084.534579 # average overall miss latency 811system.cpu.dcache.overall_avg_miss_latency::cpu.data 63084.534579 # average overall miss latency 812system.cpu.dcache.overall_avg_miss_latency::total 63084.534579 # average overall miss latency 813system.cpu.dcache.blocked_cycles::no_mshrs 792 # number of cycles access was blocked | 843system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63232.142857 # average ReadReq miss latency 844system.cpu.dcache.ReadReq_avg_miss_latency::total 63232.142857 # average ReadReq miss latency 845system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62831.239609 # average WriteReq miss latency 846system.cpu.dcache.WriteReq_avg_miss_latency::total 62831.239609 # average WriteReq miss latency 847system.cpu.dcache.demand_avg_miss_latency::cpu.data 62925.657944 # average overall miss latency 848system.cpu.dcache.demand_avg_miss_latency::total 62925.657944 # average overall miss latency 849system.cpu.dcache.overall_avg_miss_latency::cpu.data 62925.657944 # average overall miss latency 850system.cpu.dcache.overall_avg_miss_latency::total 62925.657944 # average overall miss latency 851system.cpu.dcache.blocked_cycles::no_mshrs 776 # number of cycles access was blocked |
| 814system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 852system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 815system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked | 853system.cpu.dcache.blocked::no_mshrs 25 # number of cycles access was blocked |
| 816system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 854system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 817system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.461538 # average number of cycles each access was blocked | 855system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.040000 # average number of cycles each access was blocked |
| 818system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.cpu.dcache.fast_writes 0 # number of fast writes performed 820system.cpu.dcache.cache_copies 0 # number of cache copies performed 821system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits 822system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 823system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 824system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits 825system.cpu.dcache.demand_mshr_hits::cpu.data 388 # number of demand (read+write) MSHR hits 826system.cpu.dcache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits 827system.cpu.dcache.overall_mshr_hits::cpu.data 388 # number of overall MSHR hits 828system.cpu.dcache.overall_mshr_hits::total 388 # number of overall MSHR hits 829system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 830system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 831system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 832system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 833system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 834system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 835system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 836system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses | 856system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 857system.cpu.dcache.fast_writes 0 # number of fast writes performed 858system.cpu.dcache.cache_copies 0 # number of cache copies performed 859system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits 860system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 861system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits 862system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits 863system.cpu.dcache.demand_mshr_hits::cpu.data 388 # number of demand (read+write) MSHR hits 864system.cpu.dcache.demand_mshr_hits::total 388 # number of demand (read+write) MSHR hits 865system.cpu.dcache.overall_mshr_hits::cpu.data 388 # number of overall MSHR hits 866system.cpu.dcache.overall_mshr_hits::total 388 # number of overall MSHR hits 867system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses 868system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses 869system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses 870system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses 871system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 872system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 873system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 874system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses |
| 837system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4706750 # number of ReadReq MSHR miss cycles 838system.cpu.dcache.ReadReq_mshr_miss_latency::total 4706750 # number of ReadReq MSHR miss cycles 839system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6185000 # number of WriteReq MSHR miss cycles 840system.cpu.dcache.WriteReq_mshr_miss_latency::total 6185000 # number of WriteReq MSHR miss cycles 841system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10891750 # number of demand (read+write) MSHR miss cycles 842system.cpu.dcache.demand_mshr_miss_latency::total 10891750 # number of demand (read+write) MSHR miss cycles 843system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10891750 # number of overall MSHR miss cycles 844system.cpu.dcache.overall_mshr_miss_latency::total 10891750 # number of overall MSHR miss cycles | 875system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4701750 # number of ReadReq MSHR miss cycles 876system.cpu.dcache.ReadReq_mshr_miss_latency::total 4701750 # number of ReadReq MSHR miss cycles 877system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6121250 # number of WriteReq MSHR miss cycles 878system.cpu.dcache.WriteReq_mshr_miss_latency::total 6121250 # number of WriteReq MSHR miss cycles 879system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10823000 # number of demand (read+write) MSHR miss cycles 880system.cpu.dcache.demand_mshr_miss_latency::total 10823000 # number of demand (read+write) MSHR miss cycles 881system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10823000 # number of overall MSHR miss cycles 882system.cpu.dcache.overall_mshr_miss_latency::total 10823000 # number of overall MSHR miss cycles |
| 845system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses 846system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses 847system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 848system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses 849system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for demand accesses 850system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses 851system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses 852system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses | 883system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020725 # mshr miss rate for ReadReq accesses 884system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020725 # mshr miss rate for ReadReq accesses 885system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses 886system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses 887system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for demand accesses 888system.cpu.dcache.demand_mshr_miss_rate::total 0.032450 # mshr miss rate for demand accesses 889system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032450 # mshr miss rate for overall accesses 890system.cpu.dcache.overall_mshr_miss_rate::total 0.032450 # mshr miss rate for overall accesses |
| 853system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73542.968750 # average ReadReq mshr miss latency 854system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73542.968750 # average ReadReq mshr miss latency 855system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74518.072289 # average WriteReq mshr miss latency 856system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74518.072289 # average WriteReq mshr miss latency 857system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74093.537415 # average overall mshr miss latency 858system.cpu.dcache.demand_avg_mshr_miss_latency::total 74093.537415 # average overall mshr miss latency 859system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74093.537415 # average overall mshr miss latency 860system.cpu.dcache.overall_avg_mshr_miss_latency::total 74093.537415 # average overall mshr miss latency | 891system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73464.843750 # average ReadReq mshr miss latency 892system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73464.843750 # average ReadReq mshr miss latency 893system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73750 # average WriteReq mshr miss latency 894system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73750 # average WriteReq mshr miss latency 895system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73625.850340 # average overall mshr miss latency 896system.cpu.dcache.demand_avg_mshr_miss_latency::total 73625.850340 # average overall mshr miss latency 897system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73625.850340 # average overall mshr miss latency 898system.cpu.dcache.overall_avg_mshr_miss_latency::total 73625.850340 # average overall mshr miss latency |
| 861system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 862 863---------- End Simulation Statistics ---------- | 899system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 900 901---------- End Simulation Statistics ---------- |