| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 19744500 # Number of ticks simulated 5final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 74885 # Simulator instruction rate (inst/s) 8host_op_rate 74878 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 102311932 # Simulator tick rate (ticks/s) 10host_mem_usage 222004 # Number of bytes of host memory used 11host_seconds 0.19 # Real time elapsed on the host |
| 12sim_insts 14449 # Number of instructions simulated 13sim_ops 14449 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30976 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 484 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1095596242 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 473245714 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1568841956 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1095596242 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1095596242 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1095596242 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 473245714 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1568841956 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.workload.num_syscalls 18 # Number of system calls 31system.cpu.numCycles 39490 # number of cpu cycles simulated 32system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 33system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 34system.cpu.BPredUnit.lookups 6899 # Number of BP lookups 35system.cpu.BPredUnit.condPredicted 4560 # Number of conditional branches predicted 36system.cpu.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect 37system.cpu.BPredUnit.BTBLookups 5346 # Number of BTB lookups --- 282 unchanged lines hidden (view full) --- 320system.cpu.icache.overall_miss_latency::total 16725500 # number of overall miss cycles 321system.cpu.icache.ReadReq_accesses::cpu.inst 5506 # number of ReadReq accesses(hits+misses) 322system.cpu.icache.ReadReq_accesses::total 5506 # number of ReadReq accesses(hits+misses) 323system.cpu.icache.demand_accesses::cpu.inst 5506 # number of demand (read+write) accesses 324system.cpu.icache.demand_accesses::total 5506 # number of demand (read+write) accesses 325system.cpu.icache.overall_accesses::cpu.inst 5506 # number of overall (read+write) accesses 326system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses 327system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.088267 # miss rate for ReadReq accesses |
| 328system.cpu.icache.ReadReq_miss_rate::total 0.088267 # miss rate for ReadReq accesses |
| 329system.cpu.icache.demand_miss_rate::cpu.inst 0.088267 # miss rate for demand accesses |
| 330system.cpu.icache.demand_miss_rate::total 0.088267 # miss rate for demand accesses |
| 331system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses |
| 332system.cpu.icache.overall_miss_rate::total 0.088267 # miss rate for overall accesses |
| 333system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency |
| 334system.cpu.icache.ReadReq_avg_miss_latency::total 34414.609053 # average ReadReq miss latency |
| 335system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency |
| 336system.cpu.icache.demand_avg_miss_latency::total 34414.609053 # average overall miss latency |
| 337system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency |
| 338system.cpu.icache.overall_avg_miss_latency::total 34414.609053 # average overall miss latency |
| 339system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 340system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 341system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 342system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 343system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 344system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 345system.cpu.icache.fast_writes 0 # number of fast writes performed 346system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 358system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses 359system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11937500 # number of ReadReq MSHR miss cycles 360system.cpu.icache.ReadReq_mshr_miss_latency::total 11937500 # number of ReadReq MSHR miss cycles 361system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 # number of demand (read+write) MSHR miss cycles 362system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles 363system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles 364system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles 365system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for ReadReq accesses |
| 366system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061751 # mshr miss rate for ReadReq accesses |
| 367system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses |
| 368system.cpu.icache.demand_mshr_miss_rate::total 0.061751 # mshr miss rate for demand accesses |
| 369system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses |
| 370system.cpu.icache.overall_mshr_miss_rate::total 0.061751 # mshr miss rate for overall accesses |
| 371system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency |
| 372system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency |
| 373system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency |
| 374system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency |
| 375system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency |
| 376system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency |
| 377system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 378system.cpu.dcache.replacements 0 # number of replacements 379system.cpu.dcache.tagsinuse 103.476464 # Cycle average of tags in use 380system.cpu.dcache.total_refs 4083 # Total number of references to valid blocks. 381system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 382system.cpu.dcache.avg_refs 27.965753 # Average number of references to valid blocks. 383system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 384system.cpu.dcache.occ_blocks::cpu.data 103.476464 # Average occupied blocks per requestor --- 31 unchanged lines hidden (view full) --- 416system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) 417system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) 418system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) 419system.cpu.dcache.demand_accesses::cpu.data 4603 # number of demand (read+write) accesses 420system.cpu.dcache.demand_accesses::total 4603 # number of demand (read+write) accesses 421system.cpu.dcache.overall_accesses::cpu.data 4603 # number of overall (read+write) accesses 422system.cpu.dcache.overall_accesses::total 4603 # number of overall (read+write) accesses 423system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037330 # miss rate for ReadReq accesses |
| 424system.cpu.dcache.ReadReq_miss_rate::total 0.037330 # miss rate for ReadReq accesses |
| 425system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses |
| 426system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses |
| 427system.cpu.dcache.demand_miss_rate::cpu.data 0.114273 # miss rate for demand accesses |
| 428system.cpu.dcache.demand_miss_rate::total 0.114273 # miss rate for demand accesses |
| 429system.cpu.dcache.overall_miss_rate::cpu.data 0.114273 # miss rate for overall accesses |
| 430system.cpu.dcache.overall_miss_rate::total 0.114273 # miss rate for overall accesses |
| 431system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency |
| 432system.cpu.dcache.ReadReq_avg_miss_latency::total 34682.203390 # average ReadReq miss latency |
| 433system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency |
| 434system.cpu.dcache.WriteReq_avg_miss_latency::total 35768.382353 # average WriteReq miss latency |
| 435system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency |
| 436system.cpu.dcache.demand_avg_miss_latency::total 35524.714829 # average overall miss latency |
| 437system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency |
| 438system.cpu.dcache.overall_avg_miss_latency::total 35524.714829 # average overall miss latency |
| 439system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 440system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 441system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 442system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 443system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 444system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 445system.cpu.dcache.fast_writes 0 # number of fast writes performed 446system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 464system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243500 # number of ReadReq MSHR miss cycles 465system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2979500 # number of WriteReq MSHR miss cycles 466system.cpu.dcache.WriteReq_mshr_miss_latency::total 2979500 # number of WriteReq MSHR miss cycles 467system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles 468system.cpu.dcache.demand_mshr_miss_latency::total 5223000 # number of demand (read+write) MSHR miss cycles 469system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles 470system.cpu.dcache.overall_mshr_miss_latency::total 5223000 # number of overall MSHR miss cycles 471system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019930 # mshr miss rate for ReadReq accesses |
| 472system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019930 # mshr miss rate for ReadReq accesses |
| 473system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses |
| 474system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses |
| 475system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for demand accesses |
| 476system.cpu.dcache.demand_mshr_miss_rate::total 0.031718 # mshr miss rate for demand accesses |
| 477system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for overall accesses |
| 478system.cpu.dcache.overall_mshr_miss_rate::total 0.031718 # mshr miss rate for overall accesses |
| 479system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency |
| 480system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency |
| 481system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361 # average WriteReq mshr miss latency |
| 482system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35897.590361 # average WriteReq mshr miss latency |
| 483system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency |
| 484system.cpu.dcache.demand_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency |
| 485system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency |
| 486system.cpu.dcache.overall_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency |
| 487system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 488system.cpu.l2cache.replacements 0 # number of replacements 489system.cpu.l2cache.tagsinuse 236.259194 # Cycle average of tags in use 490system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 491system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. 492system.cpu.l2cache.avg_refs 0.004988 # Average number of references to valid blocks. 493system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 494system.cpu.l2cache.occ_blocks::cpu.inst 200.029408 # Average occupied blocks per requestor --- 37 unchanged lines hidden (view full) --- 532system.cpu.l2cache.demand_accesses::cpu.inst 340 # number of demand (read+write) accesses 533system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses 534system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses 535system.cpu.l2cache.overall_accesses::cpu.inst 340 # number of overall (read+write) accesses 536system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses 537system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses 538system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994118 # miss rate for ReadReq accesses 539system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses |
| 540system.cpu.l2cache.ReadReq_miss_rate::total 0.995037 # miss rate for ReadReq accesses |
| 541system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| 542system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 543system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994118 # miss rate for demand accesses 544system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 545system.cpu.l2cache.demand_miss_rate::total 0.995885 # miss rate for demand accesses |
| 546system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses 547system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 548system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses |
| 549system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.751479 # average ReadReq miss latency 550system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency |
| 551system.cpu.l2cache.ReadReq_avg_miss_latency::total 34293.017456 # average ReadReq miss latency |
| 552system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency |
| 553system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency |
| 554system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency 555system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency |
| 556system.cpu.l2cache.demand_avg_miss_latency::total 34339.876033 # average overall miss latency |
| 557system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency 558system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency |
| 559system.cpu.l2cache.overall_avg_miss_latency::total 34339.876033 # average overall miss latency |
| 560system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 561system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 562system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 563system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 564system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 565system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 566system.cpu.l2cache.fast_writes 0 # number of fast writes performed 567system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 584system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10497000 # number of demand (read+write) MSHR miss cycles 585system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4576000 # number of demand (read+write) MSHR miss cycles 586system.cpu.l2cache.demand_mshr_miss_latency::total 15073000 # number of demand (read+write) MSHR miss cycles 587system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10497000 # number of overall MSHR miss cycles 588system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 # number of overall MSHR miss cycles 589system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles 590system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses 591system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses |
| 592system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses |
| 593system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| 594system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 595system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for demand accesses 596system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 597system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 # mshr miss rate for demand accesses |
| 598system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses 599system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 600system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses |
| 601system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency 602system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency |
| 603system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.034913 # average ReadReq mshr miss latency |
| 604system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency |
| 605system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency |
| 606system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency 607system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency |
| 608system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency |
| 609system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency 610system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency |
| 611system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency |
| 612system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 613 614---------- End Simulation Statistics ---------- |