1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000027 # Number of seconds simulated 4sim_ticks 26706500 # Number of ticks simulated 5final_tick 26706500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 64712 # Simulator instruction rate (inst/s) 8host_op_rate 64708 # Simulator op (including micro ops) rate (op/s) --- 518 unchanged lines hidden (view full) --- 527system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached 528system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 529system.cpu.rob.rob_reads 54927 # The number of ROB reads 530system.cpu.rob.rob_writes 50296 # The number of ROB writes 531system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself 532system.cpu.idleCycles 19883 # Total number of cycles that the CPU has spent unscheduled due to idling 533system.cpu.committedInsts 14436 # Number of Instructions Simulated 534system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated |
535system.cpu.cpi 3.700055 # CPI: Cycles Per Instruction 536system.cpu.cpi_total 3.700055 # CPI: Total CPI of All Threads 537system.cpu.ipc 0.270266 # IPC: Instructions Per Cycle 538system.cpu.ipc_total 0.270266 # IPC: Total IPC of All Threads 539system.cpu.int_regfile_reads 32043 # number of integer regfile reads 540system.cpu.int_regfile_writes 17841 # number of integer regfile writes 541system.cpu.misc_regfile_reads 6919 # number of misc regfile reads 542system.cpu.misc_regfile_writes 569 # number of misc regfile writes --- 358 unchanged lines hidden --- |