4,5c4,5
< sim_ticks 26524500 # Number of ticks simulated
< final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 26616500 # Number of ticks simulated
> final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 19767 # Simulator instruction rate (inst/s)
< host_op_rate 19766 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 36317578 # Simulator tick rate (ticks/s)
< host_mem_usage 236084 # Number of bytes of host memory used
< host_seconds 0.73 # Real time elapsed on the host
---
> host_inst_rate 75478 # Simulator instruction rate (inst/s)
> host_op_rate 75473 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 139143595 # Simulator tick rate (ticks/s)
> host_mem_usage 260732 # Number of bytes of host memory used
> host_seconds 0.19 # Real time elapsed on the host
22,88c22,90
< system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller
< system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
< system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
< system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
< system.physmem.bytesRead 30848 # Total number of bytes read from memory
< system.physmem.bytesWritten 0 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
< system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 57 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 61 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
< system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
< system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
< system.physmem.totGap 26363500 # Total gap between requests
< system.physmem.readPktSize::0 0 # Categorize read packet sizes
< system.physmem.readPktSize::1 0 # Categorize read packet sizes
< system.physmem.readPktSize::2 0 # Categorize read packet sizes
< system.physmem.readPktSize::3 0 # Categorize read packet sizes
< system.physmem.readPktSize::4 0 # Categorize read packet sizes
< system.physmem.readPktSize::5 0 # Categorize read packet sizes
< system.physmem.readPktSize::6 482 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # Categorize write packet sizes
< system.physmem.writePktSize::1 0 # Categorize write packet sizes
< system.physmem.writePktSize::2 0 # Categorize write packet sizes
< system.physmem.writePktSize::3 0 # Categorize write packet sizes
< system.physmem.writePktSize::4 0 # Categorize write packet sizes
< system.physmem.writePktSize::5 0 # Categorize write packet sizes
< system.physmem.writePktSize::6 0 # Categorize write packet sizes
---
> system.physmem.bw_read::cpu.inst 805515376 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 353464956 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1158980332 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 805515376 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 805515376 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 805515376 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 353464956 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1158980332 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 482 # Number of read requests accepted
> system.physmem.writeReqs 0 # Number of write requests accepted
> system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
> system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 102 # Per bank write bursts
> system.physmem.perBankRdBursts::1 29 # Per bank write bursts
> system.physmem.perBankRdBursts::2 50 # Per bank write bursts
> system.physmem.perBankRdBursts::3 24 # Per bank write bursts
> system.physmem.perBankRdBursts::4 19 # Per bank write bursts
> system.physmem.perBankRdBursts::5 0 # Per bank write bursts
> system.physmem.perBankRdBursts::6 32 # Per bank write bursts
> system.physmem.perBankRdBursts::7 35 # Per bank write bursts
> system.physmem.perBankRdBursts::8 4 # Per bank write bursts
> system.physmem.perBankRdBursts::9 1 # Per bank write bursts
> system.physmem.perBankRdBursts::10 1 # Per bank write bursts
> system.physmem.perBankRdBursts::11 0 # Per bank write bursts
> system.physmem.perBankRdBursts::12 57 # Per bank write bursts
> system.physmem.perBankRdBursts::13 31 # Per bank write bursts
> system.physmem.perBankRdBursts::14 61 # Per bank write bursts
> system.physmem.perBankRdBursts::15 36 # Per bank write bursts
> system.physmem.perBankWrBursts::0 0 # Per bank write bursts
> system.physmem.perBankWrBursts::1 0 # Per bank write bursts
> system.physmem.perBankWrBursts::2 0 # Per bank write bursts
> system.physmem.perBankWrBursts::3 0 # Per bank write bursts
> system.physmem.perBankWrBursts::4 0 # Per bank write bursts
> system.physmem.perBankWrBursts::5 0 # Per bank write bursts
> system.physmem.perBankWrBursts::6 0 # Per bank write bursts
> system.physmem.perBankWrBursts::7 0 # Per bank write bursts
> system.physmem.perBankWrBursts::8 0 # Per bank write bursts
> system.physmem.perBankWrBursts::9 0 # Per bank write bursts
> system.physmem.perBankWrBursts::10 0 # Per bank write bursts
> system.physmem.perBankWrBursts::11 0 # Per bank write bursts
> system.physmem.perBankWrBursts::12 0 # Per bank write bursts
> system.physmem.perBankWrBursts::13 0 # Per bank write bursts
> system.physmem.perBankWrBursts::14 0 # Per bank write bursts
> system.physmem.perBankWrBursts::15 0 # Per bank write bursts
> system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
> system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
> system.physmem.totGap 26455500 # Total gap between requests
> system.physmem.readPktSize::0 0 # Read request sizes (log2)
> system.physmem.readPktSize::1 0 # Read request sizes (log2)
> system.physmem.readPktSize::2 0 # Read request sizes (log2)
> system.physmem.readPktSize::3 0 # Read request sizes (log2)
> system.physmem.readPktSize::4 0 # Read request sizes (log2)
> system.physmem.readPktSize::5 0 # Read request sizes (log2)
> system.physmem.readPktSize::6 482 # Read request sizes (log2)
> system.physmem.writePktSize::0 0 # Write request sizes (log2)
> system.physmem.writePktSize::1 0 # Write request sizes (log2)
> system.physmem.writePktSize::2 0 # Write request sizes (log2)
> system.physmem.writePktSize::3 0 # Write request sizes (log2)
> system.physmem.writePktSize::4 0 # Write request sizes (log2)
> system.physmem.writePktSize::5 0 # Write request sizes (log2)
> system.physmem.writePktSize::6 0 # Write request sizes (log2)
90,91c92,93
< system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
153,188c155,196
< system.physmem.bytesPerActivate::samples 52 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 361.846154 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 181.816034 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 531.077461 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64 20 38.46% 38.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128 7 13.46% 51.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192 5 9.62% 61.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256 5 9.62% 71.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320 3 5.77% 76.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384 2 3.85% 80.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512 1 1.92% 82.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640 1 1.92% 84.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768 1 1.92% 86.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832 1 1.92% 88.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960 2 3.85% 92.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation
< system.physmem.totQLat 1755500 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests
< system.physmem.totBusLat 2410000 # Total cycles spent in databus access
< system.physmem.totBankLat 6765000 # Total cycles spent in bank access
< system.physmem.avgQLat 3642.12 # Average queueing delay per request
< system.physmem.avgBankLat 14035.27 # Average bank access latency per request
< system.physmem.avgBusLat 5000.00 # Average bus latency per request
< system.physmem.avgMemAccLat 22677.39 # Average memory access latency
< system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
< system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
< system.physmem.busUtil 9.09 # Data bus utilization in percentage
< system.physmem.avgRdQLen 0.41 # Average read queue length over time
< system.physmem.avgWrQLen 0.00 # Average write queue length over time
< system.physmem.readRowHits 430 # Number of row buffer hits during reads
---
> system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 386.782609 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 201.135099 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 508.628284 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64 23 33.33% 33.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128 10 14.49% 47.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192 9 13.04% 60.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256 6 8.70% 69.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320 2 2.90% 72.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384 2 2.90% 75.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512 2 2.90% 78.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640 2 2.90% 81.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704 1 1.45% 82.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768 1 1.45% 84.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832 2 2.90% 86.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024 1 1.45% 88.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088 2 2.90% 91.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344 1 1.45% 92.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600 1 1.45% 94.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792 1 1.45% 95.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856 2 2.90% 98.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176 1 1.45% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation
> system.physmem.totQLat 2423000 # Total ticks spent queuing
> system.physmem.totMemAccLat 11611750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 6778750 # Total ticks spent accessing banks
> system.physmem.avgQLat 5026.97 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 14063.80 # Average bank access latency per DRAM burst
> system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 24090.77 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1158.98 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1158.98 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
> system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
> system.physmem.busUtil 9.05 # Data bus utilization in percentage
> system.physmem.busUtilRead 9.05 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 0.44 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
> system.physmem.readRowHits 413 # Number of row buffer hits during reads
190c198
< system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 85.68 # Row buffer hit rate for reads
192,193c200,203
< system.physmem.avgGap 54696.06 # Average gap between requests
< system.membus.throughput 1163000245 # Throughput (bytes/s)
---
> system.physmem.avgGap 54886.93 # Average gap between requests
> system.physmem.pageHitRate 85.68 # Row buffer hit rate, read and write combined
> system.physmem.prechargeAllPercent 5.39 # Percentage of time for which DRAM has all the banks in precharge state
> system.membus.throughput 1158980332 # Throughput (bytes/s)
204c214
< system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks)
206,209c216,219
< system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 17.0 # Layer utilization (%)
< system.cpu.branchPred.lookups 6716 # Number of BP lookups
< system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted
---
> system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 16.9 # Layer utilization (%)
> system.cpu.branchPred.lookups 6713 # Number of BP lookups
> system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted
211c221
< system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 5019 # Number of BTB lookups
214c224
< system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 48.455868 # BTB Hit Percentage
218c228
< system.cpu.numCycles 53050 # number of cpu cycles simulated
---
> system.cpu.numCycles 53234 # number of cpu cycles simulated
221,223c231,233
< system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered
---
> system.cpu.fetch.icacheStallCycles 12410 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 31113 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered
225c235
< system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 9131 # Number of cycles fetch has run and was not squashing or blocked
227c237
< system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 8795 # Number of cycles fetch has spent blocked
229,230c239,240
< system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps
< system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched
---
> system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps
> system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched
232,234c242,244
< system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 33133 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.939034 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.131220 # Number of instructions fetched each cycle (Total)
236,244c246,254
< system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 24002 72.44% 72.44% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 4510 13.61% 86.05% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 474 1.43% 87.48% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 392 1.18% 88.67% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 680 2.05% 90.72% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 706 2.13% 92.85% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 253 0.76% 94.32% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1881 5.68% 100.00% # Number of instructions fetched each cycle (Total)
248,253c258,263
< system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 8344 # Number of cycles decode is running
---
> system.cpu.fetch.rateDist::total 33133 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.126104 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.584457 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 12933 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 9787 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 8343 # Number of cycles decode is running
256c266
< system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode
258c268
< system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 13575 # Number of cycles rename is idle
260c270
< system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst
---
> system.cpu.rename.serializeStallCycles 8758 # count of cycles rename stalled for serializing inst
285,287c295,297
< system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 33133 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.637491 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.262113 # Number of insts issued each cycle
289,293c299,303
< system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 23891 72.11% 72.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 3555 10.73% 82.84% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 2321 7.01% 89.84% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 1704 5.14% 94.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 887 2.68% 97.66% # Number of insts issued each cycle
301c311
< system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 33133 # Number of insts issued each cycle
371c381
< system.cpu.iq.rate 0.398153 # Inst issue rate
---
> system.cpu.iq.rate 0.396776 # Inst issue rate
374c384
< system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 75621 # Number of integer instruction queue reads
415c425
< system.cpu.iew.exec_rate 0.378398 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.377090 # Inst execution rate
421c431
< system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.366721 # insts written-back per cycle
427,429c437,439
< system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 31261 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.485013 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.183057 # Number of insts commited each cycle
431,435c441,445
< system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 23946 76.60% 76.60% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 4068 13.01% 89.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.96% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 764 2.44% 96.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 348 1.11% 97.51% # Number of insts commited each cycle
438c448
< system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle
443c453
< system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 31261 # Number of insts commited each cycle
456c466
< system.cpu.rob.rob_reads 54596 # The number of ROB reads
---
> system.cpu.rob.rob_reads 54530 # The number of ROB reads
458,459c468,469
< system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 20101 # Total number of cycles that the CPU has spent unscheduled due to idling
463,466c473,476
< system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 3.687587 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 3.687587 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.271180 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.271180 # IPC: Total IPC of All Threads
471c481
< system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1163789379 # Throughput (bytes/s)
486c496
< system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 564500 # Layer occupancy (ticks)
488c498
< system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks)
491,492c501,502
< system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 187.514405 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks.
494c504
< system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks.
496,504c506,514
< system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits
< system.cpu.icache.overall_hits::total 4873 # number of overall hits
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits
> system.cpu.icache.overall_hits::total 4872 # number of overall hits
511,534c521,544
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31160500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31160500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31160500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31160500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31160500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31160500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094238 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.094238 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.094238 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.094238 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.094238 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.094238 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61460.552268 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61460.552268 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61460.552268 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61460.552268 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31694500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31694500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31694500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31694500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31694500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31694500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62513.806706 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62513.806706 # average overall miss latency
555,572c565,582
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22334500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22334500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22334500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22334500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22334500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22334500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062639 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.062639 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22488500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22488500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22488500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22488500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22488500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22488500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency
575c585
< system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 221.363231 # Cycle average of tags in use
580,582c590,592
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.907225 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy
584c594
< system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy
602,612c612,622
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21977500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4600000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 26577500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5717750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21977500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10317750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 32295250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21977500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10317750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 32295250 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22131500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5102250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 27233750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5727000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5727000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22131500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10829250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 32960750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22131500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10829250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 32960750 # number of overall miss cycles
635,645c645,655
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71875 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 66610.275689 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68888.554217 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 67002.593361 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 67002.593361 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69000 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69000 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755 # average overall miss latency
665,675c675,685
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17752000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3813000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 21565000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4699750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4699750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17752000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8512750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 26264750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8512750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17918000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4316250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22234250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4712000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4712000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17918000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9028250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26946250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17918000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9028250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26946250 # number of overall MSHR miss cycles
687,697c697,707
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency
700c710
< system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 99.106073 # Cycle average of tags in use
705,707c715,717
< system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy
726,733c736,743
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 32684224 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8431750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8431750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 24708724 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 24708724 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 33140474 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 33140474 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 33140474 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 33140474 # number of overall miss cycles
752,759c762,769
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61944.811215 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61944.811215 # average overall miss latency
784,791c794,801
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4664500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5801750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 5801750 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10466250 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5166750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5166750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5811000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5811000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10977750 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10977750 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10977750 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10977750 # number of overall MSHR miss cycles
800,807c810,817
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency
< sim_ticks 26524500 # Number of ticks simulated
< final_tick 26524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 26616500 # Number of ticks simulated
> final_tick 26616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 19767 # Simulator instruction rate (inst/s)
< host_op_rate 19766 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 36317578 # Simulator tick rate (ticks/s)
< host_mem_usage 236084 # Number of bytes of host memory used
< host_seconds 0.73 # Real time elapsed on the host
---
> host_inst_rate 75478 # Simulator instruction rate (inst/s)
> host_op_rate 75473 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 139143595 # Simulator tick rate (ticks/s)
> host_mem_usage 260732 # Number of bytes of host memory used
> host_seconds 0.19 # Real time elapsed on the host
22,88c22,90
< system.physmem.bw_read::cpu.inst 808309299 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 354690946 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1163000245 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 808309299 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 808309299 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 808309299 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 354690946 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1163000245 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 482 # Total number of read requests accepted by DRAM controller
< system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
< system.physmem.readBursts 482 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
< system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
< system.physmem.bytesRead 30848 # Total number of bytes read from memory
< system.physmem.bytesWritten 0 # Total number of bytes written to memory
< system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize()
< system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
< system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
< system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
< system.physmem.perBankRdReqs::0 102 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::2 50 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::3 24 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::4 19 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::10 1 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::12 57 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::13 31 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::14 61 # Track reads on a per bank basis
< system.physmem.perBankRdReqs::15 36 # Track reads on a per bank basis
< system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
< system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
< system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
< system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
< system.physmem.totGap 26363500 # Total gap between requests
< system.physmem.readPktSize::0 0 # Categorize read packet sizes
< system.physmem.readPktSize::1 0 # Categorize read packet sizes
< system.physmem.readPktSize::2 0 # Categorize read packet sizes
< system.physmem.readPktSize::3 0 # Categorize read packet sizes
< system.physmem.readPktSize::4 0 # Categorize read packet sizes
< system.physmem.readPktSize::5 0 # Categorize read packet sizes
< system.physmem.readPktSize::6 482 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # Categorize write packet sizes
< system.physmem.writePktSize::1 0 # Categorize write packet sizes
< system.physmem.writePktSize::2 0 # Categorize write packet sizes
< system.physmem.writePktSize::3 0 # Categorize write packet sizes
< system.physmem.writePktSize::4 0 # Categorize write packet sizes
< system.physmem.writePktSize::5 0 # Categorize write packet sizes
< system.physmem.writePktSize::6 0 # Categorize write packet sizes
---
> system.physmem.bw_read::cpu.inst 805515376 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 353464956 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1158980332 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 805515376 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 805515376 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 805515376 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 353464956 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1158980332 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 482 # Number of read requests accepted
> system.physmem.writeReqs 0 # Number of write requests accepted
> system.physmem.readBursts 482 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 30848 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
> system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 30848 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 102 # Per bank write bursts
> system.physmem.perBankRdBursts::1 29 # Per bank write bursts
> system.physmem.perBankRdBursts::2 50 # Per bank write bursts
> system.physmem.perBankRdBursts::3 24 # Per bank write bursts
> system.physmem.perBankRdBursts::4 19 # Per bank write bursts
> system.physmem.perBankRdBursts::5 0 # Per bank write bursts
> system.physmem.perBankRdBursts::6 32 # Per bank write bursts
> system.physmem.perBankRdBursts::7 35 # Per bank write bursts
> system.physmem.perBankRdBursts::8 4 # Per bank write bursts
> system.physmem.perBankRdBursts::9 1 # Per bank write bursts
> system.physmem.perBankRdBursts::10 1 # Per bank write bursts
> system.physmem.perBankRdBursts::11 0 # Per bank write bursts
> system.physmem.perBankRdBursts::12 57 # Per bank write bursts
> system.physmem.perBankRdBursts::13 31 # Per bank write bursts
> system.physmem.perBankRdBursts::14 61 # Per bank write bursts
> system.physmem.perBankRdBursts::15 36 # Per bank write bursts
> system.physmem.perBankWrBursts::0 0 # Per bank write bursts
> system.physmem.perBankWrBursts::1 0 # Per bank write bursts
> system.physmem.perBankWrBursts::2 0 # Per bank write bursts
> system.physmem.perBankWrBursts::3 0 # Per bank write bursts
> system.physmem.perBankWrBursts::4 0 # Per bank write bursts
> system.physmem.perBankWrBursts::5 0 # Per bank write bursts
> system.physmem.perBankWrBursts::6 0 # Per bank write bursts
> system.physmem.perBankWrBursts::7 0 # Per bank write bursts
> system.physmem.perBankWrBursts::8 0 # Per bank write bursts
> system.physmem.perBankWrBursts::9 0 # Per bank write bursts
> system.physmem.perBankWrBursts::10 0 # Per bank write bursts
> system.physmem.perBankWrBursts::11 0 # Per bank write bursts
> system.physmem.perBankWrBursts::12 0 # Per bank write bursts
> system.physmem.perBankWrBursts::13 0 # Per bank write bursts
> system.physmem.perBankWrBursts::14 0 # Per bank write bursts
> system.physmem.perBankWrBursts::15 0 # Per bank write bursts
> system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
> system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
> system.physmem.totGap 26455500 # Total gap between requests
> system.physmem.readPktSize::0 0 # Read request sizes (log2)
> system.physmem.readPktSize::1 0 # Read request sizes (log2)
> system.physmem.readPktSize::2 0 # Read request sizes (log2)
> system.physmem.readPktSize::3 0 # Read request sizes (log2)
> system.physmem.readPktSize::4 0 # Read request sizes (log2)
> system.physmem.readPktSize::5 0 # Read request sizes (log2)
> system.physmem.readPktSize::6 482 # Read request sizes (log2)
> system.physmem.writePktSize::0 0 # Write request sizes (log2)
> system.physmem.writePktSize::1 0 # Write request sizes (log2)
> system.physmem.writePktSize::2 0 # Write request sizes (log2)
> system.physmem.writePktSize::3 0 # Write request sizes (log2)
> system.physmem.writePktSize::4 0 # Write request sizes (log2)
> system.physmem.writePktSize::5 0 # Write request sizes (log2)
> system.physmem.writePktSize::6 0 # Write request sizes (log2)
90,91c92,93
< system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 50 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
153,188c155,196
< system.physmem.bytesPerActivate::samples 52 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 361.846154 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 181.816034 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 531.077461 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64 20 38.46% 38.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128 7 13.46% 51.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192 5 9.62% 61.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256 5 9.62% 71.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320 3 5.77% 76.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384 2 3.85% 80.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512 1 1.92% 82.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640 1 1.92% 84.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768 1 1.92% 86.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832 1 1.92% 88.46% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960 2 3.85% 92.31% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856 2 3.85% 96.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112 1 1.92% 98.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176 1 1.92% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 52 # Bytes accessed per row activation
< system.physmem.totQLat 1755500 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 10930500 # Sum of mem lat for all requests
< system.physmem.totBusLat 2410000 # Total cycles spent in databus access
< system.physmem.totBankLat 6765000 # Total cycles spent in bank access
< system.physmem.avgQLat 3642.12 # Average queueing delay per request
< system.physmem.avgBankLat 14035.27 # Average bank access latency per request
< system.physmem.avgBusLat 5000.00 # Average bus latency per request
< system.physmem.avgMemAccLat 22677.39 # Average memory access latency
< system.physmem.avgRdBW 1163.00 # Average achieved read bandwidth in MB/s
< system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
< system.physmem.avgConsumedRdBW 1163.00 # Average consumed read bandwidth in MB/s
< system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
< system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
< system.physmem.busUtil 9.09 # Data bus utilization in percentage
< system.physmem.avgRdQLen 0.41 # Average read queue length over time
< system.physmem.avgWrQLen 0.00 # Average write queue length over time
< system.physmem.readRowHits 430 # Number of row buffer hits during reads
---
> system.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 386.782609 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 201.135099 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 508.628284 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64 23 33.33% 33.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128 10 14.49% 47.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192 9 13.04% 60.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256 6 8.70% 69.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320 2 2.90% 72.46% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384 2 2.90% 75.36% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512 2 2.90% 78.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640 2 2.90% 81.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704 1 1.45% 82.61% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768 1 1.45% 84.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832 2 2.90% 86.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024 1 1.45% 88.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088 2 2.90% 91.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344 1 1.45% 92.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600 1 1.45% 94.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792 1 1.45% 95.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856 2 2.90% 98.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176 1 1.45% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation
> system.physmem.totQLat 2423000 # Total ticks spent queuing
> system.physmem.totMemAccLat 11611750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2410000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 6778750 # Total ticks spent accessing banks
> system.physmem.avgQLat 5026.97 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 14063.80 # Average bank access latency per DRAM burst
> system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
> system.physmem.avgMemAccLat 24090.77 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1158.98 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1158.98 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
> system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
> system.physmem.busUtil 9.05 # Data bus utilization in percentage
> system.physmem.busUtilRead 9.05 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 0.44 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
> system.physmem.readRowHits 413 # Number of row buffer hits during reads
190c198
< system.physmem.readRowHitRate 89.21 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 85.68 # Row buffer hit rate for reads
192,193c200,203
< system.physmem.avgGap 54696.06 # Average gap between requests
< system.membus.throughput 1163000245 # Throughput (bytes/s)
---
> system.physmem.avgGap 54886.93 # Average gap between requests
> system.physmem.pageHitRate 85.68 # Row buffer hit rate, read and write combined
> system.physmem.prechargeAllPercent 5.39 # Percentage of time for which DRAM has all the banks in precharge state
> system.membus.throughput 1158980332 # Throughput (bytes/s)
204c214
< system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks)
206,209c216,219
< system.membus.respLayer1.occupancy 4504750 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 17.0 # Layer utilization (%)
< system.cpu.branchPred.lookups 6716 # Number of BP lookups
< system.cpu.branchPred.condPredicted 4456 # Number of conditional branches predicted
---
> system.membus.respLayer1.occupancy 4495750 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 16.9 # Layer utilization (%)
> system.cpu.branchPred.lookups 6713 # Number of BP lookups
> system.cpu.branchPred.condPredicted 4454 # Number of conditional branches predicted
211c221
< system.cpu.branchPred.BTBLookups 5022 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 5019 # Number of BTB lookups
214c224
< system.cpu.branchPred.BTBHitPct 48.426922 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 48.455868 # BTB Hit Percentage
218c228
< system.cpu.numCycles 53050 # number of cpu cycles simulated
---
> system.cpu.numCycles 53234 # number of cpu cycles simulated
221,223c231,233
< system.cpu.fetch.icacheStallCycles 12402 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 31129 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 6716 # Number of branches that fetch encountered
---
> system.cpu.fetch.icacheStallCycles 12410 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 31113 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 6713 # Number of branches that fetch encountered
225c235
< system.cpu.fetch.Cycles 9133 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 9131 # Number of cycles fetch has run and was not squashing or blocked
227c237
< system.cpu.fetch.BlockedCycles 8789 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 8795 # Number of cycles fetch has spent blocked
229,230c239,240
< system.cpu.fetch.PendingTrapStallCycles 999 # Number of stall cycles due to pending traps
< system.cpu.fetch.CacheLines 5380 # Number of cache lines fetched
---
> system.cpu.fetch.PendingTrapStallCycles 921 # Number of stall cycles due to pending traps
> system.cpu.fetch.CacheLines 5379 # Number of cache lines fetched
232,234c242,244
< system.cpu.fetch.rateDist::samples 33199 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.937649 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.130205 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 33133 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.939034 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.131220 # Number of instructions fetched each cycle (Total)
236,244c246,254
< system.cpu.fetch.rateDist::0 24066 72.49% 72.49% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 4510 13.58% 86.07% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 474 1.43% 87.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 392 1.18% 88.68% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 680 2.05% 90.73% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 706 2.13% 92.86% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 235 0.71% 93.57% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 253 0.76% 94.33% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 1883 5.67% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 24002 72.44% 72.44% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 4510 13.61% 86.05% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 474 1.43% 87.48% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 392 1.18% 88.67% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 680 2.05% 90.72% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 706 2.13% 92.85% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 235 0.71% 93.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 253 0.76% 94.32% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 1881 5.68% 100.00% # Number of instructions fetched each cycle (Total)
248,253c258,263
< system.cpu.fetch.rateDist::total 33199 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.126598 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.586786 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 13000 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 9785 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 8344 # Number of cycles decode is running
---
> system.cpu.fetch.rateDist::total 33133 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.126104 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.584457 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 12933 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 9787 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 8343 # Number of cycles decode is running
256c266
< system.cpu.decode.DecodedInsts 29016 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 29008 # Number of instructions handled by decode
258c268
< system.cpu.rename.IdleCycles 13643 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 13575 # Number of cycles rename is idle
260c270
< system.cpu.rename.serializeStallCycles 8756 # count of cycles rename stalled for serializing inst
---
> system.cpu.rename.serializeStallCycles 8758 # count of cycles rename stalled for serializing inst
285,287c295,297
< system.cpu.iq.issued_per_cycle::samples 33199 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.636224 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.261129 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 33133 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.637491 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.262113 # Number of insts issued each cycle
289,293c299,303
< system.cpu.iq.issued_per_cycle::0 23956 72.16% 72.16% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 3556 10.71% 82.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 2322 6.99% 89.86% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 1703 5.13% 94.99% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 887 2.67% 97.67% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 23891 72.11% 72.11% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 3555 10.73% 82.84% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 2321 7.01% 89.84% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 1704 5.14% 94.98% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 887 2.68% 97.66% # Number of insts issued each cycle
301c311
< system.cpu.iq.issued_per_cycle::total 33199 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 33133 # Number of insts issued each cycle
371c381
< system.cpu.iq.rate 0.398153 # Inst issue rate
---
> system.cpu.iq.rate 0.396776 # Inst issue rate
374c384
< system.cpu.iq.int_inst_queue_reads 75687 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 75621 # Number of integer instruction queue reads
415c425
< system.cpu.iew.exec_rate 0.378398 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.377090 # Inst execution rate
421c431
< system.cpu.iew.wb_rate 0.367992 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.366721 # insts written-back per cycle
427,429c437,439
< system.cpu.commit.committed_per_cycle::samples 31327 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.483991 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.181452 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 31261 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.485013 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.183057 # Number of insts commited each cycle
431,435c441,445
< system.cpu.commit.committed_per_cycle::0 24007 76.63% 76.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 4072 13.00% 89.63% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 1361 4.34% 93.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 763 2.44% 96.41% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 348 1.11% 97.52% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 23946 76.60% 76.60% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 4068 13.01% 89.61% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 1358 4.34% 93.96% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 764 2.44% 96.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 348 1.11% 97.51% # Number of insts commited each cycle
438c448
< system.cpu.commit.committed_per_cycle::7 67 0.21% 99.63% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::7 68 0.22% 99.63% # Number of insts commited each cycle
443c453
< system.cpu.commit.committed_per_cycle::total 31327 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 31261 # Number of insts commited each cycle
456c466
< system.cpu.rob.rob_reads 54596 # The number of ROB reads
---
> system.cpu.rob.rob_reads 54530 # The number of ROB reads
458,459c468,469
< system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 19851 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 20101 # Total number of cycles that the CPU has spent unscheduled due to idling
463,466c473,476
< system.cpu.cpi 3.674841 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 3.674841 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.272121 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.272121 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 3.687587 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 3.687587 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.271180 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.271180 # IPC: Total IPC of All Threads
471c481
< system.cpu.toL2Bus.throughput 1167825972 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1163789379 # Throughput (bytes/s)
486c496
< system.cpu.toL2Bus.respLayer0.occupancy 570000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 564500 # Layer occupancy (ticks)
488c498
< system.cpu.toL2Bus.respLayer1.occupancy 235750 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 234250 # Layer occupancy (ticks)
491,492c501,502
< system.cpu.icache.tags.tagsinuse 187.665560 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 4873 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 187.514405 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 4872 # Total number of references to valid blocks.
494c504
< system.cpu.icache.tags.avg_refs 14.459941 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 14.456973 # Average number of references to valid blocks.
496,504c506,514
< system.cpu.icache.tags.occ_blocks::cpu.inst 187.665560 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.091634 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.091634 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 4873 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 4873 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 4873 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 4873 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 4873 # number of overall hits
< system.cpu.icache.overall_hits::total 4873 # number of overall hits
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 187.514405 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.091560 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.091560 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 4872 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 4872 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 4872 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 4872 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 4872 # number of overall hits
> system.cpu.icache.overall_hits::total 4872 # number of overall hits
511,534c521,544
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31160500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31160500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31160500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31160500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31160500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31160500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 5380 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 5380 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 5380 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 5380 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 5380 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 5380 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094238 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.094238 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.094238 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.094238 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.094238 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.094238 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61460.552268 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61460.552268 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61460.552268 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61460.552268 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61460.552268 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31694500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31694500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31694500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31694500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31694500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31694500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 5379 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 5379 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 5379 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 5379 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 5379 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 5379 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094255 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.094255 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.094255 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.094255 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.094255 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.094255 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62513.806706 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62513.806706 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62513.806706 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62513.806706 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62513.806706 # average overall miss latency
555,572c565,582
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22334500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22334500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22334500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22334500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22334500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22334500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062639 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.062639 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062639 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.062639 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66274.480712 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66274.480712 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66274.480712 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 66274.480712 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22488500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22488500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22488500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22488500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22488500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22488500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.062651 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.062651 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.062651 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.062651 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66731.454006 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66731.454006 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66731.454006 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 66731.454006 # average overall mshr miss latency
575c585
< system.cpu.l2cache.tags.tagsinuse 221.542392 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 221.363231 # Cycle average of tags in use
580,582c590,592
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 187.054257 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 34.488135 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005708 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 186.907225 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 34.456006 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005704 # Average percentage of cache occupancy
584c594
< system.cpu.l2cache.tags.occ_percent::total 0.006761 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.006755 # Average percentage of cache occupancy
602,612c612,622
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< system.cpu.l2cache.ReadExReq_miss_latency::total 5717750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21977500 # number of demand (read+write) miss cycles
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< system.cpu.l2cache.overall_miss_latency::cpu.inst 21977500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10317750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 32295250 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22131500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5102250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 27233750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5727000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5727000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22131500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10829250 # number of demand (read+write) miss cycles
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> system.cpu.l2cache.overall_miss_latency::cpu.inst 22131500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10829250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 32960750 # number of overall miss cycles
635,645c645,655
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65604.477612 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71875 # average ReadReq miss latency
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< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68888.554217 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency
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< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65604.477612 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70188.775510 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 67002.593361 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66064.179104 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79722.656250 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 68255.012531 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69000 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69000 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 68383.298755 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66064.179104 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73668.367347 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 68383.298755 # average overall miss latency
665,675c675,685
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17752000 # number of ReadReq MSHR miss cycles
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< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4699750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17752000 # number of demand (read+write) MSHR miss cycles
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< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17752000 # number of overall MSHR miss cycles
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< system.cpu.l2cache.overall_mshr_miss_latency::total 26264750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17918000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4316250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22234250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4712000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4712000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17918000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9028250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 26946250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17918000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9028250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 26946250 # number of overall MSHR miss cycles
687,697c697,707
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52991.044776 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59578.125000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54047.619048 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56623.493976 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56623.493976 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency
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< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52991.044776 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.863946 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54491.182573 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53486.567164 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67441.406250 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55724.937343 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56771.084337 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56771.084337 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53486.567164 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61416.666667 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55905.082988 # average overall mshr miss latency
700c710
< system.cpu.dcache.tags.tagsinuse 98.809715 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 99.106073 # Cycle average of tags in use
705,707c715,717
< system.cpu.dcache.tags.occ_blocks::cpu.data 98.809715 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.024123 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.024123 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 99.106073 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.024196 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.024196 # Average percentage of cache occupancy
726,733c736,743
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7983250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7983250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 24700974 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 24700974 # number of WriteReq miss cycles
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< system.cpu.dcache.demand_miss_latency::total 32684224 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 32684224 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32684224 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8431750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8431750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 24708724 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 24708724 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 33140474 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 33140474 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 33140474 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 33140474 # number of overall miss cycles
752,759c762,769
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63359.126984 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 63359.126984 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60393.579462 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 60393.579462 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 61092.007477 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 61092.007477 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 61092.007477 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66918.650794 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 66918.650794 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60412.528117 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 60412.528117 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61944.811215 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61944.811215 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61944.811215 # average overall miss latency
784,791c794,801
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4664500 # number of ReadReq MSHR miss cycles
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< system.cpu.dcache.demand_mshr_miss_latency::total 10466250 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10466250 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10466250 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5166750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5166750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5811000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 5811000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10977750 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10977750 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10977750 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10977750 # number of overall MSHR miss cycles
800,807c810,817
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72882.812500 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72882.812500 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69900.602410 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69900.602410 # average WriteReq mshr miss latency
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< system.cpu.dcache.demand_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71198.979592 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 71198.979592 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80730.468750 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80730.468750 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70012.048193 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70012.048193 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74678.571429 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 74678.571429 # average overall mshr miss latency