7,11c7,11
< host_inst_rate 52427 # Simulator instruction rate (inst/s)
< host_op_rate 52424 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 71633039 # Simulator tick rate (ticks/s)
< host_mem_usage 221536 # Number of bytes of host memory used
< host_seconds 0.28 # Real time elapsed on the host
---
> host_inst_rate 74885 # Simulator instruction rate (inst/s)
> host_op_rate 74878 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 102311932 # Simulator tick rate (ticks/s)
> host_mem_usage 222004 # Number of bytes of host memory used
> host_seconds 0.19 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 30976 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 484 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 1568841956 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1095596242 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 1568841956 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
> system.physmem.bytes_read::total 30976 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 484 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1095596242 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 473245714 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1568841956 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1095596242 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1095596242 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1095596242 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 473245714 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1568841956 # Total bandwidth to/from this memory (bytes/s)
320a328
> system.cpu.icache.ReadReq_miss_rate::total 0.088267 # miss rate for ReadReq accesses
321a330
> system.cpu.icache.demand_miss_rate::total 0.088267 # miss rate for demand accesses
322a332
> system.cpu.icache.overall_miss_rate::total 0.088267 # miss rate for overall accesses
323a334
> system.cpu.icache.ReadReq_avg_miss_latency::total 34414.609053 # average ReadReq miss latency
324a336
> system.cpu.icache.demand_avg_miss_latency::total 34414.609053 # average overall miss latency
325a338
> system.cpu.icache.overall_avg_miss_latency::total 34414.609053 # average overall miss latency
352a366
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061751 # mshr miss rate for ReadReq accesses
353a368
> system.cpu.icache.demand_mshr_miss_rate::total 0.061751 # mshr miss rate for demand accesses
354a370
> system.cpu.icache.overall_mshr_miss_rate::total 0.061751 # mshr miss rate for overall accesses
355a372
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency
356a374
> system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency
357a376
> system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency
404a424
> system.cpu.dcache.ReadReq_miss_rate::total 0.037330 # miss rate for ReadReq accesses
405a426
> system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses
406a428
> system.cpu.dcache.demand_miss_rate::total 0.114273 # miss rate for demand accesses
407a430
> system.cpu.dcache.overall_miss_rate::total 0.114273 # miss rate for overall accesses
408a432
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34682.203390 # average ReadReq miss latency
409a434
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35768.382353 # average WriteReq miss latency
410a436
> system.cpu.dcache.demand_avg_miss_latency::total 35524.714829 # average overall miss latency
411a438
> system.cpu.dcache.overall_avg_miss_latency::total 35524.714829 # average overall miss latency
444a472
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019930 # mshr miss rate for ReadReq accesses
445a474
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
446a476
> system.cpu.dcache.demand_mshr_miss_rate::total 0.031718 # mshr miss rate for demand accesses
447a478
> system.cpu.dcache.overall_mshr_miss_rate::total 0.031718 # mshr miss rate for overall accesses
448a480
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency
449a482
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35897.590361 # average WriteReq mshr miss latency
450a484
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency
451a486
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency
504a540
> system.cpu.l2cache.ReadReq_miss_rate::total 0.995037 # miss rate for ReadReq accesses
505a542
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
507a545
> system.cpu.l2cache.demand_miss_rate::total 0.995885 # miss rate for demand accesses
509a548
> system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses
511a551
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34293.017456 # average ReadReq miss latency
512a553
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency
514a556
> system.cpu.l2cache.demand_avg_miss_latency::total 34339.876033 # average overall miss latency
516a559
> system.cpu.l2cache.overall_avg_miss_latency::total 34339.876033 # average overall miss latency
548a592
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses
549a594
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
551a597
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 # mshr miss rate for demand accesses
553a600
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses
555a603
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.034913 # average ReadReq mshr miss latency
556a605
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency
558a608
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency
560a611
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency
< host_inst_rate 52427 # Simulator instruction rate (inst/s)
< host_op_rate 52424 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 71633039 # Simulator tick rate (ticks/s)
< host_mem_usage 221536 # Number of bytes of host memory used
< host_seconds 0.28 # Real time elapsed on the host
---
> host_inst_rate 74885 # Simulator instruction rate (inst/s)
> host_op_rate 74878 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 102311932 # Simulator tick rate (ticks/s)
> host_mem_usage 222004 # Number of bytes of host memory used
> host_seconds 0.19 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 30976 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 21632 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 484 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 1568841956 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1095596242 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 1568841956 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory
> system.physmem.bytes_read::total 30976 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 484 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1095596242 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 473245714 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1568841956 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1095596242 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1095596242 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1095596242 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 473245714 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1568841956 # Total bandwidth to/from this memory (bytes/s)
320a328
> system.cpu.icache.ReadReq_miss_rate::total 0.088267 # miss rate for ReadReq accesses
321a330
> system.cpu.icache.demand_miss_rate::total 0.088267 # miss rate for demand accesses
322a332
> system.cpu.icache.overall_miss_rate::total 0.088267 # miss rate for overall accesses
323a334
> system.cpu.icache.ReadReq_avg_miss_latency::total 34414.609053 # average ReadReq miss latency
324a336
> system.cpu.icache.demand_avg_miss_latency::total 34414.609053 # average overall miss latency
325a338
> system.cpu.icache.overall_avg_miss_latency::total 34414.609053 # average overall miss latency
352a366
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061751 # mshr miss rate for ReadReq accesses
353a368
> system.cpu.icache.demand_mshr_miss_rate::total 0.061751 # mshr miss rate for demand accesses
354a370
> system.cpu.icache.overall_mshr_miss_rate::total 0.061751 # mshr miss rate for overall accesses
355a372
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency
356a374
> system.cpu.icache.demand_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency
357a376
> system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency
404a424
> system.cpu.dcache.ReadReq_miss_rate::total 0.037330 # miss rate for ReadReq accesses
405a426
> system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses
406a428
> system.cpu.dcache.demand_miss_rate::total 0.114273 # miss rate for demand accesses
407a430
> system.cpu.dcache.overall_miss_rate::total 0.114273 # miss rate for overall accesses
408a432
> system.cpu.dcache.ReadReq_avg_miss_latency::total 34682.203390 # average ReadReq miss latency
409a434
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35768.382353 # average WriteReq miss latency
410a436
> system.cpu.dcache.demand_avg_miss_latency::total 35524.714829 # average overall miss latency
411a438
> system.cpu.dcache.overall_avg_miss_latency::total 35524.714829 # average overall miss latency
444a472
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019930 # mshr miss rate for ReadReq accesses
445a474
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
446a476
> system.cpu.dcache.demand_mshr_miss_rate::total 0.031718 # mshr miss rate for demand accesses
447a478
> system.cpu.dcache.overall_mshr_miss_rate::total 0.031718 # mshr miss rate for overall accesses
448a480
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency
449a482
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35897.590361 # average WriteReq mshr miss latency
450a484
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency
451a486
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency
504a540
> system.cpu.l2cache.ReadReq_miss_rate::total 0.995037 # miss rate for ReadReq accesses
505a542
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
507a545
> system.cpu.l2cache.demand_miss_rate::total 0.995885 # miss rate for demand accesses
509a548
> system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses
511a551
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34293.017456 # average ReadReq miss latency
512a553
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency
514a556
> system.cpu.l2cache.demand_avg_miss_latency::total 34339.876033 # average overall miss latency
516a559
> system.cpu.l2cache.overall_avg_miss_latency::total 34339.876033 # average overall miss latency
548a592
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses
549a594
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
551a597
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 # mshr miss rate for demand accesses
553a600
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses
555a603
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.034913 # average ReadReq mshr miss latency
556a605
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency
558a608
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency
560a611
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency