4,5c4,5
< sim_ticks 29908500 # Number of ticks simulated
< final_tick 29908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 29673500 # Number of ticks simulated
> final_tick 29673500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 19226 # Simulator instruction rate (inst/s)
< host_op_rate 19225 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 39829510 # Simulator tick rate (ticks/s)
< host_mem_usage 234412 # Number of bytes of host memory used
< host_seconds 0.75 # Real time elapsed on the host
---
> host_inst_rate 97740 # Simulator instruction rate (inst/s)
> host_op_rate 97731 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 200871294 # Simulator tick rate (ticks/s)
> host_mem_usage 251556 # Number of bytes of host memory used
> host_seconds 0.15 # Real time elapsed on the host
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 23360 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory
19,22c19,22
< system.physmem.bytes_read::total 32768 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 23360 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 23360 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 365 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 32640 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory
24,33c24,33
< system.physmem.num_reads::total 512 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 781048866 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 314559406 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1095608272 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 781048866 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 781048866 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 781048866 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 314559406 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1095608272 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 513 # Number of read requests accepted
---
> system.physmem.num_reads::total 510 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 782920788 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 317050567 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1099971355 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 782920788 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 782920788 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 782920788 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 317050567 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1099971355 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 511 # Number of read requests accepted
35c35
< system.physmem.readBursts 513 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 511 # Number of DRAM read bursts, including those serviced by the write queue
37c37
< system.physmem.bytesReadDRAM 32832 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 32704 # Total number of bytes read from DRAM
40c40
< system.physmem.bytesReadSys 32832 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 32704 # Total read bytes from the system interface side
45c45
< system.physmem.perBankRdBursts::0 105 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 104 # Per bank write bursts
47,49c47,49
< system.physmem.perBankRdBursts::2 55 # Per bank write bursts
< system.physmem.perBankRdBursts::3 27 # Per bank write bursts
< system.physmem.perBankRdBursts::4 23 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 54 # Per bank write bursts
> system.physmem.perBankRdBursts::3 28 # Per bank write bursts
> system.physmem.perBankRdBursts::4 22 # Per bank write bursts
79c79
< system.physmem.totGap 29877000 # Total gap between requests
---
> system.physmem.totGap 29642000 # Total gap between requests
86c86
< system.physmem.readPktSize::6 513 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 511 # Read request sizes (log2)
95c95
< system.physmem.rdQLenPdf::1 156 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see
97,99c97,99
< system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
191,193c191,193
< system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 253.933476 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 348.475070 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 393.025641 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 252.718123 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 347.605052 # Bytes accessed per row activation
195,197c195,197
< system.physmem.bytesPerActivate::128-255 19 24.36% 46.15% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 12 15.38% 61.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 5 6.41% 67.95% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::128-255 18 23.08% 44.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 14 17.95% 62.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 4 5.13% 67.95% # Bytes accessed per row activation
200,201c200
< system.physmem.bytesPerActivate::768-895 6 7.69% 83.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1 1.28% 84.62% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::768-895 7 8.97% 84.62% # Bytes accessed per row activation
204,207c203,206
< system.physmem.totQLat 6719500 # Total ticks spent queuing
< system.physmem.totMemAccLat 16338250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 2565000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 13098.44 # Average queueing delay per DRAM burst
---
> system.physmem.totQLat 6610250 # Total ticks spent queuing
> system.physmem.totMemAccLat 16191500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 2555000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 12935.91 # Average queueing delay per DRAM burst
209,210c208,209
< system.physmem.avgMemAccLat 31848.44 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1097.75 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 31685.91 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1102.13 # Average DRAM read bandwidth in MiByte/s
212c211
< system.physmem.avgRdBWSys 1097.75 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1102.13 # Average system read bandwidth in MiByte/s
215,216c214,215
< system.physmem.busUtil 8.58 # Data bus utilization in percentage
< system.physmem.busUtilRead 8.58 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 8.61 # Data bus utilization in percentage
> system.physmem.busUtilRead 8.61 # Data bus utilization in percentage for reads
220c219
< system.physmem.readRowHits 424 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 422 # Number of row buffer hits during reads
222c221
< system.physmem.readRowHitRate 82.65 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads
224,226c223,225
< system.physmem.avgGap 58239.77 # Average gap between requests
< system.physmem.pageHitRate 82.65 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 357000 # Energy for activate commands per rank (pJ)
---
> system.physmem.avgGap 58007.83 # Average gap between requests
> system.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 364140 # Energy for activate commands per rank (pJ)
228c227
< system.physmem_0.readEnergy 2199120 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 2184840 # Energy for read commands per rank (pJ)
231c230
< system.physmem_0.actBackEnergy 3644010 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 3606960 # Energy for active background per rank (pJ)
233,234c232,233
< system.physmem_0.actPowerDownEnergy 9899190 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 16800 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 9847320 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
236,238c235,237
< system.physmem_0.totalEnergy 18197970 # Total energy per rank (pJ)
< system.physmem_0.averagePower 608.449701 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 21617000 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalEnergy 18086550 # Total energy per rank (pJ)
> system.physmem_0.averagePower 609.513459 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 21469250 # Total Idle time Per DRAM Rank
242,245c241,244
< system.physmem_0.memoryStateTime::PRE_PDN 44000 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 7338500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 21705500 # Time in different power states
< system.physmem_1.actEnergy 278460 # Energy for activate commands per rank (pJ)
---
> system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 7251250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 21598000 # Time in different power states
> system.physmem_1.actEnergy 271320 # Energy for activate commands per rank (pJ)
250,253c249,252
< system.physmem_1.actBackEnergy 2521680 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 86880 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 10427010 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 493920 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actBackEnergy 2504580 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 86400 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 10184760 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 622560 # Energy for precharge power-down per rank (pJ)
255,257c254,256
< system.physmem_1.totalEnergy 17237010 # Total energy per rank (pJ)
< system.physmem_1.averagePower 576.319973 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 24154250 # Total Idle time Per DRAM Rank
---
> system.physmem_1.totalEnergy 17098680 # Total energy per rank (pJ)
> system.physmem_1.averagePower 576.222419 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 23952750 # Total Idle time Per DRAM Rank
261,268c260,267
< system.physmem_1.memoryStateTime::PRE_PDN 1286000 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 4831250 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 22868250 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 12304 # Number of BP lookups
< system.cpu.branchPred.condPredicted 7429 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 1435 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 9156 # Number of BTB lookups
---
> system.physmem_1.memoryStateTime::PRE_PDN 1619750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 4797750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 22333000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 11901 # Number of BP lookups
> system.cpu.branchPred.condPredicted 7287 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 1354 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 9352 # Number of BTB lookups
272c271
< system.cpu.branchPred.usedRAS 730 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.usedRAS 685 # Number of times the RAS was used to get a target.
274,277c273,276
< system.cpu.branchPred.indirectLookups 9156 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 1824 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 7332 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 865 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectLookups 9352 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 1949 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 7403 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 793 # Number of mispredicted indirect branches.
280,281c279,280
< system.cpu.pwrStateResidencyTicks::ON 29908500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 59818 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 29673500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 59348 # number of cpu cycles simulated
284,291c283,291
< system.cpu.fetch.icacheStallCycles 15502 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 57440 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 12304 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 2554 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 17524 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 3065 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 1117 # Number of stall cycles due to pending traps
---
> system.cpu.fetch.icacheStallCycles 15163 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 55604 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 11901 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 2634 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 17364 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 2905 # Number of cycles fetch has spent squashing
> system.cpu.fetch.TlbCycles 12 # Number of cycles fetch has spent waiting for tlb
> system.cpu.fetch.MiscStallCycles 9 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 1168 # Number of stall cycles due to pending traps
293,297c293,298
< system.cpu.fetch.CacheLines 7446 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 730 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 35692 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.609324 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.874327 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 7191 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 701 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
> system.cpu.fetch.rateDist::samples 35180 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.580557 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.839184 # Number of instructions fetched each cycle (Total)
299,307c300,308
< system.cpu.fetch.rateDist::0 23194 64.98% 64.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 4479 12.55% 77.53% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 496 1.39% 78.92% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 441 1.24% 80.16% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 761 2.13% 82.29% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 680 1.91% 84.20% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 284 0.80% 84.99% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 358 1.00% 85.99% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 4999 14.01% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 22867 65.00% 65.00% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 4490 12.76% 77.76% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 508 1.44% 79.21% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 450 1.28% 80.49% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 761 2.16% 82.65% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 731 2.08% 84.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 296 0.84% 85.57% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 343 0.97% 86.54% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 4734 13.46% 100.00% # Number of instructions fetched each cycle (Total)
311,327c312,328
< system.cpu.fetch.rateDist::total 35692 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.205691 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.960246 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 12333 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 13299 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 7732 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 1532 # Number of cycles decode is squashing
< system.cpu.decode.DecodedInsts 41071 # Number of instructions handled by decode
< system.cpu.rename.SquashCycles 1532 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 13082 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 2036 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 9748 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 7750 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1544 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 36233 # Number of instructions processed by rename
< system.cpu.rename.IQFullEvents 13 # Number of times rename has blocked due to IQ full
---
> system.cpu.fetch.rateDist::total 35180 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.200529 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.936914 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 12094 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 13233 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 7639 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 762 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 1452 # Number of cycles decode is squashing
> system.cpu.decode.DecodedInsts 39805 # Number of instructions handled by decode
> system.cpu.rename.SquashCycles 1452 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 12828 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 9904 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 7640 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1543 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 35279 # Number of instructions processed by rename
> system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full
329,331c330,332
< system.cpu.rename.RenamedOperands 31392 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 65112 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 53717 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 30611 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 63420 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 52396 # Number of integer rename lookups
333,339c334,340
< system.cpu.rename.UndoneMaps 17573 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 793 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 793 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 4281 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 4496 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 2885 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads.
---
> system.cpu.rename.UndoneMaps 16792 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 761 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 767 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 4154 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 4391 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 2803 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads.
341,350c342,351
< system.cpu.iq.iqInstsAdded 28450 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 744 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 25030 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 14758 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 11000 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 269 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 35692 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.701278 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.501683 # Number of insts issued each cycle
---
> system.cpu.iq.iqInstsAdded 27854 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 724 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 24627 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 122 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 14142 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 10452 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 249 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 35180 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.700028 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.493682 # Number of insts issued each cycle
352,360c353,361
< system.cpu.iq.issued_per_cycle::0 26611 74.56% 74.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 3173 8.89% 83.45% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1585 4.44% 87.89% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 1525 4.27% 92.16% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 1196 3.35% 95.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 748 2.10% 97.61% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 484 1.36% 98.96% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 276 0.77% 99.74% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 94 0.26% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 26218 74.53% 74.53% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 3125 8.88% 83.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1567 4.45% 87.86% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 1507 4.28% 92.15% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1190 3.38% 95.53% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 757 2.15% 97.68% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 486 1.38% 99.06% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 254 0.72% 99.78% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 76 0.22% 100.00% # Number of insts issued each cycle
364c365
< system.cpu.iq.issued_per_cycle::total 35692 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 35180 # Number of insts issued each cycle
366,398c367,399
< system.cpu.iq.fu_full::IntAlu 164 53.07% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 53 17.15% 70.23% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 92 29.77% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 151 52.07% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.07% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 51 17.59% 69.66% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 88 30.34% 100.00% # attempts to use FU when none available
404,436c405,437
< system.cpu.iq.FU_type_0::IntAlu 18344 73.29% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.29% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 4185 16.72% 90.01% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 2501 9.99% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 18085 73.44% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.44% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 4096 16.63% 90.07% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 2446 9.93% 100.00% # Type of FU issued
441,447c442,448
< system.cpu.iq.FU_type_0::total 25030 # Type of FU issued
< system.cpu.iq.rate 0.418436 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 309 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 86193 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 43979 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 22369 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 24627 # Type of FU issued
> system.cpu.iq.rate 0.414959 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 290 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.011776 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 84846 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 42748 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 22066 # Number of integer instruction queue wakeup accesses
451c452
< system.cpu.iq.int_alu_accesses 25339 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 24917 # Number of integer alu accesses
455c456
< system.cpu.iew.lsq.thread0.squashedLoads 2271 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 2166 # Number of loads squashed
457,458c458,459
< system.cpu.iew.lsq.thread0.memOrderViolation 28 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.memOrderViolation 29 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 1355 # Number of stores squashed
464,471c465,472
< system.cpu.iew.iewSquashCycles 1532 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 2073 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 30726 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 235 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 4496 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 2885 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 744 # Number of dispatched non-speculative instructions
---
> system.cpu.iew.iewSquashCycles 1452 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 1841 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 30085 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 231 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 4391 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 2803 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 724 # Number of dispatched non-speculative instructions
474,480c475,481
< system.cpu.iew.memOrderViolationEvents 28 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 207 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 1574 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1781 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 23432 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 3882 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 1598 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 209 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 1460 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1669 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 23080 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 3816 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 1547 # Number of squashed instructions skipped in execute
482,493c483,494
< system.cpu.iew.exec_nop 1532 # number of nop insts executed
< system.cpu.iew.exec_refs 6190 # number of memory reference insts executed
< system.cpu.iew.exec_branches 4984 # Number of branches executed
< system.cpu.iew.exec_stores 2308 # Number of stores executed
< system.cpu.iew.exec_rate 0.391722 # Inst execution rate
< system.cpu.iew.wb_sent 22840 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 22369 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 10409 # num instructions producing a value
< system.cpu.iew.wb_consumers 13648 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.373951 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.762676 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 15475 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 1507 # number of nop insts executed
> system.cpu.iew.exec_refs 6070 # number of memory reference insts executed
> system.cpu.iew.exec_branches 4884 # Number of branches executed
> system.cpu.iew.exec_stores 2254 # Number of stores executed
> system.cpu.iew.exec_rate 0.388893 # Inst execution rate
> system.cpu.iew.wb_sent 22529 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 22066 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 10367 # num instructions producing a value
> system.cpu.iew.wb_consumers 13651 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.371807 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.759432 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 14855 # The number of squashed insts skipped by commit
495,498c496,499
< system.cpu.commit.branchMispredicts 1435 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 32615 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.464878 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.257144 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 1354 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 32262 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.469965 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.260994 # Number of insts commited each cycle
500,508c501,509
< system.cpu.commit.committed_per_cycle::0 25974 79.64% 79.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 3555 10.90% 90.54% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 1191 3.65% 94.19% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 577 1.77% 95.96% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 319 0.98% 96.94% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 311 0.95% 97.89% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 392 1.20% 99.09% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 57 0.17% 99.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 239 0.73% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 25609 79.38% 79.38% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 3577 11.09% 90.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 1157 3.59% 94.05% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 603 1.87% 95.92% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 332 1.03% 96.95% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 298 0.92% 97.87% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 393 1.22% 99.09% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 58 0.18% 99.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 235 0.73% 100.00% # Number of insts commited each cycle
512c513
< system.cpu.commit.committed_per_cycle::total 32615 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 32262 # Number of insts commited each cycle
562,564c563,565
< system.cpu.commit.bw_lim_events 239 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 62190 # The number of ROB reads
< system.cpu.rob.rob_writes 64431 # The number of ROB writes
---
> system.cpu.commit.bw_lim_events 235 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 61221 # The number of ROB reads
> system.cpu.rob.rob_writes 63021 # The number of ROB writes
566c567
< system.cpu.idleCycles 24126 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 24168 # Total number of cycles that the CPU has spent unscheduled due to idling
569,575c570,576
< system.cpu.cpi 4.143669 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 4.143669 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.241332 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.241332 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 36473 # number of integer regfile reads
< system.cpu.int_regfile_writes 20293 # number of integer regfile writes
< system.cpu.misc_regfile_reads 8093 # number of misc regfile reads
---
> system.cpu.cpi 4.111111 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 4.111111 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.243243 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.243243 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 36173 # number of integer regfile reads
> system.cpu.int_regfile_writes 20126 # number of integer regfile writes
> system.cpu.misc_regfile_reads 7956 # number of misc regfile reads
577c578
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states
579,580c580,581
< system.cpu.dcache.tags.tagsinuse 99.156027 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 4579 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 98.931439 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 4528 # Total number of references to valid blocks.
582c583
< system.cpu.dcache.tags.avg_refs 31.363014 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 31.013699 # Average number of references to valid blocks.
584,586c585,587
< system.cpu.dcache.tags.occ_blocks::cpu.data 99.156027 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.024208 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.024208 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 98.931439 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.024153 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.024153 # Average percentage of cache occupancy
591,595c592,596
< system.cpu.dcache.tags.tag_accesses 10412 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 10412 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 3540 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 3540 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 10292 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 10292 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 3489 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 3489 # number of ReadReq hits
600,605c601,606
< system.cpu.dcache.demand_hits::cpu.data 4573 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 4573 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 4573 # number of overall hits
< system.cpu.dcache.overall_hits::total 4573 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 145 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 145 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 4522 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 4522 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 4522 # number of overall hits
> system.cpu.dcache.overall_hits::total 4522 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses
608,621c609,622
< system.cpu.dcache.demand_misses::cpu.data 554 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 554 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 554 # number of overall misses
< system.cpu.dcache.overall_misses::total 554 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11443500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11443500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 29003985 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 29003985 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 40447485 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 40447485 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 40447485 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 40447485 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 3685 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 3685 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 545 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 545 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 545 # number of overall misses
> system.cpu.dcache.overall_misses::total 545 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10734500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10734500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 29028485 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 29028485 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 39762985 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 39762985 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 39762985 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 39762985 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 3625 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 3625 # number of ReadReq accesses(hits+misses)
626,631c627,632
< system.cpu.dcache.demand_accesses::cpu.data 5127 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 5127 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 5127 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 5127 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039349 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.039349 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 5067 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 5067 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 5067 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 5067 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037517 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.037517 # miss rate for ReadReq accesses
634,645c635,646
< system.cpu.dcache.demand_miss_rate::cpu.data 0.108055 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.108055 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.108055 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.108055 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78920.689655 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 78920.689655 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70914.388753 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 70914.388753 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 73009.900722 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 73009.900722 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 73009.900722 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.107559 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.107559 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.107559 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.107559 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78930.147059 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 78930.147059 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70974.290954 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 70974.290954 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 72959.605505 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 72959.605505 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 72959.605505 # average overall miss latency
652,653c653,654
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 71 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
656,659c657,660
< system.cpu.dcache.demand_mshr_hits::cpu.data 406 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 406 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 406 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 406 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 397 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 397 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 397 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 397 # number of overall MSHR hits
668,677c669,678
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6078000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 6078000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6888000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6888000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12966000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12966000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12966000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12966000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017639 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017639 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6080000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 6080000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6906500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6906500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12986500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12986500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12986500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12986500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017931 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017931 # mshr miss rate for ReadReq accesses
680,692c681,693
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.028867 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028867 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.028867 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93507.692308 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93507.692308 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82987.951807 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82987.951807 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87608.108108 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 87608.108108 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.029209 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029209 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.029209 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93538.461538 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93538.461538 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83210.843373 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83210.843373 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87746.621622 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 87746.621622 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states
694,697c695,698
< system.cpu.icache.tags.tagsinuse 204.744610 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 6856 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 18.681199 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 202.053622 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 6606 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 18.098630 # Average number of references to valid blocks.
699,745c700,746
< system.cpu.icache.tags.occ_blocks::cpu.inst 204.744610 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.099973 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.099973 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.179199 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 15259 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 15259 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 6856 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 6856 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 6856 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 6856 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 6856 # number of overall hits
< system.cpu.icache.overall_hits::total 6856 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 590 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 590 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 590 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 590 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 590 # number of overall misses
< system.cpu.icache.overall_misses::total 590 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 45890500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 45890500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 45890500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 45890500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 45890500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 45890500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 7446 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 7446 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 7446 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 7446 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 7446 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 7446 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.079237 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.079237 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.079237 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.079237 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.079237 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.079237 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77780.508475 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77780.508475 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77780.508475 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77780.508475 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 123 # number of cycles access was blocked
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 202.053622 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.098659 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.098659 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 14747 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 14747 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 6606 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 6606 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 6606 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 6606 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 6606 # number of overall hits
> system.cpu.icache.overall_hits::total 6606 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 585 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 585 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 585 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 585 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 585 # number of overall misses
> system.cpu.icache.overall_misses::total 585 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 45161000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 45161000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 45161000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 45161000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 45161000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 45161000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 7191 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 7191 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 7191 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 7191 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 7191 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 7191 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081352 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.081352 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.081352 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.081352 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.081352 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.081352 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77198.290598 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77198.290598 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77198.290598 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77198.290598 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77198.290598 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 127 # number of cycles access was blocked
747c748
< system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked
749c750
< system.cpu.icache.avg_blocked_cycles::no_mshrs 123 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 63.500000 # average number of cycles each access was blocked
751,781c752,782
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 223 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 223 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 223 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 223 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 367 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 367 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 367 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 367 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30255500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 30255500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30255500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 30255500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30255500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 30255500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049288 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.049288 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049288 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.049288 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82440.054496 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82440.054496 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 220 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 220 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 220 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 220 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 220 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 220 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29981500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 29981500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29981500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 29981500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29981500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 29981500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050758 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.050758 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050758 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.050758 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82141.095890 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82141.095890 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82141.095890 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 82141.095890 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states
783c784
< system.cpu.l2cache.tags.tagsinuse 303.310888 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 300.398022 # Cycle average of tags in use
785,786c786,787
< system.cpu.l2cache.tags.sampled_refs 511 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.003914 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks.
788,799c789,800
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.103605 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 99.207284 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006229 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.003028 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.009256 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015594 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 4631 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 4631 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 201.414921 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 98.983101 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006147 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.003021 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.009167 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 4613 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 4613 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states
808,809c809,810
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 365 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 365 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses
812c813
< system.cpu.l2cache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses
814,815c815,816
< system.cpu.l2cache.demand_misses::total 513 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 365 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 511 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses
817,829c818,830
< system.cpu.l2cache.overall_misses::total 513 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6762500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6762500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29682000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 29682000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5983000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5983000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 29682000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12745500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 42427500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 29682000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12745500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 42427500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::total 511 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6781000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6781000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29411000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 29411000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5985000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 5985000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 29411000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12766000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 42177000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 29411000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12766000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 42177000 # number of overall miss cycles
832,833c833,834
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 367 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 367 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 365 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 365 # number of ReadCleanReq accesses(hits+misses)
836c837
< system.cpu.l2cache.demand_accesses::cpu.inst 367 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses
838,839c839,840
< system.cpu.l2cache.demand_accesses::total 515 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 367 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 513 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses
841c842
< system.cpu.l2cache.overall_accesses::total 515 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 513 # number of overall (read+write) accesses
844,845c845,846
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994550 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994550 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994521 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994521 # miss rate for ReadCleanReq accesses
848c849
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994550 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994521 # miss rate for demand accesses
850,851c851,852
< system.cpu.l2cache.demand_miss_rate::total 0.996117 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994550 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.996101 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994521 # miss rate for overall accesses
853,865c854,866
< system.cpu.l2cache.overall_miss_rate::total 0.996117 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81475.903614 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81475.903614 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.547945 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.547945 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92046.153846 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92046.153846 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 82704.678363 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86118.243243 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 82704.678363 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.996101 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81698.795181 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81698.795181 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81022.038567 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81022.038567 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92076.923077 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92076.923077 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 82538.160470 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81022.038567 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86256.756757 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 82538.160470 # average overall miss latency
874,875c875,876
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 365 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 365 # number of ReadCleanReq MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses
878c879
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses
880,881c881,882
< system.cpu.l2cache.demand_mshr_misses::total 513 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 511 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses
883,895c884,896
< system.cpu.l2cache.overall_mshr_misses::total 513 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5932500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5932500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26032000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26032000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5353000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5353000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26032000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11285500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 37317500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26032000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11285500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 37317500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::total 511 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5951000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5951000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 25781000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 25781000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5355000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5355000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25781000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11306000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 37087000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25781000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11306000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 37087000 # number of overall MSHR miss cycles
898,899c899,900
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994550 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994521 # mshr miss rate for ReadCleanReq accesses
902c903
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for demand accesses
904,905c905,906
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.996117 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994550 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.996101 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994521 # mshr miss rate for overall accesses
907,920c908,921
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.996117 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71475.903614 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71475.903614 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71320.547945 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71320.547945 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82353.846154 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82353.846154 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76253.378378 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 515 # Total number of requests made to the snoop filter.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.996101 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71698.795181 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71698.795181 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71022.038567 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71022.038567 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82384.615385 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82384.615385 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71022.038567 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76391.891892 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72577.299413 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter.
926,927c927,928
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 428 # Transaction distribution
930c931
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 367 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 365 # Transaction distribution
932c933
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 734 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes)
934,935c935,936
< system.cpu.toL2Bus.pkt_count::total 1028 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 1024 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes)
937c938
< system.cpu.toL2Bus.pkt_size::total 32832 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes)
940,942c941,943
< system.cpu.toL2Bus.snoop_fanout::samples 515 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.003883 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.062257 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 513 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.003899 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.062378 # Request fanout histogram
944c945
< system.cpu.toL2Bus.snoop_fanout::0 513 99.61% 99.61% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 511 99.61% 99.61% # Request fanout histogram
950,951c951,952
< system.cpu.toL2Bus.snoop_fanout::total 515 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 257500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 513 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 256500 # Layer occupancy (ticks)
953c954
< system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 547500 # Layer occupancy (ticks)
957c958
< system.membus.snoop_filter.tot_requests 513 # Total number of requests made to the snoop filter.
---
> system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
963,964c964,965
< system.membus.pwrStateResidencyTicks::UNDEFINED 29908500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 428 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 29673500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 426 # Transaction distribution
967,971c968,972
< system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1024 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1024 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32704 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 32704 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 428 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1020 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1020 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 32576 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 32576 # Cumulative packet size per connected master and slave (bytes)
974c975
< system.membus.snoop_fanout::samples 513 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 511 # Request fanout histogram
978c979
< system.membus.snoop_fanout::0 513 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 511 100.00% 100.00% # Request fanout histogram
983,984c984,985
< system.membus.snoop_fanout::total 513 # Request fanout histogram
< system.membus.reqLayer0.occupancy 627500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 511 # Request fanout histogram
> system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks)
986c987
< system.membus.respLayer1.occupancy 2707250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2697250 # Layer occupancy (ticks)