7,11c7,11
< host_inst_rate 90593 # Simulator instruction rate (inst/s)
< host_op_rate 90586 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 187662601 # Simulator tick rate (ticks/s)
< host_mem_usage 251772 # Number of bytes of host memory used
< host_seconds 0.16 # Real time elapsed on the host
---
> host_inst_rate 19226 # Simulator instruction rate (inst/s)
> host_op_rate 19225 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 39829510 # Simulator tick rate (ticks/s)
> host_mem_usage 234412 # Number of bytes of host memory used
> host_seconds 0.75 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 6721500 # Total ticks spent queuing
< system.physmem.totMemAccLat 16340250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6719500 # Total ticks spent queuing
> system.physmem.totMemAccLat 16338250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 13102.34 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13098.44 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 31852.34 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 31848.44 # Average memory access latency per DRAM burst
231c231
< system.physmem_0.actBackEnergy 3642300 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 3644010 # Energy for active background per rank (pJ)
233c233
< system.physmem_0.actPowerDownEnergy 9900900 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 9899190 # Energy for active power-down per rank (pJ)
250c250
< system.physmem_1.actBackEnergy 2522250 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 2521680 # Energy for active background per rank (pJ)
252c252
< system.physmem_1.actPowerDownEnergy 10426440 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 10427010 # Energy for active power-down per rank (pJ)
343c343
< system.cpu.iq.iqInstsIssued 25032 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 25030 # Number of instructions issued
346c346
< system.cpu.iq.iqSquashedOperandsExamined 10993 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedOperandsExamined 11000 # Number of squashed operands that are examined and possibly removed from graph
349,350c349,350
< system.cpu.iq.issued_per_cycle::mean 0.701334 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.501806 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::mean 0.701278 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.501683 # Number of insts issued each cycle
352,354c352,354
< system.cpu.iq.issued_per_cycle::0 26613 74.56% 74.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 3169 8.88% 83.44% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1586 4.44% 87.89% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 26611 74.56% 74.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 3173 8.89% 83.45% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1585 4.44% 87.89% # Number of insts issued each cycle
356c356
< system.cpu.iq.issued_per_cycle::4 1197 3.35% 95.51% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::4 1196 3.35% 95.51% # Number of insts issued each cycle
404c404
< system.cpu.iq.FU_type_0::IntAlu 18346 73.29% 73.29% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 18344 73.29% 73.29% # Type of FU issued
441,442c441,442
< system.cpu.iq.FU_type_0::total 25032 # Type of FU issued
< system.cpu.iq.rate 0.418469 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 25030 # Type of FU issued
> system.cpu.iq.rate 0.418436 # Inst issue rate
444,445c444,445
< system.cpu.iq.fu_busy_rate 0.012344 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 86197 # Number of integer instruction queue reads
---
> system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 86193 # Number of integer instruction queue reads
447c447
< system.cpu.iq.int_inst_queue_wakeup_accesses 22374 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_wakeup_accesses 22369 # Number of integer instruction queue wakeup accesses
451c451
< system.cpu.iq.int_alu_accesses 25341 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 25339 # Number of integer alu accesses
476,478c476,478
< system.cpu.iew.predictedNotTakenIncorrect 1575 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1782 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 23436 # Number of executed instructions
---
> system.cpu.iew.predictedNotTakenIncorrect 1574 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1781 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 23432 # Number of executed instructions
480c480
< system.cpu.iew.iewExecSquashedInsts 1596 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 1598 # Number of squashed instructions skipped in execute
483,492c483,492
< system.cpu.iew.exec_refs 6191 # number of memory reference insts executed
< system.cpu.iew.exec_branches 4986 # Number of branches executed
< system.cpu.iew.exec_stores 2309 # Number of stores executed
< system.cpu.iew.exec_rate 0.391788 # Inst execution rate
< system.cpu.iew.wb_sent 22845 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 22374 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 10411 # num instructions producing a value
< system.cpu.iew.wb_consumers 13650 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.374035 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.762711 # average fanout of values written-back
---
> system.cpu.iew.exec_refs 6190 # number of memory reference insts executed
> system.cpu.iew.exec_branches 4984 # Number of branches executed
> system.cpu.iew.exec_stores 2308 # Number of stores executed
> system.cpu.iew.exec_rate 0.391722 # Inst execution rate
> system.cpu.iew.wb_sent 22840 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 22369 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 10409 # num instructions producing a value
> system.cpu.iew.wb_consumers 13648 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.373951 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.762676 # average fanout of values written-back
573,575c573,575
< system.cpu.int_regfile_reads 36480 # number of integer regfile reads
< system.cpu.int_regfile_writes 20296 # number of integer regfile writes
< system.cpu.misc_regfile_reads 8094 # number of misc regfile reads
---
> system.cpu.int_regfile_reads 36473 # number of integer regfile reads
> system.cpu.int_regfile_writes 20293 # number of integer regfile writes
> system.cpu.misc_regfile_reads 8093 # number of misc regfile reads
579c579
< system.cpu.dcache.tags.tagsinuse 99.158435 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 99.156027 # Cycle average of tags in use
584,586c584,586
< system.cpu.dcache.tags.occ_blocks::cpu.data 99.158435 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.024209 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.024209 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 99.156027 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.024208 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.024208 # Average percentage of cache occupancy
694c694
< system.cpu.icache.tags.tagsinuse 204.747820 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 204.744610 # Cycle average of tags in use
699,701c699,701
< system.cpu.icache.tags.occ_blocks::cpu.inst 204.747820 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.099975 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.099975 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 204.744610 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.099973 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.099973 # Average percentage of cache occupancy
721,726c721,726
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 45891500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 45891500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 45891500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 45891500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 45891500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 45891500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 45890500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 45890500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 45890500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 45890500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 45890500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 45890500 # number of overall miss cycles
739,744c739,744
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77782.203390 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77782.203390 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77782.203390 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77782.203390 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77780.508475 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77780.508475 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77780.508475 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77780.508475 # average overall miss latency
763,768c763,768
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30257500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 30257500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30257500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30257500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30255500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 30255500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30255500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 30255500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30255500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 30255500 # number of overall MSHR miss cycles
775,780c775,780
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82445.504087 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82445.504087 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82440.054496 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82440.054496 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency
783c783
< system.cpu.l2cache.tags.tagsinuse 303.316506 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 303.310888 # Cycle average of tags in use
788,789c788,789
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.106814 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 99.209691 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.103605 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 99.207284 # Average occupied blocks per requestor
820,821c820,821
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29684000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 29684000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29682000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 29682000 # number of ReadCleanReq miss cycles
824c824
< system.cpu.l2cache.demand_miss_latency::cpu.inst 29684000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 29682000 # number of demand (read+write) miss cycles
826,827c826,827
< system.cpu.l2cache.demand_miss_latency::total 42429500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 29684000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 42427500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 29682000 # number of overall miss cycles
829c829
< system.cpu.l2cache.overall_miss_latency::total 42429500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 42427500 # number of overall miss cycles
856,857c856,857
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81326.027397 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81326.027397 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.547945 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.547945 # average ReadCleanReq miss latency
860c860
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency
862,863c862,863
< system.cpu.l2cache.demand_avg_miss_latency::total 82708.576998 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 82704.678363 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency
865c865
< system.cpu.l2cache.overall_avg_miss_latency::total 82708.576998 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 82704.678363 # average overall miss latency
886,887c886,887
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26034000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26034000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26032000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26032000 # number of ReadCleanReq MSHR miss cycles
890c890
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26034000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26032000 # number of demand (read+write) MSHR miss cycles
892,893c892,893
< system.cpu.l2cache.demand_mshr_miss_latency::total 37319500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26034000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 37317500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26032000 # number of overall MSHR miss cycles
895c895
< system.cpu.l2cache.overall_mshr_miss_latency::total 37319500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 37317500 # number of overall MSHR miss cycles
910,911c910,911
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71326.027397 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71326.027397 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71320.547945 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71320.547945 # average ReadCleanReq mshr miss latency
914c914
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency
916,917c916,917
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency
919c919
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency
< host_inst_rate 90593 # Simulator instruction rate (inst/s)
< host_op_rate 90586 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 187662601 # Simulator tick rate (ticks/s)
< host_mem_usage 251772 # Number of bytes of host memory used
< host_seconds 0.16 # Real time elapsed on the host
---
> host_inst_rate 19226 # Simulator instruction rate (inst/s)
> host_op_rate 19225 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 39829510 # Simulator tick rate (ticks/s)
> host_mem_usage 234412 # Number of bytes of host memory used
> host_seconds 0.75 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 6721500 # Total ticks spent queuing
< system.physmem.totMemAccLat 16340250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6719500 # Total ticks spent queuing
> system.physmem.totMemAccLat 16338250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 13102.34 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13098.44 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 31852.34 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 31848.44 # Average memory access latency per DRAM burst
231c231
< system.physmem_0.actBackEnergy 3642300 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 3644010 # Energy for active background per rank (pJ)
233c233
< system.physmem_0.actPowerDownEnergy 9900900 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 9899190 # Energy for active power-down per rank (pJ)
250c250
< system.physmem_1.actBackEnergy 2522250 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 2521680 # Energy for active background per rank (pJ)
252c252
< system.physmem_1.actPowerDownEnergy 10426440 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 10427010 # Energy for active power-down per rank (pJ)
343c343
< system.cpu.iq.iqInstsIssued 25032 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 25030 # Number of instructions issued
346c346
< system.cpu.iq.iqSquashedOperandsExamined 10993 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedOperandsExamined 11000 # Number of squashed operands that are examined and possibly removed from graph
349,350c349,350
< system.cpu.iq.issued_per_cycle::mean 0.701334 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.501806 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::mean 0.701278 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.501683 # Number of insts issued each cycle
352,354c352,354
< system.cpu.iq.issued_per_cycle::0 26613 74.56% 74.56% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 3169 8.88% 83.44% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1586 4.44% 87.89% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 26611 74.56% 74.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 3173 8.89% 83.45% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1585 4.44% 87.89% # Number of insts issued each cycle
356c356
< system.cpu.iq.issued_per_cycle::4 1197 3.35% 95.51% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::4 1196 3.35% 95.51% # Number of insts issued each cycle
404c404
< system.cpu.iq.FU_type_0::IntAlu 18346 73.29% 73.29% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 18344 73.29% 73.29% # Type of FU issued
441,442c441,442
< system.cpu.iq.FU_type_0::total 25032 # Type of FU issued
< system.cpu.iq.rate 0.418469 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 25030 # Type of FU issued
> system.cpu.iq.rate 0.418436 # Inst issue rate
444,445c444,445
< system.cpu.iq.fu_busy_rate 0.012344 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 86197 # Number of integer instruction queue reads
---
> system.cpu.iq.fu_busy_rate 0.012345 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 86193 # Number of integer instruction queue reads
447c447
< system.cpu.iq.int_inst_queue_wakeup_accesses 22374 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_wakeup_accesses 22369 # Number of integer instruction queue wakeup accesses
451c451
< system.cpu.iq.int_alu_accesses 25341 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 25339 # Number of integer alu accesses
476,478c476,478
< system.cpu.iew.predictedNotTakenIncorrect 1575 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1782 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 23436 # Number of executed instructions
---
> system.cpu.iew.predictedNotTakenIncorrect 1574 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1781 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 23432 # Number of executed instructions
480c480
< system.cpu.iew.iewExecSquashedInsts 1596 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 1598 # Number of squashed instructions skipped in execute
483,492c483,492
< system.cpu.iew.exec_refs 6191 # number of memory reference insts executed
< system.cpu.iew.exec_branches 4986 # Number of branches executed
< system.cpu.iew.exec_stores 2309 # Number of stores executed
< system.cpu.iew.exec_rate 0.391788 # Inst execution rate
< system.cpu.iew.wb_sent 22845 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 22374 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 10411 # num instructions producing a value
< system.cpu.iew.wb_consumers 13650 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.374035 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.762711 # average fanout of values written-back
---
> system.cpu.iew.exec_refs 6190 # number of memory reference insts executed
> system.cpu.iew.exec_branches 4984 # Number of branches executed
> system.cpu.iew.exec_stores 2308 # Number of stores executed
> system.cpu.iew.exec_rate 0.391722 # Inst execution rate
> system.cpu.iew.wb_sent 22840 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 22369 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 10409 # num instructions producing a value
> system.cpu.iew.wb_consumers 13648 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.373951 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.762676 # average fanout of values written-back
573,575c573,575
< system.cpu.int_regfile_reads 36480 # number of integer regfile reads
< system.cpu.int_regfile_writes 20296 # number of integer regfile writes
< system.cpu.misc_regfile_reads 8094 # number of misc regfile reads
---
> system.cpu.int_regfile_reads 36473 # number of integer regfile reads
> system.cpu.int_regfile_writes 20293 # number of integer regfile writes
> system.cpu.misc_regfile_reads 8093 # number of misc regfile reads
579c579
< system.cpu.dcache.tags.tagsinuse 99.158435 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 99.156027 # Cycle average of tags in use
584,586c584,586
< system.cpu.dcache.tags.occ_blocks::cpu.data 99.158435 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.024209 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.024209 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 99.156027 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.024208 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.024208 # Average percentage of cache occupancy
694c694
< system.cpu.icache.tags.tagsinuse 204.747820 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 204.744610 # Cycle average of tags in use
699,701c699,701
< system.cpu.icache.tags.occ_blocks::cpu.inst 204.747820 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.099975 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.099975 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 204.744610 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.099973 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.099973 # Average percentage of cache occupancy
721,726c721,726
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 45891500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 45891500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 45891500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 45891500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 45891500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 45891500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 45890500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 45890500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 45890500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 45890500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 45890500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 45890500 # number of overall miss cycles
739,744c739,744
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77782.203390 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77782.203390 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77782.203390 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77782.203390 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77782.203390 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77780.508475 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77780.508475 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77780.508475 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77780.508475 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77780.508475 # average overall miss latency
763,768c763,768
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30257500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 30257500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30257500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 30257500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30257500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 30257500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30255500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 30255500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30255500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 30255500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30255500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 30255500 # number of overall MSHR miss cycles
775,780c775,780
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82445.504087 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82445.504087 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82445.504087 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 82445.504087 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 82440.054496 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 82440.054496 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 82440.054496 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 82440.054496 # average overall mshr miss latency
783c783
< system.cpu.l2cache.tags.tagsinuse 303.316506 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 303.310888 # Cycle average of tags in use
788,789c788,789
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.106814 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 99.209691 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 204.103605 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 99.207284 # Average occupied blocks per requestor
820,821c820,821
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29684000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 29684000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 29682000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 29682000 # number of ReadCleanReq miss cycles
824c824
< system.cpu.l2cache.demand_miss_latency::cpu.inst 29684000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 29682000 # number of demand (read+write) miss cycles
826,827c826,827
< system.cpu.l2cache.demand_miss_latency::total 42429500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 29684000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 42427500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 29682000 # number of overall miss cycles
829c829
< system.cpu.l2cache.overall_miss_latency::total 42429500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 42427500 # number of overall miss cycles
856,857c856,857
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81326.027397 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81326.027397 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81320.547945 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81320.547945 # average ReadCleanReq miss latency
860c860
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency
862,863c862,863
< system.cpu.l2cache.demand_avg_miss_latency::total 82708.576998 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81326.027397 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 82704.678363 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81320.547945 # average overall miss latency
865c865
< system.cpu.l2cache.overall_avg_miss_latency::total 82708.576998 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 82704.678363 # average overall miss latency
886,887c886,887
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26034000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26034000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26032000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26032000 # number of ReadCleanReq MSHR miss cycles
890c890
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26034000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26032000 # number of demand (read+write) MSHR miss cycles
892,893c892,893
< system.cpu.l2cache.demand_mshr_miss_latency::total 37319500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26034000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 37317500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26032000 # number of overall MSHR miss cycles
895c895
< system.cpu.l2cache.overall_mshr_miss_latency::total 37319500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 37317500 # number of overall MSHR miss cycles
910,911c910,911
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71326.027397 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71326.027397 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71320.547945 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71320.547945 # average ReadCleanReq mshr miss latency
914c914
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency
916,917c916,917
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71326.027397 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71320.547945 # average overall mshr miss latency
919c919
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72747.563353 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72743.664717 # average overall mshr miss latency