4,5c4,5
< sim_ticks 28845500 # Number of ticks simulated
< final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 29089500 # Number of ticks simulated
> final_tick 29089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 66025 # Simulator instruction rate (inst/s)
< host_op_rate 66018 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 131902943 # Simulator tick rate (ticks/s)
< host_mem_usage 248796 # Number of bytes of host memory used
< host_seconds 0.22 # Real time elapsed on the host
---
> host_inst_rate 39190 # Simulator instruction rate (inst/s)
> host_op_rate 39188 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 78964807 # Simulator tick rate (ticks/s)
> host_mem_usage 252916 # Number of bytes of host memory used
> host_seconds 0.37 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 798638684 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 323415665 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1122054350 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 798638684 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 798638684 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 798638684 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 323415665 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1122054350 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 28814000 # Total gap between requests
---
> system.physmem.totGap 29058000 # Total gap between requests
191,193c191,193
< system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 411.306667 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 274.853259 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 343.874505 # Bytes accessed per row activation
195,197c195,197
< system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::128-255 19 25.33% 42.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 12 16.00% 58.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 6 8.00% 66.67% # Bytes accessed per row activation
203,204c203,204
< system.physmem.totQLat 3584250 # Total ticks spent queuing
< system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3266500 # Total ticks spent queuing
> system.physmem.totMemAccLat 12847750 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6392.37 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 25142.37 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1124.25 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1124.25 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 8.86 # Data bus utilization in percentage
< system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 8.78 # Data bus utilization in percentage
> system.physmem.busUtilRead 8.78 # Data bus utilization in percentage for reads
217c217
< system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing
219c219
< system.physmem.readRowHits 428 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 427 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 83.56 # Row buffer hit rate for reads
223,224c223,224
< system.physmem.avgGap 56387.48 # Average gap between requests
< system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 56864.97 # Average gap between requests
> system.physmem.pageHitRate 83.56 # Row buffer hit rate, read and write combined
227c227
< system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 2113800 # Energy for read commands per rank (pJ)
230,234c230,234
< system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ)
< system.physmem_0.averagePower 856.515480 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states
---
> system.physmem_0.actBackEnergy 16083405 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 63000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 20264970 # Total energy per rank (pJ)
> system.physmem_0.averagePower 858.003493 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states
244,248c244,248
< system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ)
< system.physmem_1.averagePower 820.243027 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states
---
> system.physmem_1.actBackEnergy 15332715 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 721500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 19350015 # Total energy per rank (pJ)
> system.physmem_1.averagePower 819.264991 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 4570750 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 21719750 # Time in different power states
253,255c253,255
< system.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 12618 # Number of BP lookups
< system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted
---
> system.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 12614 # Number of BP lookups
> system.cpu.branchPred.condPredicted 7656 # Number of conditional branches predicted
257c257
< system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 9453 # Number of BTB lookups
263c263
< system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups.
---
> system.cpu.branchPred.indirectLookups 9453 # Number of indirect predictor lookups.
265c265
< system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses.
---
> system.cpu.branchPred.indirectMisses 7609 # Number of indirect misses.
269,270c269,270
< system.cpu.pwrStateResidencyTicks::ON 28845500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 57692 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 29089500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 58180 # number of cpu cycles simulated
273,275c273,275
< system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered
---
> system.cpu.fetch.icacheStallCycles 15554 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 59055 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 12614 # Number of branches that fetch encountered
277c277
< system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 17529 # Number of cycles fetch has run and was not squashing or blocked
280c280
< system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
---
> system.cpu.fetch.PendingTrapStallCycles 1090 # Number of stall cycles due to pending traps
283,286c283,286
< system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheSquashes 720 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 35776 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.650688 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.904189 # Number of instructions fetched each cycle (Total)
288,296c288,296
< system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 23025 64.36% 64.36% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 4506 12.60% 76.95% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 507 1.42% 78.37% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 451 1.26% 79.63% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 761 2.13% 81.76% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 707 1.98% 83.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 297 0.83% 84.57% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 355 0.99% 85.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 5167 14.44% 100.00% # Number of instructions fetched each cycle (Total)
300,306c300,306
< system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 7933 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking
---
> system.cpu.fetch.rateDist::total 35776 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.216810 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.015040 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 12463 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 13012 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 7932 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 797 # Number of cycles decode is unblocking
308c308
< system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 42051 # Number of instructions handled by decode
310,315c310,315
< system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 7918 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename
---
> system.cpu.rename.IdleCycles 13239 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 1819 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 9760 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 7921 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1465 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 37034 # Number of instructions processed by rename
317,320c317,320
< system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 1048 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 31990 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 66442 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 54845 # Number of integer rename lookups
322c322
< system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 18171 # Number of HB maps that are undone due to squashing
327c327
< system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedStores 2920 # Number of stores inserted to the mem dependence unit.
330c330
< system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 28828 # Number of instructions added to the IQ (excludes non-spec)
333,335c333,335
< system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 15149 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 11337 # Number of squashed operands that are examined and possibly removed from graph
337,339c337,339
< system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 35776 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.708911 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.503990 # Number of insts issued each cycle
341,348c341,348
< system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 26518 74.12% 74.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 3268 9.13% 83.26% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1619 4.53% 87.78% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 1541 4.31% 92.09% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1236 3.45% 95.54% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 752 2.10% 97.65% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 465 1.30% 98.95% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 277 0.77% 99.72% # Number of insts issued each cycle
353c353
< system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 35776 # Number of insts issued each cycle
355,385c355,385
< system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 154 52.56% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 51 17.41% 69.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 88 30.03% 100.00% # attempts to use FU when none available
389,418c389,418
< system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 18584 73.27% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 4272 16.84% 90.12% # Type of FU issued
423,428c423,428
< system.cpu.iq.rate 0.439610 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 294 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.rate 0.435923 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 293 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.011553 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 86911 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 44761 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 22611 # Number of integer instruction queue wakeup accesses
432c432
< system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 25655 # Number of integer alu accesses
439c439
< system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 1472 # Number of stores squashed
446c446
< system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 1852 # Number of cycles IEW is blocking
448c448
< system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 31164 # Number of instructions dispatched to IQ
451c451
< system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispStoreInsts 2920 # Number of dispatched store instructions
457,459c457,459
< system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions
---
> system.cpu.iew.predictedNotTakenIncorrect 1624 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1835 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 23718 # Number of executed instructions
461c461
< system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 1644 # Number of squashed instructions skipped in execute
464c464
< system.cpu.iew.exec_refs 6244 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 6245 # number of memory reference insts executed
466,474c466,474
< system.cpu.iew.exec_stores 2299 # Number of stores executed
< system.cpu.iew.exec_rate 0.411045 # Inst execution rate
< system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 22607 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 10530 # num instructions producing a value
< system.cpu.iew.wb_consumers 13790 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_stores 2300 # Number of stores executed
> system.cpu.iew.exec_rate 0.407666 # Inst execution rate
> system.cpu.iew.wb_sent 23107 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 22611 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 10526 # num instructions producing a value
> system.cpu.iew.wb_consumers 13786 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.388639 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.763528 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 15913 # The number of squashed insts skipped by commit
477,479c477,479
< system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 32637 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.464565 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.243420 # Number of insts commited each cycle
481,486c481,486
< system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 25892 79.33% 79.33% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 3639 11.15% 90.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 1211 3.71% 94.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 601 1.84% 96.04% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 338 1.04% 97.07% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 300 0.92% 97.99% # Number of insts commited each cycle
488c488
< system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::7 54 0.17% 99.30% # Number of insts commited each cycle
493c493
< system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 32637 # Number of insts commited each cycle
540,543c540,543
< system.cpu.rob.rob_reads 62581 # The number of ROB reads
< system.cpu.rob.rob_writes 65380 # The number of ROB writes
< system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 62661 # The number of ROB reads
> system.cpu.rob.rob_writes 65377 # The number of ROB writes
> system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 22404 # Total number of cycles that the CPU has spent unscheduled due to idling
546,552c546,552
< system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 36850 # number of integer regfile reads
< system.cpu.int_regfile_writes 20548 # number of integer regfile writes
< system.cpu.misc_regfile_reads 8142 # number of misc regfile reads
---
> system.cpu.cpi 4.030202 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 4.030202 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.248127 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.248127 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 36851 # number of integer regfile reads
> system.cpu.int_regfile_writes 20552 # number of integer regfile writes
> system.cpu.misc_regfile_reads 8143 # number of misc regfile reads
554c554
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
556c556
< system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 99.825953 # Cycle average of tags in use
561,563c561,563
< system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 99.825953 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.024372 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.024372 # Average percentage of cache occupancy
570c570
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
589,596c589,596
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9476500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9476500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 27259981 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 27259981 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 36736481 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 36736481 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 36736481 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 36736481 # number of overall miss cycles
615,623c615,623
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67689.285714 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 67689.285714 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66650.320293 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 66650.320293 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 66915.265938 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 66915.265938 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked
627c627
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.956522 # average number of cycles each access was blocked
645,652c645,652
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5190500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5190500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6454500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6454500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11645000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11645000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11645000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11645000 # number of overall MSHR miss cycles
661,669c661,669
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79853.846154 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79853.846154 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77765.060241 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77765.060241 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
671c671
< system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 206.188252 # Cycle average of tags in use
676,678c676,678
< system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 206.188252 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.100678 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.100678 # Average percentage of cache occupancy
680,681c680,681
< system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
685c685
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
698,703c698,703
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 40938500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 40938500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 40938500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 40938500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 40938500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 40938500 # number of overall miss cycles
716,722c716,722
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70462.134251 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 70462.134251 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 70462.134251 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 70462.134251 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 194 # number of cycles access was blocked
726c726
< system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 97 # average number of cycles each access was blocked
740,745c740,745
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27977500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 27977500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27977500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 27977500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27977500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 27977500 # number of overall MSHR miss cycles
752,758c752,758
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76650.684932 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76650.684932 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
760c760
< system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 305.425349 # Cycle average of tags in use
762,763c762,763
< system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks.
765,773c765,773
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.546698 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 99.878652 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006273 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.003048 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.009321 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id
776c776
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
795,806c795,806
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6452500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6452500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27176000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 27176000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5013500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5013500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 27176000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11466000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 38642000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 27176000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11466000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 38642000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6329000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6329000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27407000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 27407000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5095500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 5095500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27407000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11424500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 38831500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27407000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11424500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 38831500 # number of overall miss cycles
831,842c831,842
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76253.012048 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76253.012048 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75501.377410 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75501.377410 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78392.307692 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78392.307692 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75501.377410 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77192.567568 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75991.193738 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75501.377410 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77192.567568 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75991.193738 # average overall miss latency
861,872c861,872
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5499000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5499000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23777000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23777000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4465500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4465500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23777000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9964500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 33741500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23777000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9964500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 33741500 # number of overall MSHR miss cycles
885,896c885,896
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66253.012048 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66253.012048 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65501.377410 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65501.377410 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68700 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68700 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency
903c903
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
934c934,940
< system.membus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
955,957c961,963
< system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 623000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.1 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2693500 # Layer occupancy (ticks)
< sim_ticks 28845500 # Number of ticks simulated
< final_tick 28845500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 29089500 # Number of ticks simulated
> final_tick 29089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 66025 # Simulator instruction rate (inst/s)
< host_op_rate 66018 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 131902943 # Simulator tick rate (ticks/s)
< host_mem_usage 248796 # Number of bytes of host memory used
< host_seconds 0.22 # Real time elapsed on the host
---
> host_inst_rate 39190 # Simulator instruction rate (inst/s)
> host_op_rate 39188 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 78964807 # Simulator tick rate (ticks/s)
> host_mem_usage 252916 # Number of bytes of host memory used
> host_seconds 0.37 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 805394256 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 326151393 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1131545648 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 805394256 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 805394256 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 805394256 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 326151393 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1131545648 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 798638684 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 323415665 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1122054350 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 798638684 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 798638684 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 798638684 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 323415665 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1122054350 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 28814000 # Total gap between requests
---
> system.physmem.totGap 29058000 # Total gap between requests
191,193c191,193
< system.physmem.bytesPerActivate::mean 412.160000 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 276.286075 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 342.271863 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::mean 411.306667 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 274.853259 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 343.874505 # Bytes accessed per row activation
195,197c195,197
< system.physmem.bytesPerActivate::128-255 18 24.00% 41.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 12 16.00% 57.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 7 9.33% 66.67% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::128-255 19 25.33% 42.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 12 16.00% 58.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 6 8.00% 66.67% # Bytes accessed per row activation
203,204c203,204
< system.physmem.totQLat 3584250 # Total ticks spent queuing
< system.physmem.totMemAccLat 13165500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 3266500 # Total ticks spent queuing
> system.physmem.totMemAccLat 12847750 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 7014.19 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 6392.37 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 25764.19 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1133.76 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 25142.37 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1124.25 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1133.76 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1124.25 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 8.86 # Data bus utilization in percentage
< system.physmem.busUtilRead 8.86 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 8.78 # Data bus utilization in percentage
> system.physmem.busUtilRead 8.78 # Data bus utilization in percentage for reads
217c217
< system.physmem.avgRdQLen 1.55 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.54 # Average read queue length when enqueuing
219c219
< system.physmem.readRowHits 428 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 427 # Number of row buffer hits during reads
221c221
< system.physmem.readRowHitRate 83.76 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 83.56 # Row buffer hit rate for reads
223,224c223,224
< system.physmem.avgGap 56387.48 # Average gap between requests
< system.physmem.pageHitRate 83.76 # Row buffer hit rate, read and write combined
---
> system.physmem.avgGap 56864.97 # Average gap between requests
> system.physmem.pageHitRate 83.56 # Row buffer hit rate, read and write combined
227c227
< system.physmem_0.readEnergy 2121600 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 2113800 # Energy for read commands per rank (pJ)
230,234c230,234
< system.physmem_0.actBackEnergy 15733710 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 369750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 20229825 # Total energy per rank (pJ)
< system.physmem_0.averagePower 856.515480 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 717750 # Time in different power states
---
> system.physmem_0.actBackEnergy 16083405 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 63000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 20264970 # Total energy per rank (pJ)
> system.physmem_0.averagePower 858.003493 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 27177750 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states
244,248c244,248
< system.physmem_1.actBackEnergy 15520815 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 556500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 19373115 # Total energy per rank (pJ)
< system.physmem_1.averagePower 820.243027 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 4073500 # Time in different power states
---
> system.physmem_1.actBackEnergy 15332715 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 721500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 19350015 # Total energy per rank (pJ)
> system.physmem_1.averagePower 819.264991 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 4570750 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 21995000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 21719750 # Time in different power states
253,255c253,255
< system.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 12618 # Number of BP lookups
< system.cpu.branchPred.condPredicted 7653 # Number of conditional branches predicted
---
> system.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 12614 # Number of BP lookups
> system.cpu.branchPred.condPredicted 7656 # Number of conditional branches predicted
257c257
< system.cpu.branchPred.BTBLookups 9458 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 9453 # Number of BTB lookups
263c263
< system.cpu.branchPred.indirectLookups 9458 # Number of indirect predictor lookups.
---
> system.cpu.branchPred.indirectLookups 9453 # Number of indirect predictor lookups.
265c265
< system.cpu.branchPred.indirectMisses 7614 # Number of indirect misses.
---
> system.cpu.branchPred.indirectMisses 7609 # Number of indirect misses.
269,270c269,270
< system.cpu.pwrStateResidencyTicks::ON 28845500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 57692 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 29089500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 58180 # number of cpu cycles simulated
273,275c273,275
< system.cpu.fetch.icacheStallCycles 15531 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 59063 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 12618 # Number of branches that fetch encountered
---
> system.cpu.fetch.icacheStallCycles 15554 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 59055 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 12614 # Number of branches that fetch encountered
277c277
< system.cpu.fetch.Cycles 17477 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.Cycles 17529 # Number of cycles fetch has run and was not squashing or blocked
280c280
< system.cpu.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
---
> system.cpu.fetch.PendingTrapStallCycles 1090 # Number of stall cycles due to pending traps
283,286c283,286
< system.cpu.fetch.IcacheSquashes 719 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 35695 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.654658 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.906598 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheSquashes 720 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 35776 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.650688 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.904189 # Number of instructions fetched each cycle (Total)
288,296c288,296
< system.cpu.fetch.rateDist::0 22943 64.28% 64.28% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 4506 12.62% 76.90% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 507 1.42% 78.32% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 451 1.26% 79.58% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 761 2.13% 81.71% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 707 1.98% 83.70% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 297 0.83% 84.53% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 355 0.99% 85.52% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 5168 14.48% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 23025 64.36% 64.36% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 4506 12.60% 76.95% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 507 1.42% 78.37% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 451 1.26% 79.63% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 761 2.13% 81.76% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 707 1.98% 83.73% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 297 0.83% 84.57% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 355 0.99% 85.56% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 5167 14.44% 100.00% # Number of instructions fetched each cycle (Total)
300,306c300,306
< system.cpu.fetch.rateDist::total 35695 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.218713 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.023764 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 12449 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 12945 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 7933 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 796 # Number of cycles decode is unblocking
---
> system.cpu.fetch.rateDist::total 35776 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.216810 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.015040 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 12463 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 13012 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 7932 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 797 # Number of cycles decode is unblocking
308c308
< system.cpu.decode.DecodedInsts 42061 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 42051 # Number of instructions handled by decode
310,315c310,315
< system.cpu.rename.IdleCycles 13228 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 1813 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 9713 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 7918 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1451 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 37021 # Number of instructions processed by rename
---
> system.cpu.rename.IdleCycles 13239 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 1819 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 9760 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 7921 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1465 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 37034 # Number of instructions processed by rename
317,320c317,320
< system.cpu.rename.SQFullEvents 1034 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 31983 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 66431 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 54837 # Number of integer rename lookups
---
> system.cpu.rename.SQFullEvents 1048 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 31990 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 66442 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 54845 # Number of integer rename lookups
322c322
< system.cpu.rename.UndoneMaps 18164 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 18171 # Number of HB maps that are undone due to squashing
327c327
< system.cpu.memDep0.insertedStores 2922 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedStores 2920 # Number of stores inserted to the mem dependence unit.
330c330
< system.cpu.iq.iqInstsAdded 28829 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 28828 # Number of instructions added to the IQ (excludes non-spec)
333,335c333,335
< system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 15150 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 11340 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 15149 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 11337 # Number of squashed operands that are examined and possibly removed from graph
337,339c337,339
< system.cpu.iq.issued_per_cycle::samples 35695 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.710520 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.505149 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 35776 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.708911 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.503990 # Number of insts issued each cycle
341,348c341,348
< system.cpu.iq.issued_per_cycle::0 26438 74.07% 74.07% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 3266 9.15% 83.22% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1617 4.53% 87.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 1544 4.33% 92.07% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 1236 3.46% 95.53% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 754 2.11% 97.65% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 464 1.30% 98.95% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 276 0.77% 99.72% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 26518 74.12% 74.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 3268 9.13% 83.26% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1619 4.53% 87.78% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 1541 4.31% 92.09% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1236 3.45% 95.54% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 752 2.10% 97.65% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 465 1.30% 98.95% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 277 0.77% 99.72% # Number of insts issued each cycle
353c353
< system.cpu.iq.issued_per_cycle::total 35695 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 35776 # Number of insts issued each cycle
355,385c355,385
< system.cpu.iq.fu_full::IntAlu 153 52.04% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.04% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 53 18.03% 70.07% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 88 29.93% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 154 52.56% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.56% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 51 17.41% 69.97% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 88 30.03% 100.00% # attempts to use FU when none available
389,418c389,418
< system.cpu.iq.FU_type_0::IntAlu 18585 73.28% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.28% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 4271 16.84% 90.12% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 18584 73.27% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.27% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 4272 16.84% 90.12% # Type of FU issued
423,428c423,428
< system.cpu.iq.rate 0.439610 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 294 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.011592 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 86830 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 44763 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 22607 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.rate 0.435923 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 293 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.011553 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 86911 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 44761 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 22611 # Number of integer instruction queue wakeup accesses
432c432
< system.cpu.iq.int_alu_accesses 25656 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 25655 # Number of integer alu accesses
439c439
< system.cpu.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 1472 # Number of stores squashed
446c446
< system.cpu.iew.iewBlockCycles 1846 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 1852 # Number of cycles IEW is blocking
448c448
< system.cpu.iew.iewDispatchedInsts 31165 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 31164 # Number of instructions dispatched to IQ
451c451
< system.cpu.iew.iewDispStoreInsts 2922 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispStoreInsts 2920 # Number of dispatched store instructions
457,459c457,459
< system.cpu.iew.predictedNotTakenIncorrect 1623 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 1834 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 23714 # Number of executed instructions
---
> system.cpu.iew.predictedNotTakenIncorrect 1624 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 1835 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 23718 # Number of executed instructions
461c461
< system.cpu.iew.iewExecSquashedInsts 1648 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 1644 # Number of squashed instructions skipped in execute
464c464
< system.cpu.iew.exec_refs 6244 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs 6245 # number of memory reference insts executed
466,474c466,474
< system.cpu.iew.exec_stores 2299 # Number of stores executed
< system.cpu.iew.exec_rate 0.411045 # Inst execution rate
< system.cpu.iew.wb_sent 23102 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 22607 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 10530 # num instructions producing a value
< system.cpu.iew.wb_consumers 13790 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.391857 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.763597 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 15914 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_stores 2300 # Number of stores executed
> system.cpu.iew.exec_rate 0.407666 # Inst execution rate
> system.cpu.iew.wb_sent 23107 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 22611 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 10526 # num instructions producing a value
> system.cpu.iew.wb_consumers 13786 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.388639 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.763528 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 15913 # The number of squashed insts skipped by commit
477,479c477,479
< system.cpu.commit.committed_per_cycle::samples 32556 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.465721 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.244675 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 32637 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.464565 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.243420 # Number of insts commited each cycle
481,486c481,486
< system.cpu.commit.committed_per_cycle::0 25812 79.28% 79.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 3638 11.17% 90.46% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 1209 3.71% 94.17% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 603 1.85% 96.03% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 337 1.04% 97.06% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 302 0.93% 97.99% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 25892 79.33% 79.33% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 3639 11.15% 90.48% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 1211 3.71% 94.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 601 1.84% 96.04% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 338 1.04% 97.07% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 300 0.92% 97.99% # Number of insts commited each cycle
488c488
< system.cpu.commit.committed_per_cycle::7 53 0.16% 99.30% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::7 54 0.17% 99.30% # Number of insts commited each cycle
493c493
< system.cpu.commit.committed_per_cycle::total 32556 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 32637 # Number of insts commited each cycle
540,543c540,543
< system.cpu.rob.rob_reads 62581 # The number of ROB reads
< system.cpu.rob.rob_writes 65380 # The number of ROB writes
< system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 21997 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 62661 # The number of ROB reads
> system.cpu.rob.rob_writes 65377 # The number of ROB writes
> system.cpu.timesIdled 196 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 22404 # Total number of cycles that the CPU has spent unscheduled due to idling
546,552c546,552
< system.cpu.cpi 3.996398 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 3.996398 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.250225 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.250225 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 36850 # number of integer regfile reads
< system.cpu.int_regfile_writes 20548 # number of integer regfile writes
< system.cpu.misc_regfile_reads 8142 # number of misc regfile reads
---
> system.cpu.cpi 4.030202 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 4.030202 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.248127 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.248127 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 36851 # number of integer regfile reads
> system.cpu.int_regfile_writes 20552 # number of integer regfile writes
> system.cpu.misc_regfile_reads 8143 # number of misc regfile reads
554c554
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
556c556
< system.cpu.dcache.tags.tagsinuse 99.867537 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 99.825953 # Cycle average of tags in use
561,563c561,563
< system.cpu.dcache.tags.occ_blocks::cpu.data 99.867537 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.024382 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.024382 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 99.825953 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.024372 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.024372 # Average percentage of cache occupancy
570c570
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
589,596c589,596
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9339500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9339500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 27134481 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 27134481 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 36473981 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 36473981 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 36473981 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 36473981 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9476500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9476500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 27259981 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 27259981 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 36736481 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 36736481 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 36736481 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 36736481 # number of overall miss cycles
615,623c615,623
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66710.714286 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 66710.714286 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66343.474328 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 66343.474328 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 66437.123862 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 66437.123862 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 66437.123862 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 1313 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67689.285714 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 67689.285714 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66650.320293 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 66650.320293 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 66915.265938 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 66915.265938 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 66915.265938 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked
627c627
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.086957 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 57.956522 # average number of cycles each access was blocked
645,652c645,652
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5108500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5108500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6578000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 6578000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11686500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11686500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11686500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5190500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5190500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6454500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 6454500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11645000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11645000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11645000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11645000 # number of overall MSHR miss cycles
661,669c661,669
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78592.307692 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78592.307692 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79253.012048 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79253.012048 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78962.837838 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 78962.837838 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79853.846154 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79853.846154 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77765.060241 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77765.060241 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78682.432432 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 78682.432432 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
671c671
< system.cpu.icache.tags.tagsinuse 206.414108 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 206.188252 # Cycle average of tags in use
676,678c676,678
< system.cpu.icache.tags.occ_blocks::cpu.inst 206.414108 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.100788 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.100788 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 206.188252 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.100678 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.100678 # Average percentage of cache occupancy
680,681c680,681
< system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id
685c685
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
698,703c698,703
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 40819000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 40819000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 40819000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 40819000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 40819000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 40819000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 40938500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 40938500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 40938500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 40938500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 40938500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 40938500 # number of overall miss cycles
716,722c716,722
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70256.454389 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 70256.454389 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 70256.454389 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 70256.454389 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 70256.454389 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70462.134251 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 70462.134251 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 70462.134251 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 70462.134251 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 70462.134251 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 194 # number of cycles access was blocked
726c726
< system.cpu.icache.avg_blocked_cycles::no_mshrs 95 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 97 # average number of cycles each access was blocked
740,745c740,745
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27746500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 27746500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27746500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 27746500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27746500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 27746500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27977500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 27977500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27977500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 27977500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27977500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 27977500 # number of overall MSHR miss cycles
752,758c752,758
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76017.808219 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76017.808219 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76017.808219 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 76017.808219 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76650.684932 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76650.684932 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76650.684932 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 76650.684932 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
760c760
< system.cpu.l2cache.tags.tagsinuse 240.923513 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 305.425349 # Cycle average of tags in use
762,763c762,763
< system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.004695 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 509 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.003929 # Average number of references to valid blocks.
765,773c765,773
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.773852 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 35.149660 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006280 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001073 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007352 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 205.546698 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 99.878652 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006273 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.003048 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.009321 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 399 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015533 # Percentage of cache occupancy per task id
776c776
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
795,806c795,806
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6452500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 6452500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27176000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 27176000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5013500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5013500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 27176000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11466000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 38642000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 27176000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11466000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 38642000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6329000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 6329000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27407000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 27407000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5095500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 5095500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27407000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11424500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 38831500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27407000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11424500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 38831500 # number of overall miss cycles
831,842c831,842
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77740.963855 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77740.963855 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74865.013774 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74865.013774 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77130.769231 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77130.769231 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75620.352250 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74865.013774 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77472.972973 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75620.352250 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76253.012048 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76253.012048 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75501.377410 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75501.377410 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78392.307692 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78392.307692 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75501.377410 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77192.567568 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75991.193738 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75501.377410 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77192.567568 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75991.193738 # average overall miss latency
861,872c861,872
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5622500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5622500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23546000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23546000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4383500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4383500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23546000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10006000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 33552000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23546000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10006000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 33552000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5499000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5499000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23777000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23777000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4465500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4465500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23777000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9964500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 33741500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23777000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9964500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 33741500 # number of overall MSHR miss cycles
885,896c885,896
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67740.963855 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67740.963855 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64865.013774 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64865.013774 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 67438.461538 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 67438.461538 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64865.013774 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67608.108108 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65659.491194 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66253.012048 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66253.012048 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65501.377410 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65501.377410 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68700 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68700 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65501.377410 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67327.702703 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66030.332681 # average overall mshr miss latency
903c903
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
934c934,940
< system.membus.pwrStateResidencyTicks::UNDEFINED 28845500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 29089500 # Cumulative time (in ticks) in various power states
955,957c961,963
< system.membus.reqLayer0.occupancy 623500 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2694000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 623000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.1 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2693500 # Layer occupancy (ticks)