7,11c7,11
< host_inst_rate 14664 # Simulator instruction rate (inst/s)
< host_op_rate 14664 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 26353337 # Simulator tick rate (ticks/s)
< host_mem_usage 237548 # Number of bytes of host memory used
< host_seconds 0.98 # Real time elapsed on the host
---
> host_inst_rate 79125 # Simulator instruction rate (inst/s)
> host_op_rate 79119 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 142180718 # Simulator tick rate (ticks/s)
> host_mem_usage 289004 # Number of bytes of host memory used
> host_seconds 0.18 # Real time elapsed on the host
94,95c94,95
< system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
203,204c203,204
< system.physmem.totQLat 2648500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11873500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2786000 # Total ticks spent queuing
> system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 5383.13 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 24133.13 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst
230d229
< system.membus.throughput 1211224175 # Throughput (bytes/s)
237,240c236,248
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 31424 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 492 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 492 # Request fanout histogram
543d550
< system.cpu.toL2Bus.throughput 1216157879 # Throughput (bytes/s)
551,555c558,572
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 31552 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram
563c580
< system.cpu.icache.tags.tagsinuse 192.510615 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use
568c585
< system.cpu.icache.tags.occ_blocks::cpu.inst 192.510615 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor
589,594c606,611
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32454000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32454000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32454000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32454000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32454000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32454000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles
607,612c624,629
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61465.909091 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61465.909091 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61465.909091 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61465.909091 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency
633,638c650,655
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23048750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23048750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23048750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23048750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23048750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23048750 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles
645,650c662,667
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66614.884393 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66614.884393 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency
658,659c675,676
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902478 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 34.634175 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor
686,687c703,704
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22682250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4667500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles
691,692c708,709
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22682250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10818500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles
694,695c711,712
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22682250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10818500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles
719,720c736,737
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.773256 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71807.692308 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency
724,725c741,742
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency
727,728c744,745
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency
749,750c766,767
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18356250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3880500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles
754,755c771,772
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18356250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9012000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles
757,758c774,775
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18356250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9012000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles
771,772c788,789
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53361.191860 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59700 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency
776,777c793,794
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency
779,780c796,797
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency
784c801
< system.cpu.dcache.tags.tagsinuse 98.823641 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use
789c806
< system.cpu.dcache.tags.occ_blocks::cpu.data 98.823641 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor
816,817c833,834
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8661750 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8661750 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles
820,823c837,840
< system.cpu.dcache.demand_miss_latency::cpu.data 34754974 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34754974 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34754974 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34754974 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles
842,843c859,860
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62314.748201 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 62314.748201 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency
846,849c863,866
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63421.485401 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63421.485401 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency
874,875c891,892
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4732000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4732000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles
878,881c895,898
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10967500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10967500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10967500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10967500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles
890,891c907,908
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72800 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72800 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency
894,897c911,914
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency
< host_inst_rate 14664 # Simulator instruction rate (inst/s)
< host_op_rate 14664 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 26353337 # Simulator tick rate (ticks/s)
< host_mem_usage 237548 # Number of bytes of host memory used
< host_seconds 0.98 # Real time elapsed on the host
---
> host_inst_rate 79125 # Simulator instruction rate (inst/s)
> host_op_rate 79119 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 142180718 # Simulator tick rate (ticks/s)
> host_mem_usage 289004 # Number of bytes of host memory used
> host_seconds 0.18 # Real time elapsed on the host
94,95c94,95
< system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
203,204c203,204
< system.physmem.totQLat 2648500 # Total ticks spent queuing
< system.physmem.totMemAccLat 11873500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 2786000 # Total ticks spent queuing
> system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 5383.13 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst
208c208
< system.physmem.avgMemAccLat 24133.13 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst
230d229
< system.membus.throughput 1211224175 # Throughput (bytes/s)
237,240c236,248
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 31424 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 492 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 492 # Request fanout histogram
543d550
< system.cpu.toL2Bus.throughput 1216157879 # Throughput (bytes/s)
551,555c558,572
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 31552 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram
563c580
< system.cpu.icache.tags.tagsinuse 192.510615 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use
568c585
< system.cpu.icache.tags.occ_blocks::cpu.inst 192.510615 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor
589,594c606,611
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32454000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32454000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32454000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32454000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32454000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32454000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles
607,612c624,629
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61465.909091 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61465.909091 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61465.909091 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61465.909091 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency
633,638c650,655
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23048750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 23048750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23048750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 23048750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23048750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 23048750 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles
645,650c662,667
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66614.884393 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66614.884393 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency
658,659c675,676
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902478 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 34.634175 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor
686,687c703,704
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22682250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4667500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles
691,692c708,709
< system.cpu.l2cache.demand_miss_latency::cpu.inst 22682250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10818500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles
694,695c711,712
< system.cpu.l2cache.overall_miss_latency::cpu.inst 22682250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10818500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles
719,720c736,737
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.773256 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71807.692308 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency
724,725c741,742
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency
727,728c744,745
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency
749,750c766,767
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18356250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3880500 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles
754,755c771,772
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18356250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9012000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles
757,758c774,775
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18356250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9012000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles
771,772c788,789
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53361.191860 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59700 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency
776,777c793,794
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency
779,780c796,797
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency
784c801
< system.cpu.dcache.tags.tagsinuse 98.823641 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use
789c806
< system.cpu.dcache.tags.occ_blocks::cpu.data 98.823641 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor
816,817c833,834
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 8661750 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 8661750 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles
820,823c837,840
< system.cpu.dcache.demand_miss_latency::cpu.data 34754974 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34754974 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34754974 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34754974 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles
842,843c859,860
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62314.748201 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 62314.748201 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency
846,849c863,866
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63421.485401 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63421.485401 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency
874,875c891,892
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4732000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4732000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles
878,881c895,898
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10967500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10967500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10967500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10967500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles
890,891c907,908
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72800 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72800 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency
894,897c911,914
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency