Cross Reference: /gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000027 # Number of seconds simulated

4sim_ticks 26943000 # Number of ticks simulated
5final_tick 26943000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 26944000 # Number of ticks simulated
5final_tick 26944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 30305 # Simulator instruction rate (inst/s)
8host_op_rate 30304 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 56555572 # Simulator tick rate (ticks/s)
10host_mem_usage 288252 # Number of bytes of host memory used
11host_seconds 0.48 # Real time elapsed on the host

7host_inst_rate 95332 # Simulator instruction rate (inst/s)
8host_op_rate 95323 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 177899852 # Simulator tick rate (ticks/s)
10host_mem_usage 294468 # Number of bytes of host memory used
11host_seconds 0.15 # Real time elapsed on the host

12sim_insts 14436 # Number of instructions simulated
13sim_ops 14436 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 21888 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9408 # Number of bytes read from this memory
18system.physmem.bytes_read::total 31296 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 21888 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 21888 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 342 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 489 # Number of read requests responded to by this memory

24system.physmem.bw_read::cpu.inst 812381695 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 349181606 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1161563300 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 812381695 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 812381695 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 812381695 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 349181606 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1161563300 # Total bandwidth to/from this memory (bytes/s)

24system.physmem.bw_read::cpu.inst 812351544 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 349168646 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1161520190 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 812351544 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 812351544 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 812351544 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 349168646 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1161520190 # Total bandwidth to/from this memory (bytes/s)

32system.physmem.readReqs 489 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 489 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 31296 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 31296 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 107 # Per bank write bursts
45system.physmem.perBankRdBursts::1 27 # Per bank write bursts
46system.physmem.perBankRdBursts::2 49 # Per bank write bursts
47system.physmem.perBankRdBursts::3 24 # Per bank write bursts
48system.physmem.perBankRdBursts::4 20 # Per bank write bursts
49system.physmem.perBankRdBursts::5 0 # Per bank write bursts
50system.physmem.perBankRdBursts::6 32 # Per bank write bursts
51system.physmem.perBankRdBursts::7 36 # Per bank write bursts
52system.physmem.perBankRdBursts::8 4 # Per bank write bursts
53system.physmem.perBankRdBursts::9 2 # Per bank write bursts
54system.physmem.perBankRdBursts::10 1 # Per bank write bursts
55system.physmem.perBankRdBursts::11 0 # Per bank write bursts
56system.physmem.perBankRdBursts::12 56 # Per bank write bursts
57system.physmem.perBankRdBursts::13 31 # Per bank write bursts
58system.physmem.perBankRdBursts::14 61 # Per bank write bursts
59system.physmem.perBankRdBursts::15 39 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry

78system.physmem.totGap 26890000 # Total gap between requests

78system.physmem.totGap 26891000 # Total gap between requests

79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 489 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 297 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 73 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 396.273973 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 268.840282 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 332.152795 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 12 16.44% 16.44% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 20 27.40% 43.84% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 11 15.07% 58.90% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 7 9.59% 68.49% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 6 8.22% 76.71% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 1 1.37% 78.08% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 5 6.85% 84.93% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 1 1.37% 86.30% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 10 13.70% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 73 # Bytes accessed per row activation
203system.physmem.totQLat 3681750 # Total ticks spent queuing
204system.physmem.totMemAccLat 12850500 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 2445000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 7529.14 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 26279.14 # Average memory access latency per DRAM burst

209system.physmem.avgRdBW 1161.56 # Average DRAM read bandwidth in MiByte/s

209system.physmem.avgRdBW 1161.52 # Average DRAM read bandwidth in MiByte/s

210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s

211system.physmem.avgRdBWSys 1161.56 # Average system read bandwidth in MiByte/s

211system.physmem.avgRdBWSys 1161.52 # Average system read bandwidth in MiByte/s

212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 9.07 # Data bus utilization in percentage
215system.physmem.busUtilRead 9.07 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 409 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 83.64 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

223system.physmem.avgGap 54989.78 # Average gap between requests

223system.physmem.avgGap 54991.82 # Average gap between requests

224system.physmem.pageHitRate 83.64 # Row buffer hit rate, read and write combined
225system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
227system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ)
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
230system.physmem_0.actBackEnergy 15849990 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 267750 # Energy for precharge background per rank (pJ)
232system.physmem_0.totalEnergy 20193420 # Total energy per rank (pJ)
233system.physmem_0.averagePower 854.974120 # Core power per rank (mW)
234system.physmem_0.memoryStateTime::IDLE 363750 # Time in different power states
235system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237system.physmem_0.memoryStateTime::ACT 22488750 # Time in different power states
238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 241920 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 132000 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ)
244system.physmem_1.actBackEnergy 15637950 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 453750 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 19309500 # Total energy per rank (pJ)
247system.physmem_1.averagePower 817.549616 # Core power per rank (mW)

248system.physmem_1.memoryStateTime::IDLE 2039000 # Time in different power states

248system.physmem_1.memoryStateTime::IDLE 2040000 # Time in different power states

249system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 22166500 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253system.cpu.branchPred.lookups 8026 # Number of BP lookups
254system.cpu.branchPred.condPredicted 5198 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 978 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 5876 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 3165 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 53.863172 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 554 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
262system.cpu_clk_domain.clock 500 # Clock period in ticks
263system.cpu.workload.num_syscalls 18 # Number of system calls

264system.cpu.numCycles 53887 # number of cpu cycles simulated

264system.cpu.numCycles 53889 # number of cpu cycles simulated

265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

267system.cpu.fetch.icacheStallCycles 13793 # Number of cycles fetch is stalled on an Icache miss

267system.cpu.fetch.icacheStallCycles 13792 # Number of cycles fetch is stalled on an Icache miss

268system.cpu.fetch.Insts 37180 # Number of instructions fetch has processed
269system.cpu.fetch.Branches 8026 # Number of branches that fetch encountered
270system.cpu.fetch.predictedBranches 3719 # Number of branches that fetch has predicted taken

271system.cpu.fetch.Cycles 15451 # Number of cycles fetch has run and was not squashing or blocked

271system.cpu.fetch.Cycles 15452 # Number of cycles fetch has run and was not squashing or blocked

272system.cpu.fetch.SquashCycles 2149 # Number of cycles fetch has spent squashing
273system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
274system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps
275system.cpu.fetch.CacheLines 6095 # Number of cache lines fetched
276system.cpu.fetch.IcacheSquashes 549 # Number of outstanding Icache misses that were squashed
277system.cpu.fetch.rateDist::samples 31410 # Number of instructions fetched each cycle (Total)
278system.cpu.fetch.rateDist::mean 1.183699 # Number of instructions fetched each cycle (Total)
279system.cpu.fetch.rateDist::stdev 2.297330 # Number of instructions fetched each cycle (Total)
280system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
281system.cpu.fetch.rateDist::0 20227 64.40% 64.40% # Number of instructions fetched each cycle (Total)
282system.cpu.fetch.rateDist::1 5497 17.50% 81.90% # Number of instructions fetched each cycle (Total)
283system.cpu.fetch.rateDist::2 701 2.23% 84.13% # Number of instructions fetched each cycle (Total)
284system.cpu.fetch.rateDist::3 561 1.79% 85.92% # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::4 758 2.41% 88.33% # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::5 907 2.89% 91.22% # Number of instructions fetched each cycle (Total)
287system.cpu.fetch.rateDist::6 332 1.06% 92.27% # Number of instructions fetched each cycle (Total)
288system.cpu.fetch.rateDist::7 377 1.20% 93.47% # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::8 2050 6.53% 100.00% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::total 31410 # Number of instructions fetched each cycle (Total)

294system.cpu.fetch.branchRate 0.148941 # Number of branch fetches per cycle
295system.cpu.fetch.rate 0.689962 # Number of inst fetches per cycle

294system.cpu.fetch.branchRate 0.148936 # Number of branch fetches per cycle
295system.cpu.fetch.rate 0.689937 # Number of inst fetches per cycle

296system.cpu.decode.IdleCycles 10981 # Number of cycles decode is idle
297system.cpu.decode.BlockedCycles 12209 # Number of cycles decode is blocked
298system.cpu.decode.RunCycles 6549 # Number of cycles decode is running
299system.cpu.decode.UnblockCycles 597 # Number of cycles decode is unblocking
300system.cpu.decode.SquashCycles 1074 # Number of cycles decode is squashing
301system.cpu.decode.DecodedInsts 28093 # Number of instructions handled by decode
302system.cpu.rename.SquashCycles 1074 # Number of cycles rename is squashing
303system.cpu.rename.IdleCycles 11557 # Number of cycles rename is idle
304system.cpu.rename.BlockCycles 929 # Number of cycles rename is blocking
305system.cpu.rename.serializeStallCycles 9876 # count of cycles rename stalled for serializing inst
306system.cpu.rename.RunCycles 6585 # Number of cycles rename is running
307system.cpu.rename.UnblockCycles 1389 # Number of cycles rename is unblocking
308system.cpu.rename.RenamedInsts 25671 # Number of instructions processed by rename
309system.cpu.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
310system.cpu.rename.SQFullEvents 994 # Number of times rename has blocked due to SQ full
311system.cpu.rename.RenamedOperands 23124 # Number of destination operands rename has renamed
312system.cpu.rename.RenameLookups 48097 # Number of register rename lookups that rename has made
313system.cpu.rename.int_rename_lookups 39637 # Number of integer rename lookups
314system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
315system.cpu.rename.UndoneMaps 9305 # Number of HB maps that are undone due to squashing
316system.cpu.rename.serializingInsts 731 # count of serializing insts renamed
317system.cpu.rename.tempSerializingInsts 747 # count of temporary serializing insts renamed
318system.cpu.rename.skidInsts 3478 # count of insts added to the skid buffer
319system.cpu.memDep0.insertedLoads 3489 # Number of loads inserted to the mem dependence unit.
320system.cpu.memDep0.insertedStores 2288 # Number of stores inserted to the mem dependence unit.
321system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
322system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
323system.cpu.iq.iqInstsAdded 22031 # Number of instructions added to the IQ (excludes non-spec)
324system.cpu.iq.iqNonSpecInstsAdded 704 # Number of non-speculative instructions added to the IQ
325system.cpu.iq.iqInstsIssued 20835 # Number of instructions issued
326system.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued
327system.cpu.iq.iqSquashedInstsExamined 8299 # Number of squashed instructions iterated over during squash; mainly for profiling
328system.cpu.iq.iqSquashedOperandsExamined 5262 # Number of squashed operands that are examined and possibly removed from graph
329system.cpu.iq.iqSquashedNonSpecRemoved 229 # Number of squashed non-spec instructions that were removed
330system.cpu.iq.issued_per_cycle::samples 31410 # Number of insts issued each cycle
331system.cpu.iq.issued_per_cycle::mean 0.663324 # Number of insts issued each cycle
332system.cpu.iq.issued_per_cycle::stdev 1.403192 # Number of insts issued each cycle
333system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
334system.cpu.iq.issued_per_cycle::0 23338 74.30% 74.30% # Number of insts issued each cycle
335system.cpu.iq.issued_per_cycle::1 2945 9.38% 83.68% # Number of insts issued each cycle
336system.cpu.iq.issued_per_cycle::2 1556 4.95% 88.63% # Number of insts issued each cycle
337system.cpu.iq.issued_per_cycle::3 1448 4.61% 93.24% # Number of insts issued each cycle
338system.cpu.iq.issued_per_cycle::4 938 2.99% 96.23% # Number of insts issued each cycle
339system.cpu.iq.issued_per_cycle::5 645 2.05% 98.28% # Number of insts issued each cycle
340system.cpu.iq.issued_per_cycle::6 357 1.14% 99.42% # Number of insts issued each cycle
341system.cpu.iq.issued_per_cycle::7 149 0.47% 99.89% # Number of insts issued each cycle
342system.cpu.iq.issued_per_cycle::8 34 0.11% 100.00% # Number of insts issued each cycle
343system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
344system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
345system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
346system.cpu.iq.issued_per_cycle::total 31410 # Number of insts issued each cycle
347system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
348system.cpu.iq.fu_full::IntAlu 59 33.33% 33.33% # attempts to use FU when none available
349system.cpu.iq.fu_full::IntMult 0 0.00% 33.33% # attempts to use FU when none available
350system.cpu.iq.fu_full::IntDiv 0 0.00% 33.33% # attempts to use FU when none available
351system.cpu.iq.fu_full::FloatAdd 0 0.00% 33.33% # attempts to use FU when none available
352system.cpu.iq.fu_full::FloatCmp 0 0.00% 33.33% # attempts to use FU when none available
353system.cpu.iq.fu_full::FloatCvt 0 0.00% 33.33% # attempts to use FU when none available
354system.cpu.iq.fu_full::FloatMult 0 0.00% 33.33% # attempts to use FU when none available
355system.cpu.iq.fu_full::FloatDiv 0 0.00% 33.33% # attempts to use FU when none available
356system.cpu.iq.fu_full::FloatSqrt 0 0.00% 33.33% # attempts to use FU when none available
357system.cpu.iq.fu_full::SimdAdd 0 0.00% 33.33% # attempts to use FU when none available
358system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 33.33% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdAlu 0 0.00% 33.33% # attempts to use FU when none available
360system.cpu.iq.fu_full::SimdCmp 0 0.00% 33.33% # attempts to use FU when none available
361system.cpu.iq.fu_full::SimdCvt 0 0.00% 33.33% # attempts to use FU when none available
362system.cpu.iq.fu_full::SimdMisc 0 0.00% 33.33% # attempts to use FU when none available
363system.cpu.iq.fu_full::SimdMult 0 0.00% 33.33% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 33.33% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdShift 0 0.00% 33.33% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 33.33% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdSqrt 0 0.00% 33.33% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 33.33% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 33.33% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 33.33% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 33.33% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 33.33% # attempts to use FU when none available
373system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 33.33% # attempts to use FU when none available
374system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 33.33% # attempts to use FU when none available
375system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.33% # attempts to use FU when none available
376system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 33.33% # attempts to use FU when none available
377system.cpu.iq.fu_full::MemRead 51 28.81% 62.15% # attempts to use FU when none available
378system.cpu.iq.fu_full::MemWrite 67 37.85% 100.00% # attempts to use FU when none available
379system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
380system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
381system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
382system.cpu.iq.FU_type_0::IntAlu 15392 73.88% 73.88% # Type of FU issued
383system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued
384system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued
385system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued
386system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued
387system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued
388system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued
389system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued
390system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued
391system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued
392system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued
393system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued
394system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued
395system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued
396system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued
397system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued
407system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued
408system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued
409system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued
410system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued
411system.cpu.iq.FU_type_0::MemRead 3355 16.10% 89.98% # Type of FU issued
412system.cpu.iq.FU_type_0::MemWrite 2088 10.02% 100.00% # Type of FU issued
413system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
414system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
415system.cpu.iq.FU_type_0::total 20835 # Type of FU issued

416system.cpu.iq.rate 0.386642 # Inst issue rate

416system.cpu.iq.rate 0.386628 # Inst issue rate

417system.cpu.iq.fu_busy_cnt 177 # FU busy when requested
418system.cpu.iq.fu_busy_rate 0.008495 # FU busy rate (busy events/executed inst)
419system.cpu.iq.int_inst_queue_reads 73265 # Number of integer instruction queue reads
420system.cpu.iq.int_inst_queue_writes 31060 # Number of integer instruction queue writes
421system.cpu.iq.int_inst_queue_wakeup_accesses 19408 # Number of integer instruction queue wakeup accesses
422system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
423system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
424system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
425system.cpu.iq.int_alu_accesses 21012 # Number of integer alu accesses
426system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
427system.cpu.iew.lsq.thread0.forwLoads 30 # Number of loads that had data forwarded from stores
428system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
429system.cpu.iew.lsq.thread0.squashedLoads 1264 # Number of loads squashed
430system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
431system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
432system.cpu.iew.lsq.thread0.squashedStores 840 # Number of stores squashed
433system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
434system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
435system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
436system.cpu.iew.lsq.thread0.cacheBlocked 30 # Number of times an access to memory failed due to the cache being blocked
437system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
438system.cpu.iew.iewSquashCycles 1074 # Number of cycles IEW is squashing
439system.cpu.iew.iewBlockCycles 918 # Number of cycles IEW is blocking
440system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
441system.cpu.iew.iewDispatchedInsts 23852 # Number of instructions dispatched to IQ
442system.cpu.iew.iewDispSquashedInsts 173 # Number of squashed instructions skipped by dispatch
443system.cpu.iew.iewDispLoadInsts 3489 # Number of dispatched load instructions
444system.cpu.iew.iewDispStoreInsts 2288 # Number of dispatched store instructions
445system.cpu.iew.iewDispNonSpecInsts 704 # Number of dispatched non-speculative instructions
446system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
447system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall
448system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
449system.cpu.iew.predictedTakenIncorrect 261 # Number of branches that were predicted taken incorrectly
450system.cpu.iew.predictedNotTakenIncorrect 835 # Number of branches that were predicted not taken incorrectly
451system.cpu.iew.branchMispredicts 1096 # Number of branch mispredicts detected at execute
452system.cpu.iew.iewExecutedInsts 20012 # Number of executed instructions
453system.cpu.iew.iewExecLoadInsts 3241 # Number of load instructions executed
454system.cpu.iew.iewExecSquashedInsts 823 # Number of squashed instructions skipped in execute
455system.cpu.iew.exec_swp 0 # number of swp insts executed
456system.cpu.iew.exec_nop 1117 # number of nop insts executed
457system.cpu.iew.exec_refs 5240 # number of memory reference insts executed
458system.cpu.iew.exec_branches 4296 # Number of branches executed
459system.cpu.iew.exec_stores 1999 # Number of stores executed

460system.cpu.iew.exec_rate 0.371370 # Inst execution rate

460system.cpu.iew.exec_rate 0.371356 # Inst execution rate

461system.cpu.iew.wb_sent 19648 # cumulative count of insts sent to commit
462system.cpu.iew.wb_count 19408 # cumulative count of insts written-back
463system.cpu.iew.wb_producers 9326 # num instructions producing a value
464system.cpu.iew.wb_consumers 12017 # num instructions consuming a value
465system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

466system.cpu.iew.wb_rate 0.360161 # insts written-back per cycle

466system.cpu.iew.wb_rate 0.360148 # insts written-back per cycle

467system.cpu.iew.wb_fanout 0.776067 # average fanout of values written-back
468system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
469system.cpu.commit.commitSquashedInsts 8625 # The number of squashed insts skipped by commit
470system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
471system.cpu.commit.branchMispredicts 978 # The number of times a branch was mispredicted
472system.cpu.commit.committed_per_cycle::samples 29597 # Number of insts commited each cycle
473system.cpu.commit.committed_per_cycle::mean 0.512282 # Number of insts commited each cycle
474system.cpu.commit.committed_per_cycle::stdev 1.339725 # Number of insts commited each cycle
475system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
476system.cpu.commit.committed_per_cycle::0 23176 78.31% 78.31% # Number of insts commited each cycle
477system.cpu.commit.committed_per_cycle::1 3360 11.35% 89.66% # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::2 1108 3.74% 93.40% # Number of insts commited each cycle
479system.cpu.commit.committed_per_cycle::3 619 2.09% 95.49% # Number of insts commited each cycle
480system.cpu.commit.committed_per_cycle::4 326 1.10% 96.59% # Number of insts commited each cycle
481system.cpu.commit.committed_per_cycle::5 270 0.91% 97.51% # Number of insts commited each cycle
482system.cpu.commit.committed_per_cycle::6 381 1.29% 98.79% # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::7 67 0.23% 99.02% # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::8 290 0.98% 100.00% # Number of insts commited each cycle
485system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
486system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
487system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
488system.cpu.commit.committed_per_cycle::total 29597 # Number of insts commited each cycle
489system.cpu.commit.committedInsts 15162 # Number of instructions committed
490system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
491system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
492system.cpu.commit.refs 3673 # Number of memory references committed
493system.cpu.commit.loads 2225 # Number of loads committed
494system.cpu.commit.membars 0 # Number of memory barriers committed
495system.cpu.commit.branches 3358 # Number of branches committed
496system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
497system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
498system.cpu.commit.function_calls 187 # Number of function calls committed.
499system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
500system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
501system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
502system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
503system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
504system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
505system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
506system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
507system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
508system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
509system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
510system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
511system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
512system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
513system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
514system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
515system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
516system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
517system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
518system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
519system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
520system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
521system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
522system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
523system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
524system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
525system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
526system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
527system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
528system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
529system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
530system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
531system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
532system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
533system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
534system.cpu.commit.bw_lim_events 290 # number cycles where commit BW limit reached
535system.cpu.rob.rob_reads 52271 # The number of ROB reads
536system.cpu.rob.rob_writes 49405 # The number of ROB writes
537system.cpu.timesIdled 197 # Number of times that the entire CPU went into an idle state and unscheduled itself

538system.cpu.idleCycles 22477 # Total number of cycles that the CPU has spent unscheduled due to idling

538system.cpu.idleCycles 22479 # Total number of cycles that the CPU has spent unscheduled due to idling

539system.cpu.committedInsts 14436 # Number of Instructions Simulated
540system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated

541system.cpu.cpi 3.732821 # CPI: Cycles Per Instruction
542system.cpu.cpi_total 3.732821 # CPI: Total CPI of All Threads
543system.cpu.ipc 0.267894 # IPC: Instructions Per Cycle
544system.cpu.ipc_total 0.267894 # IPC: Total IPC of All Threads

541system.cpu.cpi 3.732959 # CPI: Cycles Per Instruction
542system.cpu.cpi_total 3.732959 # CPI: Total CPI of All Threads
543system.cpu.ipc 0.267884 # IPC: Instructions Per Cycle
544system.cpu.ipc_total 0.267884 # IPC: Total IPC of All Threads

545system.cpu.int_regfile_reads 32029 # number of integer regfile reads
546system.cpu.int_regfile_writes 17799 # number of integer regfile writes
547system.cpu.misc_regfile_reads 6992 # number of misc regfile reads
548system.cpu.misc_regfile_writes 569 # number of misc regfile writes
549system.cpu.dcache.tags.replacements 0 # number of replacements

550system.cpu.dcache.tags.tagsinuse 98.068517 # Cycle average of tags in use

550system.cpu.dcache.tags.tagsinuse 98.069813 # Cycle average of tags in use

551system.cpu.dcache.tags.total_refs 4030 # Total number of references to valid blocks.
552system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks.
553system.cpu.dcache.tags.avg_refs 27.602740 # Average number of references to valid blocks.
554system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

555system.cpu.dcache.tags.occ_blocks::cpu.data 98.068517 # Average occupied blocks per requestor

555system.cpu.dcache.tags.occ_blocks::cpu.data 98.069813 # Average occupied blocks per requestor

556system.cpu.dcache.tags.occ_percent::cpu.data 0.023943 # Average percentage of cache occupancy
557system.cpu.dcache.tags.occ_percent::total 0.023943 # Average percentage of cache occupancy
558system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id
559system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id
560system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
561system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id
562system.cpu.dcache.tags.tag_accesses 9286 # Number of tag accesses
563system.cpu.dcache.tags.data_accesses 9286 # Number of data accesses
564system.cpu.dcache.ReadReq_hits::cpu.data 2991 # number of ReadReq hits
565system.cpu.dcache.ReadReq_hits::total 2991 # number of ReadReq hits
566system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
567system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
568system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
569system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
570system.cpu.dcache.demand_hits::cpu.data 4024 # number of demand (read+write) hits
571system.cpu.dcache.demand_hits::total 4024 # number of demand (read+write) hits
572system.cpu.dcache.overall_hits::cpu.data 4024 # number of overall hits
573system.cpu.dcache.overall_hits::total 4024 # number of overall hits
574system.cpu.dcache.ReadReq_misses::cpu.data 131 # number of ReadReq misses
575system.cpu.dcache.ReadReq_misses::total 131 # number of ReadReq misses
576system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
577system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
578system.cpu.dcache.demand_misses::cpu.data 540 # number of demand (read+write) misses
579system.cpu.dcache.demand_misses::total 540 # number of demand (read+write) misses
580system.cpu.dcache.overall_misses::cpu.data 540 # number of overall misses
581system.cpu.dcache.overall_misses::total 540 # number of overall misses
582system.cpu.dcache.ReadReq_miss_latency::cpu.data 9101000 # number of ReadReq miss cycles
583system.cpu.dcache.ReadReq_miss_latency::total 9101000 # number of ReadReq miss cycles
584system.cpu.dcache.WriteReq_miss_latency::cpu.data 26970477 # number of WriteReq miss cycles
585system.cpu.dcache.WriteReq_miss_latency::total 26970477 # number of WriteReq miss cycles
586system.cpu.dcache.demand_miss_latency::cpu.data 36071477 # number of demand (read+write) miss cycles
587system.cpu.dcache.demand_miss_latency::total 36071477 # number of demand (read+write) miss cycles
588system.cpu.dcache.overall_miss_latency::cpu.data 36071477 # number of overall miss cycles
589system.cpu.dcache.overall_miss_latency::total 36071477 # number of overall miss cycles
590system.cpu.dcache.ReadReq_accesses::cpu.data 3122 # number of ReadReq accesses(hits+misses)
591system.cpu.dcache.ReadReq_accesses::total 3122 # number of ReadReq accesses(hits+misses)
592system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
593system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
594system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
595system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
596system.cpu.dcache.demand_accesses::cpu.data 4564 # number of demand (read+write) accesses
597system.cpu.dcache.demand_accesses::total 4564 # number of demand (read+write) accesses
598system.cpu.dcache.overall_accesses::cpu.data 4564 # number of overall (read+write) accesses
599system.cpu.dcache.overall_accesses::total 4564 # number of overall (read+write) accesses
600system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041960 # miss rate for ReadReq accesses
601system.cpu.dcache.ReadReq_miss_rate::total 0.041960 # miss rate for ReadReq accesses
602system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
603system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
604system.cpu.dcache.demand_miss_rate::cpu.data 0.118317 # miss rate for demand accesses
605system.cpu.dcache.demand_miss_rate::total 0.118317 # miss rate for demand accesses
606system.cpu.dcache.overall_miss_rate::cpu.data 0.118317 # miss rate for overall accesses
607system.cpu.dcache.overall_miss_rate::total 0.118317 # miss rate for overall accesses
608system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69473.282443 # average ReadReq miss latency
609system.cpu.dcache.ReadReq_avg_miss_latency::total 69473.282443 # average ReadReq miss latency
610system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65942.486553 # average WriteReq miss latency
611system.cpu.dcache.WriteReq_avg_miss_latency::total 65942.486553 # average WriteReq miss latency
612system.cpu.dcache.demand_avg_miss_latency::cpu.data 66799.031481 # average overall miss latency
613system.cpu.dcache.demand_avg_miss_latency::total 66799.031481 # average overall miss latency
614system.cpu.dcache.overall_avg_miss_latency::cpu.data 66799.031481 # average overall miss latency
615system.cpu.dcache.overall_avg_miss_latency::total 66799.031481 # average overall miss latency
616system.cpu.dcache.blocked_cycles::no_mshrs 1282 # number of cycles access was blocked
617system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
618system.cpu.dcache.blocked::no_mshrs 27 # number of cycles access was blocked
619system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
620system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.481481 # average number of cycles each access was blocked
621system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
622system.cpu.dcache.fast_writes 0 # number of fast writes performed
623system.cpu.dcache.cache_copies 0 # number of cache copies performed
624system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
625system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
626system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
627system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
628system.cpu.dcache.demand_mshr_hits::cpu.data 393 # number of demand (read+write) MSHR hits
629system.cpu.dcache.demand_mshr_hits::total 393 # number of demand (read+write) MSHR hits
630system.cpu.dcache.overall_mshr_hits::cpu.data 393 # number of overall MSHR hits
631system.cpu.dcache.overall_mshr_hits::total 393 # number of overall MSHR hits
632system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses
633system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses
634system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
635system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
636system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
637system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses
638system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
639system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses
640system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5139000 # number of ReadReq MSHR miss cycles
641system.cpu.dcache.ReadReq_mshr_miss_latency::total 5139000 # number of ReadReq MSHR miss cycles
642system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6383500 # number of WriteReq MSHR miss cycles
643system.cpu.dcache.WriteReq_mshr_miss_latency::total 6383500 # number of WriteReq MSHR miss cycles
644system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11522500 # number of demand (read+write) MSHR miss cycles
645system.cpu.dcache.demand_mshr_miss_latency::total 11522500 # number of demand (read+write) MSHR miss cycles
646system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11522500 # number of overall MSHR miss cycles
647system.cpu.dcache.overall_mshr_miss_latency::total 11522500 # number of overall MSHR miss cycles
648system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020500 # mshr miss rate for ReadReq accesses
649system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020500 # mshr miss rate for ReadReq accesses
650system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
651system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
652system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032209 # mshr miss rate for demand accesses
653system.cpu.dcache.demand_mshr_miss_rate::total 0.032209 # mshr miss rate for demand accesses
654system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032209 # mshr miss rate for overall accesses
655system.cpu.dcache.overall_mshr_miss_rate::total 0.032209 # mshr miss rate for overall accesses
656system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80296.875000 # average ReadReq mshr miss latency
657system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80296.875000 # average ReadReq mshr miss latency
658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76909.638554 # average WriteReq mshr miss latency
659system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76909.638554 # average WriteReq mshr miss latency
660system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78384.353741 # average overall mshr miss latency
661system.cpu.dcache.demand_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency
662system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78384.353741 # average overall mshr miss latency
663system.cpu.dcache.overall_avg_mshr_miss_latency::total 78384.353741 # average overall mshr miss latency
664system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
665system.cpu.icache.tags.replacements 0 # number of replacements

666system.cpu.icache.tags.tagsinuse 190.286110 # Cycle average of tags in use

666system.cpu.icache.tags.tagsinuse 190.290590 # Cycle average of tags in use

667system.cpu.icache.tags.total_refs 5576 # Total number of references to valid blocks.
668system.cpu.icache.tags.sampled_refs 344 # Sample count of references to valid blocks.
669system.cpu.icache.tags.avg_refs 16.209302 # Average number of references to valid blocks.
670system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

671system.cpu.icache.tags.occ_blocks::cpu.inst 190.286110 # Average occupied blocks per requestor
672system.cpu.icache.tags.occ_percent::cpu.inst 0.092913 # Average percentage of cache occupancy
673system.cpu.icache.tags.occ_percent::total 0.092913 # Average percentage of cache occupancy

671system.cpu.icache.tags.occ_blocks::cpu.inst 190.290590 # Average occupied blocks per requestor
672system.cpu.icache.tags.occ_percent::cpu.inst 0.092915 # Average percentage of cache occupancy
673system.cpu.icache.tags.occ_percent::total 0.092915 # Average percentage of cache occupancy

674system.cpu.icache.tags.occ_task_id_blocks::1024 344 # Occupied blocks per task id
675system.cpu.icache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
676system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id
677system.cpu.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
678system.cpu.icache.tags.tag_accesses 12534 # Number of tag accesses
679system.cpu.icache.tags.data_accesses 12534 # Number of data accesses
680system.cpu.icache.ReadReq_hits::cpu.inst 5576 # number of ReadReq hits
681system.cpu.icache.ReadReq_hits::total 5576 # number of ReadReq hits
682system.cpu.icache.demand_hits::cpu.inst 5576 # number of demand (read+write) hits
683system.cpu.icache.demand_hits::total 5576 # number of demand (read+write) hits
684system.cpu.icache.overall_hits::cpu.inst 5576 # number of overall hits
685system.cpu.icache.overall_hits::total 5576 # number of overall hits
686system.cpu.icache.ReadReq_misses::cpu.inst 519 # number of ReadReq misses
687system.cpu.icache.ReadReq_misses::total 519 # number of ReadReq misses
688system.cpu.icache.demand_misses::cpu.inst 519 # number of demand (read+write) misses
689system.cpu.icache.demand_misses::total 519 # number of demand (read+write) misses
690system.cpu.icache.overall_misses::cpu.inst 519 # number of overall misses
691system.cpu.icache.overall_misses::total 519 # number of overall misses

692system.cpu.icache.ReadReq_miss_latency::cpu.inst 36198500 # number of ReadReq miss cycles
693system.cpu.icache.ReadReq_miss_latency::total 36198500 # number of ReadReq miss cycles
694system.cpu.icache.demand_miss_latency::cpu.inst 36198500 # number of demand (read+write) miss cycles
695system.cpu.icache.demand_miss_latency::total 36198500 # number of demand (read+write) miss cycles
696system.cpu.icache.overall_miss_latency::cpu.inst 36198500 # number of overall miss cycles
697system.cpu.icache.overall_miss_latency::total 36198500 # number of overall miss cycles

692system.cpu.icache.ReadReq_miss_latency::cpu.inst 36200500 # number of ReadReq miss cycles
693system.cpu.icache.ReadReq_miss_latency::total 36200500 # number of ReadReq miss cycles
694system.cpu.icache.demand_miss_latency::cpu.inst 36200500 # number of demand (read+write) miss cycles
695system.cpu.icache.demand_miss_latency::total 36200500 # number of demand (read+write) miss cycles
696system.cpu.icache.overall_miss_latency::cpu.inst 36200500 # number of overall miss cycles
697system.cpu.icache.overall_miss_latency::total 36200500 # number of overall miss cycles

698system.cpu.icache.ReadReq_accesses::cpu.inst 6095 # number of ReadReq accesses(hits+misses)
699system.cpu.icache.ReadReq_accesses::total 6095 # number of ReadReq accesses(hits+misses)
700system.cpu.icache.demand_accesses::cpu.inst 6095 # number of demand (read+write) accesses
701system.cpu.icache.demand_accesses::total 6095 # number of demand (read+write) accesses
702system.cpu.icache.overall_accesses::cpu.inst 6095 # number of overall (read+write) accesses
703system.cpu.icache.overall_accesses::total 6095 # number of overall (read+write) accesses
704system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085152 # miss rate for ReadReq accesses
705system.cpu.icache.ReadReq_miss_rate::total 0.085152 # miss rate for ReadReq accesses
706system.cpu.icache.demand_miss_rate::cpu.inst 0.085152 # miss rate for demand accesses
707system.cpu.icache.demand_miss_rate::total 0.085152 # miss rate for demand accesses
708system.cpu.icache.overall_miss_rate::cpu.inst 0.085152 # miss rate for overall accesses
709system.cpu.icache.overall_miss_rate::total 0.085152 # miss rate for overall accesses

710system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69746.628131 # average ReadReq miss latency
711system.cpu.icache.ReadReq_avg_miss_latency::total 69746.628131 # average ReadReq miss latency
712system.cpu.icache.demand_avg_miss_latency::cpu.inst 69746.628131 # average overall miss latency
713system.cpu.icache.demand_avg_miss_latency::total 69746.628131 # average overall miss latency
714system.cpu.icache.overall_avg_miss_latency::cpu.inst 69746.628131 # average overall miss latency
715system.cpu.icache.overall_avg_miss_latency::total 69746.628131 # average overall miss latency

710system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69750.481696 # average ReadReq miss latency
711system.cpu.icache.ReadReq_avg_miss_latency::total 69750.481696 # average ReadReq miss latency
712system.cpu.icache.demand_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency
713system.cpu.icache.demand_avg_miss_latency::total 69750.481696 # average overall miss latency
714system.cpu.icache.overall_avg_miss_latency::cpu.inst 69750.481696 # average overall miss latency
715system.cpu.icache.overall_avg_miss_latency::total 69750.481696 # average overall miss latency

716system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
717system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
718system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
719system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
720system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
721system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
722system.cpu.icache.fast_writes 0 # number of fast writes performed
723system.cpu.icache.cache_copies 0 # number of cache copies performed
724system.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits
725system.cpu.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits
726system.cpu.icache.demand_mshr_hits::cpu.inst 175 # number of demand (read+write) MSHR hits
727system.cpu.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits
728system.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits
729system.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits
730system.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses
731system.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses
732system.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses
733system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses
734system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
735system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses

736system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26530000 # number of ReadReq MSHR miss cycles
737system.cpu.icache.ReadReq_mshr_miss_latency::total 26530000 # number of ReadReq MSHR miss cycles
738system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26530000 # number of demand (read+write) MSHR miss cycles
739system.cpu.icache.demand_mshr_miss_latency::total 26530000 # number of demand (read+write) MSHR miss cycles
740system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26530000 # number of overall MSHR miss cycles
741system.cpu.icache.overall_mshr_miss_latency::total 26530000 # number of overall MSHR miss cycles

736system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26532000 # number of ReadReq MSHR miss cycles
737system.cpu.icache.ReadReq_mshr_miss_latency::total 26532000 # number of ReadReq MSHR miss cycles
738system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26532000 # number of demand (read+write) MSHR miss cycles
739system.cpu.icache.demand_mshr_miss_latency::total 26532000 # number of demand (read+write) MSHR miss cycles
740system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26532000 # number of overall MSHR miss cycles
741system.cpu.icache.overall_mshr_miss_latency::total 26532000 # number of overall MSHR miss cycles

742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for ReadReq accesses
743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.056440 # mshr miss rate for ReadReq accesses
744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for demand accesses
745system.cpu.icache.demand_mshr_miss_rate::total 0.056440 # mshr miss rate for demand accesses
746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.056440 # mshr miss rate for overall accesses
747system.cpu.icache.overall_mshr_miss_rate::total 0.056440 # mshr miss rate for overall accesses

748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77122.093023 # average ReadReq mshr miss latency
749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77122.093023 # average ReadReq mshr miss latency
750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77122.093023 # average overall mshr miss latency
751system.cpu.icache.demand_avg_mshr_miss_latency::total 77122.093023 # average overall mshr miss latency
752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77122.093023 # average overall mshr miss latency
753system.cpu.icache.overall_avg_mshr_miss_latency::total 77122.093023 # average overall mshr miss latency

748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77127.906977 # average ReadReq mshr miss latency
749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77127.906977 # average ReadReq mshr miss latency
750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency
751system.cpu.icache.demand_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency
752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77127.906977 # average overall mshr miss latency
753system.cpu.icache.overall_avg_mshr_miss_latency::total 77127.906977 # average overall mshr miss latency

754system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
755system.cpu.l2cache.tags.replacements 0 # number of replacements

756system.cpu.l2cache.tags.tagsinuse 223.995330 # Cycle average of tags in use

756system.cpu.l2cache.tags.tagsinuse 224.000415 # Cycle average of tags in use

757system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
758system.cpu.l2cache.tags.sampled_refs 405 # Sample count of references to valid blocks.
759system.cpu.l2cache.tags.avg_refs 0.004938 # Average number of references to valid blocks.
760system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

761system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.659398 # Average occupied blocks per requestor
762system.cpu.l2cache.tags.occ_blocks::cpu.data 34.335932 # Average occupied blocks per requestor

761system.cpu.l2cache.tags.occ_blocks::cpu.inst 189.663901 # Average occupied blocks per requestor
762system.cpu.l2cache.tags.occ_blocks::cpu.data 34.336514 # Average occupied blocks per requestor

763system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005788 # Average percentage of cache occupancy
764system.cpu.l2cache.tags.occ_percent::cpu.data 0.001048 # Average percentage of cache occupancy
765system.cpu.l2cache.tags.occ_percent::total 0.006836 # Average percentage of cache occupancy
766system.cpu.l2cache.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id
767system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
768system.cpu.l2cache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
769system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012360 # Percentage of cache occupancy per task id
770system.cpu.l2cache.tags.tag_accesses 4416 # Number of tag accesses
771system.cpu.l2cache.tags.data_accesses 4416 # Number of data accesses
772system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits
773system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits
774system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
775system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
776system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
777system.cpu.l2cache.overall_hits::total 2 # number of overall hits
778system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
779system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
780system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 342 # number of ReadCleanReq misses
781system.cpu.l2cache.ReadCleanReq_misses::total 342 # number of ReadCleanReq misses
782system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses
783system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses
784system.cpu.l2cache.demand_misses::cpu.inst 342 # number of demand (read+write) misses
785system.cpu.l2cache.demand_misses::cpu.data 147 # number of demand (read+write) misses
786system.cpu.l2cache.demand_misses::total 489 # number of demand (read+write) misses
787system.cpu.l2cache.overall_misses::cpu.inst 342 # number of overall misses
788system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses
789system.cpu.l2cache.overall_misses::total 489 # number of overall misses
790system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6258000 # number of ReadExReq miss cycles
791system.cpu.l2cache.ReadExReq_miss_latency::total 6258000 # number of ReadExReq miss cycles
792system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25992500 # number of ReadCleanReq miss cycles
793system.cpu.l2cache.ReadCleanReq_miss_latency::total 25992500 # number of ReadCleanReq miss cycles
794system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5044000 # number of ReadSharedReq miss cycles
795system.cpu.l2cache.ReadSharedReq_miss_latency::total 5044000 # number of ReadSharedReq miss cycles
796system.cpu.l2cache.demand_miss_latency::cpu.inst 25992500 # number of demand (read+write) miss cycles
797system.cpu.l2cache.demand_miss_latency::cpu.data 11302000 # number of demand (read+write) miss cycles
798system.cpu.l2cache.demand_miss_latency::total 37294500 # number of demand (read+write) miss cycles
799system.cpu.l2cache.overall_miss_latency::cpu.inst 25992500 # number of overall miss cycles
800system.cpu.l2cache.overall_miss_latency::cpu.data 11302000 # number of overall miss cycles
801system.cpu.l2cache.overall_miss_latency::total 37294500 # number of overall miss cycles
802system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
803system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
804system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 344 # number of ReadCleanReq accesses(hits+misses)
805system.cpu.l2cache.ReadCleanReq_accesses::total 344 # number of ReadCleanReq accesses(hits+misses)
806system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 64 # number of ReadSharedReq accesses(hits+misses)
807system.cpu.l2cache.ReadSharedReq_accesses::total 64 # number of ReadSharedReq accesses(hits+misses)
808system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses
809system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses
810system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses
811system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses
812system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses
813system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses
814system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
815system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
816system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994186 # miss rate for ReadCleanReq accesses
817system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994186 # miss rate for ReadCleanReq accesses
818system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
819system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
820system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994186 # miss rate for demand accesses
821system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
822system.cpu.l2cache.demand_miss_rate::total 0.995927 # miss rate for demand accesses
823system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994186 # miss rate for overall accesses
824system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
825system.cpu.l2cache.overall_miss_rate::total 0.995927 # miss rate for overall accesses
826system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75397.590361 # average ReadExReq miss latency
827system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75397.590361 # average ReadExReq miss latency
828system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76001.461988 # average ReadCleanReq miss latency
829system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76001.461988 # average ReadCleanReq miss latency
830system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78812.500000 # average ReadSharedReq miss latency
831system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78812.500000 # average ReadSharedReq miss latency
832system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76001.461988 # average overall miss latency
833system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76884.353741 # average overall miss latency
834system.cpu.l2cache.demand_avg_miss_latency::total 76266.871166 # average overall miss latency
835system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76001.461988 # average overall miss latency
836system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76884.353741 # average overall miss latency
837system.cpu.l2cache.overall_avg_miss_latency::total 76266.871166 # average overall miss latency
838system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
839system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
840system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
841system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
842system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
843system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
844system.cpu.l2cache.fast_writes 0 # number of fast writes performed
845system.cpu.l2cache.cache_copies 0 # number of cache copies performed
846system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
847system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
848system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 342 # number of ReadCleanReq MSHR misses
849system.cpu.l2cache.ReadCleanReq_mshr_misses::total 342 # number of ReadCleanReq MSHR misses
850system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses
851system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses
852system.cpu.l2cache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses
853system.cpu.l2cache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses
854system.cpu.l2cache.demand_mshr_misses::total 489 # number of demand (read+write) MSHR misses
855system.cpu.l2cache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses
856system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses
857system.cpu.l2cache.overall_mshr_misses::total 489 # number of overall MSHR misses
858system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5428000 # number of ReadExReq MSHR miss cycles
859system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5428000 # number of ReadExReq MSHR miss cycles
860system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22572500 # number of ReadCleanReq MSHR miss cycles
861system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22572500 # number of ReadCleanReq MSHR miss cycles
862system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4414000 # number of ReadSharedReq MSHR miss cycles
863system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4414000 # number of ReadSharedReq MSHR miss cycles
864system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22572500 # number of demand (read+write) MSHR miss cycles
865system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9842000 # number of demand (read+write) MSHR miss cycles
866system.cpu.l2cache.demand_mshr_miss_latency::total 32414500 # number of demand (read+write) MSHR miss cycles
867system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22572500 # number of overall MSHR miss cycles
868system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9842000 # number of overall MSHR miss cycles
869system.cpu.l2cache.overall_mshr_miss_latency::total 32414500 # number of overall MSHR miss cycles
870system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
871system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
872system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994186 # mshr miss rate for ReadCleanReq accesses
873system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994186 # mshr miss rate for ReadCleanReq accesses
874system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
875system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
876system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994186 # mshr miss rate for demand accesses
877system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
878system.cpu.l2cache.demand_mshr_miss_rate::total 0.995927 # mshr miss rate for demand accesses
879system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994186 # mshr miss rate for overall accesses
880system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
881system.cpu.l2cache.overall_mshr_miss_rate::total 0.995927 # mshr miss rate for overall accesses
882system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65397.590361 # average ReadExReq mshr miss latency
883system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65397.590361 # average ReadExReq mshr miss latency
884system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66001.461988 # average ReadCleanReq mshr miss latency
885system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66001.461988 # average ReadCleanReq mshr miss latency
886system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68968.750000 # average ReadSharedReq mshr miss latency
887system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68968.750000 # average ReadSharedReq mshr miss latency
888system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66001.461988 # average overall mshr miss latency
889system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency
890system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency
891system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66001.461988 # average overall mshr miss latency
892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66952.380952 # average overall mshr miss latency
893system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66287.321063 # average overall mshr miss latency
894system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

895system.cpu.toL2Bus.snoop_filter.tot_requests 491 # Total number of requests made to the snoop filter.
896system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 # Number of requests hitting in the snoop filter with a single holder of the requested data.
897system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
898system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
899system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
900system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

895system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution
896system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
897system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
898system.cpu.toL2Bus.trans_dist::ReadCleanReq 344 # Transaction distribution
899system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution
900system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
901system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
902system.cpu.toL2Bus.pkt_count::total 981 # Packet count per connected master and slave (bytes)
903system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes)
904system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
905system.cpu.toL2Bus.pkt_size::total 31360 # Cumulative packet size per connected master and slave (bytes)
906system.cpu.toL2Bus.snoops 0 # Total snoops (count)
907system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram

901system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution
902system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
903system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
904system.cpu.toL2Bus.trans_dist::ReadCleanReq 344 # Transaction distribution
905system.cpu.toL2Bus.trans_dist::ReadSharedReq 64 # Transaction distribution
906system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes)
907system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes)
908system.cpu.toL2Bus.pkt_count::total 981 # Packet count per connected master and slave (bytes)
909system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22016 # Cumulative packet size per connected master and slave (bytes)
910system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes)
911system.cpu.toL2Bus.pkt_size::total 31360 # Cumulative packet size per connected master and slave (bytes)
912system.cpu.toL2Bus.snoops 0 # Total snoops (count)
913system.cpu.toL2Bus.snoop_fanout::samples 491 # Request fanout histogram

908system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
909system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram

914system.cpu.toL2Bus.snoop_fanout::mean 0.004073 # Request fanout histogram
915system.cpu.toL2Bus.snoop_fanout::stdev 0.063757 # Request fanout histogram

910system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

916system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

911system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
912system.cpu.toL2Bus.snoop_fanout::1 491 100.00% 100.00% # Request fanout histogram

917system.cpu.toL2Bus.snoop_fanout::0 489 99.59% 99.59% # Request fanout histogram
918system.cpu.toL2Bus.snoop_fanout::1 2 0.41% 100.00% # Request fanout histogram

913system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
914system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

919system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
920system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

915system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram

921system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram