Cross Reference: /gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000026 # Number of seconds simulated
4sim_ticks 25944000 # Number of ticks simulated
5final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 14664 # Simulator instruction rate (inst/s)
8host_op_rate 14664 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 26353337 # Simulator tick rate (ticks/s)
10host_mem_usage 237548 # Number of bytes of host memory used
11host_seconds 0.98 # Real time elapsed on the host

7host_inst_rate 79125 # Simulator instruction rate (inst/s)
8host_op_rate 79119 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 142180718 # Simulator tick rate (ticks/s)
10host_mem_usage 289004 # Number of bytes of host memory used
11host_seconds 0.18 # Real time elapsed on the host

12sim_insts 14436 # Number of instructions simulated
13sim_ops 14436 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 22016 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9472 # Number of bytes read from this memory
18system.physmem.bytes_read::total 31488 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 22016 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 22016 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 492 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 848596978 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 365094049 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1213691027 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 848596978 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 848596978 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 848596978 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 365094049 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1213691027 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 492 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 31488 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 31488 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 107 # Per bank write bursts
45system.physmem.perBankRdBursts::1 28 # Per bank write bursts
46system.physmem.perBankRdBursts::2 51 # Per bank write bursts
47system.physmem.perBankRdBursts::3 24 # Per bank write bursts
48system.physmem.perBankRdBursts::4 20 # Per bank write bursts
49system.physmem.perBankRdBursts::5 0 # Per bank write bursts
50system.physmem.perBankRdBursts::6 32 # Per bank write bursts
51system.physmem.perBankRdBursts::7 35 # Per bank write bursts
52system.physmem.perBankRdBursts::8 4 # Per bank write bursts
53system.physmem.perBankRdBursts::9 2 # Per bank write bursts
54system.physmem.perBankRdBursts::10 1 # Per bank write bursts
55system.physmem.perBankRdBursts::11 0 # Per bank write bursts
56system.physmem.perBankRdBursts::12 57 # Per bank write bursts
57system.physmem.perBankRdBursts::13 31 # Per bank write bursts
58system.physmem.perBankRdBursts::14 61 # Per bank write bursts
59system.physmem.perBankRdBursts::15 39 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 25892500 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 492 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see

94system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see

94system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see

96system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 72 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 404.444444 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 264.526762 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 350.678412 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 12 16.67% 16.67% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 24 33.33% 50.00% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 7 9.72% 59.72% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 4 5.56% 65.28% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 4 5.56% 70.83% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 3 4.17% 75.00% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation

203system.physmem.totQLat 2648500 # Total ticks spent queuing
204system.physmem.totMemAccLat 11873500 # Total ticks spent from burst creation until serviced by the DRAM

203system.physmem.totQLat 2786000 # Total ticks spent queuing
204system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM

205system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers

206system.physmem.avgQLat 5383.13 # Average queueing delay per DRAM burst

206system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst

207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

208system.physmem.avgMemAccLat 24133.13 # Average memory access latency per DRAM burst

208system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst

209system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 9.48 # Data bus utilization in percentage
215system.physmem.busUtilRead 9.48 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 411 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223system.physmem.avgGap 52627.03 # Average gap between requests
224system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined
225system.physmem.memoryStateTime::IDLE 279250 # Time in different power states
226system.physmem.memoryStateTime::REF 780000 # Time in different power states
227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
228system.physmem.memoryStateTime::ACT 22761250 # Time in different power states
229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states

230system.membus.throughput 1211224175 # Throughput (bytes/s)

231system.membus.trans_dist::ReadReq 409 # Transaction distribution
232system.membus.trans_dist::ReadResp 408 # Transaction distribution
233system.membus.trans_dist::ReadExReq 83 # Transaction distribution
234system.membus.trans_dist::ReadExResp 83 # Transaction distribution
235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes)
236system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes)

230system.membus.trans_dist::ReadReq 409 # Transaction distribution
231system.membus.trans_dist::ReadResp 408 # Transaction distribution
232system.membus.trans_dist::ReadExReq 83 # Transaction distribution
233system.membus.trans_dist::ReadExResp 83 # Transaction distribution
234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 983 # Packet count per connected master and slave (bytes)
235system.membus.pkt_count::total 983 # Packet count per connected master and slave (bytes)

237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
238system.membus.tot_pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
239system.membus.data_through_bus 31424 # Total data (bytes)
240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)

236system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31424 # Cumulative packet size per connected master and slave (bytes)
237system.membus.pkt_size::total 31424 # Cumulative packet size per connected master and slave (bytes)
238system.membus.snoops 0 # Total snoops (count)
239system.membus.snoop_fanout::samples 492 # Request fanout histogram
240system.membus.snoop_fanout::mean 0 # Request fanout histogram
241system.membus.snoop_fanout::stdev 0 # Request fanout histogram
242system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
243system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram
244system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
245system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
246system.membus.snoop_fanout::min_value 0 # Request fanout histogram
247system.membus.snoop_fanout::max_value 0 # Request fanout histogram
248system.membus.snoop_fanout::total 492 # Request fanout histogram

241system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks)
242system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
243system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks)
244system.membus.respLayer1.utilization 17.7 # Layer utilization (%)
245system.cpu_clk_domain.clock 500 # Clock period in ticks
246system.cpu.branchPred.lookups 8578 # Number of BP lookups
247system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted
248system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect
249system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups
250system.cpu.branchPred.BTBHits 3046 # Number of BTB hits
251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
252system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage
253system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target.
254system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
255system.cpu.workload.num_syscalls 18 # Number of system calls
256system.cpu.numCycles 51889 # number of cpu cycles simulated
257system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
258system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
259system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss
260system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed
261system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered
262system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken
263system.cpu.fetch.Cycles 16187 # Number of cycles fetch has run and was not squashing or blocked
264system.cpu.fetch.SquashCycles 2310 # Number of cycles fetch has spent squashing
265system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
266system.cpu.fetch.PendingTrapStallCycles 1000 # Number of stall cycles due to pending traps
267system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
268system.cpu.fetch.CacheLines 6453 # Number of cache lines fetched
269system.cpu.fetch.IcacheSquashes 567 # Number of outstanding Icache misses that were squashed
270system.cpu.fetch.rateDist::samples 32510 # Number of instructions fetched each cycle (Total)
271system.cpu.fetch.rateDist::mean 1.239619 # Number of instructions fetched each cycle (Total)
272system.cpu.fetch.rateDist::stdev 2.385650 # Number of instructions fetched each cycle (Total)
273system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
274system.cpu.fetch.rateDist::0 20972 64.51% 64.51% # Number of instructions fetched each cycle (Total)
275system.cpu.fetch.rateDist::1 5490 16.89% 81.40% # Number of instructions fetched each cycle (Total)
276system.cpu.fetch.rateDist::2 661 2.03% 83.43% # Number of instructions fetched each cycle (Total)
277system.cpu.fetch.rateDist::3 508 1.56% 84.99% # Number of instructions fetched each cycle (Total)
278system.cpu.fetch.rateDist::4 826 2.54% 87.53% # Number of instructions fetched each cycle (Total)
279system.cpu.fetch.rateDist::5 909 2.80% 90.33% # Number of instructions fetched each cycle (Total)
280system.cpu.fetch.rateDist::6 334 1.03% 91.36% # Number of instructions fetched each cycle (Total)
281system.cpu.fetch.rateDist::7 369 1.14% 92.49% # Number of instructions fetched each cycle (Total)
282system.cpu.fetch.rateDist::8 2441 7.51% 100.00% # Number of instructions fetched each cycle (Total)
283system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
284system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::total 32510 # Number of instructions fetched each cycle (Total)
287system.cpu.fetch.branchRate 0.165314 # Number of branch fetches per cycle
288system.cpu.fetch.rate 0.776658 # Number of inst fetches per cycle
289system.cpu.decode.IdleCycles 11331 # Number of cycles decode is idle
290system.cpu.decode.BlockedCycles 12526 # Number of cycles decode is blocked
291system.cpu.decode.RunCycles 6844 # Number of cycles decode is running
292system.cpu.decode.UnblockCycles 654 # Number of cycles decode is unblocking
293system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing
294system.cpu.decode.DecodedInsts 30561 # Number of instructions handled by decode
295system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing
296system.cpu.rename.IdleCycles 11931 # Number of cycles rename is idle
297system.cpu.rename.BlockCycles 1436 # Number of cycles rename is blocking
298system.cpu.rename.serializeStallCycles 10087 # count of cycles rename stalled for serializing inst
299system.cpu.rename.RunCycles 6918 # Number of cycles rename is running
300system.cpu.rename.UnblockCycles 983 # Number of cycles rename is unblocking
301system.cpu.rename.RenamedInsts 27740 # Number of instructions processed by rename
302system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
303system.cpu.rename.SQFullEvents 585 # Number of times rename has blocked due to SQ full
304system.cpu.rename.RenamedOperands 25096 # Number of destination operands rename has renamed
305system.cpu.rename.RenameLookups 51799 # Number of register rename lookups that rename has made
306system.cpu.rename.int_rename_lookups 42923 # Number of integer rename lookups
307system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
308system.cpu.rename.UndoneMaps 11277 # Number of HB maps that are undone due to squashing
309system.cpu.rename.serializingInsts 768 # count of serializing insts renamed
310system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed
311system.cpu.rename.skidInsts 3783 # count of insts added to the skid buffer
312system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit.
313system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit.
314system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
315system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
316system.cpu.iq.iqInstsAdded 23657 # Number of instructions added to the IQ (excludes non-spec)
317system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ
318system.cpu.iq.iqInstsIssued 21921 # Number of instructions issued
319system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued
320system.cpu.iq.iqSquashedInstsExamined 9156 # Number of squashed instructions iterated over during squash; mainly for profiling
321system.cpu.iq.iqSquashedOperandsExamined 6522 # Number of squashed operands that are examined and possibly removed from graph
322system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed
323system.cpu.iq.issued_per_cycle::samples 32510 # Number of insts issued each cycle
324system.cpu.iq.issued_per_cycle::mean 0.674285 # Number of insts issued each cycle
325system.cpu.iq.issued_per_cycle::stdev 1.426342 # Number of insts issued each cycle
326system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
327system.cpu.iq.issued_per_cycle::0 24124 74.20% 74.20% # Number of insts issued each cycle
328system.cpu.iq.issued_per_cycle::1 3065 9.43% 83.63% # Number of insts issued each cycle
329system.cpu.iq.issued_per_cycle::2 1561 4.80% 88.43% # Number of insts issued each cycle
330system.cpu.iq.issued_per_cycle::3 1482 4.56% 92.99% # Number of insts issued each cycle
331system.cpu.iq.issued_per_cycle::4 945 2.91% 95.90% # Number of insts issued each cycle
332system.cpu.iq.issued_per_cycle::5 726 2.23% 98.13% # Number of insts issued each cycle
333system.cpu.iq.issued_per_cycle::6 412 1.27% 99.40% # Number of insts issued each cycle
334system.cpu.iq.issued_per_cycle::7 154 0.47% 99.87% # Number of insts issued each cycle
335system.cpu.iq.issued_per_cycle::8 41 0.13% 100.00% # Number of insts issued each cycle
336system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
337system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
338system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
339system.cpu.iq.issued_per_cycle::total 32510 # Number of insts issued each cycle
340system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
341system.cpu.iq.fu_full::IntAlu 112 49.56% 49.56% # attempts to use FU when none available
342system.cpu.iq.fu_full::IntMult 0 0.00% 49.56% # attempts to use FU when none available
343system.cpu.iq.fu_full::IntDiv 0 0.00% 49.56% # attempts to use FU when none available
344system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.56% # attempts to use FU when none available
345system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.56% # attempts to use FU when none available
346system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.56% # attempts to use FU when none available
347system.cpu.iq.fu_full::FloatMult 0 0.00% 49.56% # attempts to use FU when none available
348system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.56% # attempts to use FU when none available
349system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.56% # attempts to use FU when none available
350system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.56% # attempts to use FU when none available
351system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.56% # attempts to use FU when none available
352system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.56% # attempts to use FU when none available
353system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.56% # attempts to use FU when none available
354system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.56% # attempts to use FU when none available
355system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.56% # attempts to use FU when none available
356system.cpu.iq.fu_full::SimdMult 0 0.00% 49.56% # attempts to use FU when none available
357system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.56% # attempts to use FU when none available
358system.cpu.iq.fu_full::SimdShift 0 0.00% 49.56% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.56% # attempts to use FU when none available
360system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.56% # attempts to use FU when none available
361system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.56% # attempts to use FU when none available
362system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.56% # attempts to use FU when none available
363system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.56% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.56% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.56% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.56% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.56% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.56% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.56% # attempts to use FU when none available
370system.cpu.iq.fu_full::MemRead 49 21.68% 71.24% # attempts to use FU when none available
371system.cpu.iq.fu_full::MemWrite 65 28.76% 100.00% # attempts to use FU when none available
372system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
373system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
374system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
375system.cpu.iq.FU_type_0::IntAlu 16292 74.32% 74.32% # Type of FU issued
376system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued
377system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued
378system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued
379system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued
380system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued
381system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued
382system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued
383system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued
384system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued
385system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued
386system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued
387system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued
388system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued
389system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued
390system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued
391system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued
392system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued
393system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued
394system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued
395system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued
396system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued
397system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued
404system.cpu.iq.FU_type_0::MemRead 3506 15.99% 90.32% # Type of FU issued
405system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued
406system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
407system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
408system.cpu.iq.FU_type_0::total 21921 # Type of FU issued
409system.cpu.iq.rate 0.422459 # Inst issue rate
410system.cpu.iq.fu_busy_cnt 226 # FU busy when requested
411system.cpu.iq.fu_busy_rate 0.010310 # FU busy rate (busy events/executed inst)
412system.cpu.iq.int_inst_queue_reads 76635 # Number of integer instruction queue reads
413system.cpu.iq.int_inst_queue_writes 33566 # Number of integer instruction queue writes
414system.cpu.iq.int_inst_queue_wakeup_accesses 20237 # Number of integer instruction queue wakeup accesses
415system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
416system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
417system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
418system.cpu.iq.int_alu_accesses 22147 # Number of integer alu accesses
419system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
420system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores
421system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
422system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed
423system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
424system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
425system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed
426system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
427system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
428system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
429system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
430system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
431system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing
432system.cpu.iew.iewBlockCycles 1122 # Number of cycles IEW is blocking
433system.cpu.iew.iewUnblockCycles 322 # Number of cycles IEW is unblocking
434system.cpu.iew.iewDispatchedInsts 25510 # Number of instructions dispatched to IQ
435system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
436system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions
437system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions
438system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions
439system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
440system.cpu.iew.iewLSQFullEvents 318 # Number of times the LSQ has become full, causing a stall
441system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
442system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly
443system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly
444system.cpu.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute
445system.cpu.iew.iewExecutedInsts 20909 # Number of executed instructions
446system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed
447system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute
448system.cpu.iew.exec_swp 0 # number of swp insts executed
449system.cpu.iew.exec_nop 1127 # number of nop insts executed
450system.cpu.iew.exec_refs 5373 # number of memory reference insts executed
451system.cpu.iew.exec_branches 4425 # Number of branches executed
452system.cpu.iew.exec_stores 2024 # Number of stores executed
453system.cpu.iew.exec_rate 0.402956 # Inst execution rate
454system.cpu.iew.wb_sent 20494 # cumulative count of insts sent to commit
455system.cpu.iew.wb_count 20237 # cumulative count of insts written-back
456system.cpu.iew.wb_producers 9846 # num instructions producing a value
457system.cpu.iew.wb_consumers 12767 # num instructions consuming a value
458system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
459system.cpu.iew.wb_rate 0.390006 # insts written-back per cycle
460system.cpu.iew.wb_fanout 0.771207 # average fanout of values written-back
461system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
462system.cpu.commit.commitSquashedInsts 10297 # The number of squashed insts skipped by commit
463system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
464system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted
465system.cpu.commit.committed_per_cycle::samples 30446 # Number of insts commited each cycle
466system.cpu.commit.committed_per_cycle::mean 0.497996 # Number of insts commited each cycle
467system.cpu.commit.committed_per_cycle::stdev 1.310786 # Number of insts commited each cycle
468system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
469system.cpu.commit.committed_per_cycle::0 23926 78.59% 78.59% # Number of insts commited each cycle
470system.cpu.commit.committed_per_cycle::1 3430 11.27% 89.85% # Number of insts commited each cycle
471system.cpu.commit.committed_per_cycle::2 1163 3.82% 93.67% # Number of insts commited each cycle
472system.cpu.commit.committed_per_cycle::3 612 2.01% 95.68% # Number of insts commited each cycle
473system.cpu.commit.committed_per_cycle::4 344 1.13% 96.81% # Number of insts commited each cycle
474system.cpu.commit.committed_per_cycle::5 240 0.79% 97.60% # Number of insts commited each cycle
475system.cpu.commit.committed_per_cycle::6 396 1.30% 98.90% # Number of insts commited each cycle
476system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle
477system.cpu.commit.committed_per_cycle::8 273 0.90% 100.00% # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
479system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
480system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
481system.cpu.commit.committed_per_cycle::total 30446 # Number of insts commited each cycle
482system.cpu.commit.committedInsts 15162 # Number of instructions committed
483system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
484system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
485system.cpu.commit.refs 3673 # Number of memory references committed
486system.cpu.commit.loads 2225 # Number of loads committed
487system.cpu.commit.membars 0 # Number of memory barriers committed
488system.cpu.commit.branches 3358 # Number of branches committed
489system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
490system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
491system.cpu.commit.function_calls 187 # Number of function calls committed.
492system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
493system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
494system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
495system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
496system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
497system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
498system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
499system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
500system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
501system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
502system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
503system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
504system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
505system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
506system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
507system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
508system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
509system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
510system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
511system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
512system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
513system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
514system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
515system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
516system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
517system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
518system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
519system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
520system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
521system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
522system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
523system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
524system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
525system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
526system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
527system.cpu.commit.bw_lim_events 273 # number cycles where commit BW limit reached
528system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
529system.cpu.rob.rob_reads 54809 # The number of ROB reads
530system.cpu.rob.rob_writes 52996 # The number of ROB writes
531system.cpu.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself
532system.cpu.idleCycles 19379 # Total number of cycles that the CPU has spent unscheduled due to idling
533system.cpu.committedInsts 14436 # Number of Instructions Simulated
534system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
535system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction
536system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads
537system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle
538system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads
539system.cpu.int_regfile_reads 33400 # number of integer regfile reads
540system.cpu.int_regfile_writes 18599 # number of integer regfile writes
541system.cpu.misc_regfile_reads 7136 # number of misc regfile reads
542system.cpu.misc_regfile_writes 569 # number of misc regfile writes

249system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks)
250system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
251system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks)
252system.membus.respLayer1.utilization 17.7 # Layer utilization (%)
253system.cpu_clk_domain.clock 500 # Clock period in ticks
254system.cpu.branchPred.lookups 8578 # Number of BP lookups
255system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted
256system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect
257system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups
258system.cpu.branchPred.BTBHits 3046 # Number of BTB hits
259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
260system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage
261system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target.
262system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions.
263system.cpu.workload.num_syscalls 18 # Number of system calls
264system.cpu.numCycles 51889 # number of cpu cycles simulated
265system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
266system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
267system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss
268system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed
269system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered
270system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken
271system.cpu.fetch.Cycles 16187 # Number of cycles fetch has run and was not squashing or blocked
272system.cpu.fetch.SquashCycles 2310 # Number of cycles fetch has spent squashing
273system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
274system.cpu.fetch.PendingTrapStallCycles 1000 # Number of stall cycles due to pending traps
275system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
276system.cpu.fetch.CacheLines 6453 # Number of cache lines fetched
277system.cpu.fetch.IcacheSquashes 567 # Number of outstanding Icache misses that were squashed
278system.cpu.fetch.rateDist::samples 32510 # Number of instructions fetched each cycle (Total)
279system.cpu.fetch.rateDist::mean 1.239619 # Number of instructions fetched each cycle (Total)
280system.cpu.fetch.rateDist::stdev 2.385650 # Number of instructions fetched each cycle (Total)
281system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
282system.cpu.fetch.rateDist::0 20972 64.51% 64.51% # Number of instructions fetched each cycle (Total)
283system.cpu.fetch.rateDist::1 5490 16.89% 81.40% # Number of instructions fetched each cycle (Total)
284system.cpu.fetch.rateDist::2 661 2.03% 83.43% # Number of instructions fetched each cycle (Total)
285system.cpu.fetch.rateDist::3 508 1.56% 84.99% # Number of instructions fetched each cycle (Total)
286system.cpu.fetch.rateDist::4 826 2.54% 87.53% # Number of instructions fetched each cycle (Total)
287system.cpu.fetch.rateDist::5 909 2.80% 90.33% # Number of instructions fetched each cycle (Total)
288system.cpu.fetch.rateDist::6 334 1.03% 91.36% # Number of instructions fetched each cycle (Total)
289system.cpu.fetch.rateDist::7 369 1.14% 92.49% # Number of instructions fetched each cycle (Total)
290system.cpu.fetch.rateDist::8 2441 7.51% 100.00% # Number of instructions fetched each cycle (Total)
291system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
292system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
293system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
294system.cpu.fetch.rateDist::total 32510 # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.branchRate 0.165314 # Number of branch fetches per cycle
296system.cpu.fetch.rate 0.776658 # Number of inst fetches per cycle
297system.cpu.decode.IdleCycles 11331 # Number of cycles decode is idle
298system.cpu.decode.BlockedCycles 12526 # Number of cycles decode is blocked
299system.cpu.decode.RunCycles 6844 # Number of cycles decode is running
300system.cpu.decode.UnblockCycles 654 # Number of cycles decode is unblocking
301system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing
302system.cpu.decode.DecodedInsts 30561 # Number of instructions handled by decode
303system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing
304system.cpu.rename.IdleCycles 11931 # Number of cycles rename is idle
305system.cpu.rename.BlockCycles 1436 # Number of cycles rename is blocking
306system.cpu.rename.serializeStallCycles 10087 # count of cycles rename stalled for serializing inst
307system.cpu.rename.RunCycles 6918 # Number of cycles rename is running
308system.cpu.rename.UnblockCycles 983 # Number of cycles rename is unblocking
309system.cpu.rename.RenamedInsts 27740 # Number of instructions processed by rename
310system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
311system.cpu.rename.SQFullEvents 585 # Number of times rename has blocked due to SQ full
312system.cpu.rename.RenamedOperands 25096 # Number of destination operands rename has renamed
313system.cpu.rename.RenameLookups 51799 # Number of register rename lookups that rename has made
314system.cpu.rename.int_rename_lookups 42923 # Number of integer rename lookups
315system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed
316system.cpu.rename.UndoneMaps 11277 # Number of HB maps that are undone due to squashing
317system.cpu.rename.serializingInsts 768 # count of serializing insts renamed
318system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed
319system.cpu.rename.skidInsts 3783 # count of insts added to the skid buffer
320system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit.
321system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit.
322system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
323system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
324system.cpu.iq.iqInstsAdded 23657 # Number of instructions added to the IQ (excludes non-spec)
325system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ
326system.cpu.iq.iqInstsIssued 21921 # Number of instructions issued
327system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued
328system.cpu.iq.iqSquashedInstsExamined 9156 # Number of squashed instructions iterated over during squash; mainly for profiling
329system.cpu.iq.iqSquashedOperandsExamined 6522 # Number of squashed operands that are examined and possibly removed from graph
330system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed
331system.cpu.iq.issued_per_cycle::samples 32510 # Number of insts issued each cycle
332system.cpu.iq.issued_per_cycle::mean 0.674285 # Number of insts issued each cycle
333system.cpu.iq.issued_per_cycle::stdev 1.426342 # Number of insts issued each cycle
334system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
335system.cpu.iq.issued_per_cycle::0 24124 74.20% 74.20% # Number of insts issued each cycle
336system.cpu.iq.issued_per_cycle::1 3065 9.43% 83.63% # Number of insts issued each cycle
337system.cpu.iq.issued_per_cycle::2 1561 4.80% 88.43% # Number of insts issued each cycle
338system.cpu.iq.issued_per_cycle::3 1482 4.56% 92.99% # Number of insts issued each cycle
339system.cpu.iq.issued_per_cycle::4 945 2.91% 95.90% # Number of insts issued each cycle
340system.cpu.iq.issued_per_cycle::5 726 2.23% 98.13% # Number of insts issued each cycle
341system.cpu.iq.issued_per_cycle::6 412 1.27% 99.40% # Number of insts issued each cycle
342system.cpu.iq.issued_per_cycle::7 154 0.47% 99.87% # Number of insts issued each cycle
343system.cpu.iq.issued_per_cycle::8 41 0.13% 100.00% # Number of insts issued each cycle
344system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
345system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
346system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
347system.cpu.iq.issued_per_cycle::total 32510 # Number of insts issued each cycle
348system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
349system.cpu.iq.fu_full::IntAlu 112 49.56% 49.56% # attempts to use FU when none available
350system.cpu.iq.fu_full::IntMult 0 0.00% 49.56% # attempts to use FU when none available
351system.cpu.iq.fu_full::IntDiv 0 0.00% 49.56% # attempts to use FU when none available
352system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.56% # attempts to use FU when none available
353system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.56% # attempts to use FU when none available
354system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.56% # attempts to use FU when none available
355system.cpu.iq.fu_full::FloatMult 0 0.00% 49.56% # attempts to use FU when none available
356system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.56% # attempts to use FU when none available
357system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.56% # attempts to use FU when none available
358system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.56% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.56% # attempts to use FU when none available
360system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.56% # attempts to use FU when none available
361system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.56% # attempts to use FU when none available
362system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.56% # attempts to use FU when none available
363system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.56% # attempts to use FU when none available
364system.cpu.iq.fu_full::SimdMult 0 0.00% 49.56% # attempts to use FU when none available
365system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.56% # attempts to use FU when none available
366system.cpu.iq.fu_full::SimdShift 0 0.00% 49.56% # attempts to use FU when none available
367system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.56% # attempts to use FU when none available
368system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.56% # attempts to use FU when none available
369system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.56% # attempts to use FU when none available
370system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.56% # attempts to use FU when none available
371system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.56% # attempts to use FU when none available
372system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.56% # attempts to use FU when none available
373system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.56% # attempts to use FU when none available
374system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.56% # attempts to use FU when none available
375system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.56% # attempts to use FU when none available
376system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.56% # attempts to use FU when none available
377system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.56% # attempts to use FU when none available
378system.cpu.iq.fu_full::MemRead 49 21.68% 71.24% # attempts to use FU when none available
379system.cpu.iq.fu_full::MemWrite 65 28.76% 100.00% # attempts to use FU when none available
380system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
381system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
382system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
383system.cpu.iq.FU_type_0::IntAlu 16292 74.32% 74.32% # Type of FU issued
384system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued
385system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued
386system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued
387system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued
388system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued
389system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued
390system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued
391system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued
392system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued
393system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued
394system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued
395system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued
396system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued
397system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued
398system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued
399system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued
400system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued
401system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued
402system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued
403system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued
404system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued
405system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued
406system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued
407system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued
408system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued
409system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued
410system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued
411system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued
412system.cpu.iq.FU_type_0::MemRead 3506 15.99% 90.32% # Type of FU issued
413system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued
414system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
415system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
416system.cpu.iq.FU_type_0::total 21921 # Type of FU issued
417system.cpu.iq.rate 0.422459 # Inst issue rate
418system.cpu.iq.fu_busy_cnt 226 # FU busy when requested
419system.cpu.iq.fu_busy_rate 0.010310 # FU busy rate (busy events/executed inst)
420system.cpu.iq.int_inst_queue_reads 76635 # Number of integer instruction queue reads
421system.cpu.iq.int_inst_queue_writes 33566 # Number of integer instruction queue writes
422system.cpu.iq.int_inst_queue_wakeup_accesses 20237 # Number of integer instruction queue wakeup accesses
423system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
424system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
425system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
426system.cpu.iq.int_alu_accesses 22147 # Number of integer alu accesses
427system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses
428system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores
429system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
430system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed
431system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
432system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations
433system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed
434system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
435system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
436system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
437system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked
438system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
439system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing
440system.cpu.iew.iewBlockCycles 1122 # Number of cycles IEW is blocking
441system.cpu.iew.iewUnblockCycles 322 # Number of cycles IEW is unblocking
442system.cpu.iew.iewDispatchedInsts 25510 # Number of instructions dispatched to IQ
443system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch
444system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions
445system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions
446system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions
447system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
448system.cpu.iew.iewLSQFullEvents 318 # Number of times the LSQ has become full, causing a stall
449system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations
450system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly
451system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly
452system.cpu.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute
453system.cpu.iew.iewExecutedInsts 20909 # Number of executed instructions
454system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed
455system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute
456system.cpu.iew.exec_swp 0 # number of swp insts executed
457system.cpu.iew.exec_nop 1127 # number of nop insts executed
458system.cpu.iew.exec_refs 5373 # number of memory reference insts executed
459system.cpu.iew.exec_branches 4425 # Number of branches executed
460system.cpu.iew.exec_stores 2024 # Number of stores executed
461system.cpu.iew.exec_rate 0.402956 # Inst execution rate
462system.cpu.iew.wb_sent 20494 # cumulative count of insts sent to commit
463system.cpu.iew.wb_count 20237 # cumulative count of insts written-back
464system.cpu.iew.wb_producers 9846 # num instructions producing a value
465system.cpu.iew.wb_consumers 12767 # num instructions consuming a value
466system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
467system.cpu.iew.wb_rate 0.390006 # insts written-back per cycle
468system.cpu.iew.wb_fanout 0.771207 # average fanout of values written-back
469system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
470system.cpu.commit.commitSquashedInsts 10297 # The number of squashed insts skipped by commit
471system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
472system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted
473system.cpu.commit.committed_per_cycle::samples 30446 # Number of insts commited each cycle
474system.cpu.commit.committed_per_cycle::mean 0.497996 # Number of insts commited each cycle
475system.cpu.commit.committed_per_cycle::stdev 1.310786 # Number of insts commited each cycle
476system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
477system.cpu.commit.committed_per_cycle::0 23926 78.59% 78.59% # Number of insts commited each cycle
478system.cpu.commit.committed_per_cycle::1 3430 11.27% 89.85% # Number of insts commited each cycle
479system.cpu.commit.committed_per_cycle::2 1163 3.82% 93.67% # Number of insts commited each cycle
480system.cpu.commit.committed_per_cycle::3 612 2.01% 95.68% # Number of insts commited each cycle
481system.cpu.commit.committed_per_cycle::4 344 1.13% 96.81% # Number of insts commited each cycle
482system.cpu.commit.committed_per_cycle::5 240 0.79% 97.60% # Number of insts commited each cycle
483system.cpu.commit.committed_per_cycle::6 396 1.30% 98.90% # Number of insts commited each cycle
484system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle
485system.cpu.commit.committed_per_cycle::8 273 0.90% 100.00% # Number of insts commited each cycle
486system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
487system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
488system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
489system.cpu.commit.committed_per_cycle::total 30446 # Number of insts commited each cycle
490system.cpu.commit.committedInsts 15162 # Number of instructions committed
491system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed
492system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
493system.cpu.commit.refs 3673 # Number of memory references committed
494system.cpu.commit.loads 2225 # Number of loads committed
495system.cpu.commit.membars 0 # Number of memory barriers committed
496system.cpu.commit.branches 3358 # Number of branches committed
497system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
498system.cpu.commit.int_insts 12174 # Number of committed integer instructions.
499system.cpu.commit.function_calls 187 # Number of function calls committed.
500system.cpu.commit.op_class_0::No_OpClass 726 4.79% 4.79% # Class of committed instruction
501system.cpu.commit.op_class_0::IntAlu 10763 70.99% 75.77% # Class of committed instruction
502system.cpu.commit.op_class_0::IntMult 0 0.00% 75.77% # Class of committed instruction
503system.cpu.commit.op_class_0::IntDiv 0 0.00% 75.77% # Class of committed instruction
504system.cpu.commit.op_class_0::FloatAdd 0 0.00% 75.77% # Class of committed instruction
505system.cpu.commit.op_class_0::FloatCmp 0 0.00% 75.77% # Class of committed instruction
506system.cpu.commit.op_class_0::FloatCvt 0 0.00% 75.77% # Class of committed instruction
507system.cpu.commit.op_class_0::FloatMult 0 0.00% 75.77% # Class of committed instruction
508system.cpu.commit.op_class_0::FloatDiv 0 0.00% 75.77% # Class of committed instruction
509system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 75.77% # Class of committed instruction
510system.cpu.commit.op_class_0::SimdAdd 0 0.00% 75.77% # Class of committed instruction
511system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 75.77% # Class of committed instruction
512system.cpu.commit.op_class_0::SimdAlu 0 0.00% 75.77% # Class of committed instruction
513system.cpu.commit.op_class_0::SimdCmp 0 0.00% 75.77% # Class of committed instruction
514system.cpu.commit.op_class_0::SimdCvt 0 0.00% 75.77% # Class of committed instruction
515system.cpu.commit.op_class_0::SimdMisc 0 0.00% 75.77% # Class of committed instruction
516system.cpu.commit.op_class_0::SimdMult 0 0.00% 75.77% # Class of committed instruction
517system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 75.77% # Class of committed instruction
518system.cpu.commit.op_class_0::SimdShift 0 0.00% 75.77% # Class of committed instruction
519system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 75.77% # Class of committed instruction
520system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 75.77% # Class of committed instruction
521system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 75.77% # Class of committed instruction
522system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 75.77% # Class of committed instruction
523system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 75.77% # Class of committed instruction
524system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 75.77% # Class of committed instruction
525system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 75.77% # Class of committed instruction
526system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 75.77% # Class of committed instruction
527system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 75.77% # Class of committed instruction
528system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 75.77% # Class of committed instruction
529system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 75.77% # Class of committed instruction
530system.cpu.commit.op_class_0::MemRead 2225 14.67% 90.45% # Class of committed instruction
531system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Class of committed instruction
532system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
533system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
534system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
535system.cpu.commit.bw_lim_events 273 # number cycles where commit BW limit reached
536system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
537system.cpu.rob.rob_reads 54809 # The number of ROB reads
538system.cpu.rob.rob_writes 52996 # The number of ROB writes
539system.cpu.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself
540system.cpu.idleCycles 19379 # Total number of cycles that the CPU has spent unscheduled due to idling
541system.cpu.committedInsts 14436 # Number of Instructions Simulated
542system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated
543system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction
544system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads
545system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle
546system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads
547system.cpu.int_regfile_reads 33400 # number of integer regfile reads
548system.cpu.int_regfile_writes 18599 # number of integer regfile writes
549system.cpu.misc_regfile_reads 7136 # number of misc regfile reads
550system.cpu.misc_regfile_writes 569 # number of misc regfile writes

543system.cpu.toL2Bus.throughput 1216157879 # Throughput (bytes/s)

544system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution
545system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
546system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
547system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
548system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes)
549system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes)
550system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes)

551system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution
552system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution
553system.cpu.toL2Bus.trans_dist::ReadExReq 83 # Transaction distribution
554system.cpu.toL2Bus.trans_dist::ReadExResp 83 # Transaction distribution
555system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes)
556system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 295 # Packet count per connected master and slave (bytes)
557system.cpu.toL2Bus.pkt_count::total 987 # Packet count per connected master and slave (bytes)

551system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
552system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
553system.cpu.toL2Bus.tot_pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
554system.cpu.toL2Bus.data_through_bus 31552 # Total data (bytes)
555system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)

558system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes)
559system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes)
560system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
561system.cpu.toL2Bus.snoops 0 # Total snoops (count)
562system.cpu.toL2Bus.snoop_fanout::samples 494 # Request fanout histogram
563system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
564system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
565system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
566system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
567system.cpu.toL2Bus.snoop_fanout::1 494 100.00% 100.00% # Request fanout histogram
568system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
569system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
570system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
571system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
572system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram

556system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks)
557system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
558system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks)
559system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
560system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks)
561system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
562system.cpu.icache.tags.replacements 0 # number of replacements

573system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks)
574system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
575system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks)
576system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
577system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks)
578system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
579system.cpu.icache.tags.replacements 0 # number of replacements

563system.cpu.icache.tags.tagsinuse 192.510615 # Cycle average of tags in use

580system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use

564system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks.
565system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks.
566system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks.
567system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

581system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks.
582system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks.
583system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks.
584system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

568system.cpu.icache.tags.occ_blocks::cpu.inst 192.510615 # Average occupied blocks per requestor

585system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor

569system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy
570system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy
571system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id
572system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
573system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id
574system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id
575system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses
576system.cpu.icache.tags.data_accesses 13252 # Number of data accesses
577system.cpu.icache.ReadReq_hits::cpu.inst 5925 # number of ReadReq hits
578system.cpu.icache.ReadReq_hits::total 5925 # number of ReadReq hits
579system.cpu.icache.demand_hits::cpu.inst 5925 # number of demand (read+write) hits
580system.cpu.icache.demand_hits::total 5925 # number of demand (read+write) hits
581system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits
582system.cpu.icache.overall_hits::total 5925 # number of overall hits
583system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses
584system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses
585system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses
586system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses
587system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses
588system.cpu.icache.overall_misses::total 528 # number of overall misses

586system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy
587system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy
588system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id
589system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
590system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id
591system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id
592system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses
593system.cpu.icache.tags.data_accesses 13252 # Number of data accesses
594system.cpu.icache.ReadReq_hits::cpu.inst 5925 # number of ReadReq hits
595system.cpu.icache.ReadReq_hits::total 5925 # number of ReadReq hits
596system.cpu.icache.demand_hits::cpu.inst 5925 # number of demand (read+write) hits
597system.cpu.icache.demand_hits::total 5925 # number of demand (read+write) hits
598system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits
599system.cpu.icache.overall_hits::total 5925 # number of overall hits
600system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses
601system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses
602system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses
603system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses
604system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses
605system.cpu.icache.overall_misses::total 528 # number of overall misses

589system.cpu.icache.ReadReq_miss_latency::cpu.inst 32454000 # number of ReadReq miss cycles
590system.cpu.icache.ReadReq_miss_latency::total 32454000 # number of ReadReq miss cycles
591system.cpu.icache.demand_miss_latency::cpu.inst 32454000 # number of demand (read+write) miss cycles
592system.cpu.icache.demand_miss_latency::total 32454000 # number of demand (read+write) miss cycles
593system.cpu.icache.overall_miss_latency::cpu.inst 32454000 # number of overall miss cycles
594system.cpu.icache.overall_miss_latency::total 32454000 # number of overall miss cycles

606system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles
607system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles
608system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles
609system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles
610system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles
611system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles

595system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses)
596system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses)
597system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses
598system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses
599system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses
600system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses
601system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses
602system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses
603system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses
604system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses
605system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses
606system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses

612system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses)
613system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses)
614system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses
615system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses
616system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses
617system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses
618system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses
619system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses
620system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses
621system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses
622system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses
623system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses

607system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61465.909091 # average ReadReq miss latency
608system.cpu.icache.ReadReq_avg_miss_latency::total 61465.909091 # average ReadReq miss latency
609system.cpu.icache.demand_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency
610system.cpu.icache.demand_avg_miss_latency::total 61465.909091 # average overall miss latency
611system.cpu.icache.overall_avg_miss_latency::cpu.inst 61465.909091 # average overall miss latency
612system.cpu.icache.overall_avg_miss_latency::total 61465.909091 # average overall miss latency

624system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency
625system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency
626system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
627system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency
628system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency
629system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency

613system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked
614system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
615system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
616system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
617system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked
618system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
619system.cpu.icache.fast_writes 0 # number of fast writes performed
620system.cpu.icache.cache_copies 0 # number of cache copies performed
621system.cpu.icache.ReadReq_mshr_hits::cpu.inst 182 # number of ReadReq MSHR hits
622system.cpu.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits
623system.cpu.icache.demand_mshr_hits::cpu.inst 182 # number of demand (read+write) MSHR hits
624system.cpu.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits
625system.cpu.icache.overall_mshr_hits::cpu.inst 182 # number of overall MSHR hits
626system.cpu.icache.overall_mshr_hits::total 182 # number of overall MSHR hits
627system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses
628system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses
629system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses
630system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses
631system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses
632system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses

630system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked
631system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
632system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
633system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
634system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked
635system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
636system.cpu.icache.fast_writes 0 # number of fast writes performed
637system.cpu.icache.cache_copies 0 # number of cache copies performed
638system.cpu.icache.ReadReq_mshr_hits::cpu.inst 182 # number of ReadReq MSHR hits
639system.cpu.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits
640system.cpu.icache.demand_mshr_hits::cpu.inst 182 # number of demand (read+write) MSHR hits
641system.cpu.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits
642system.cpu.icache.overall_mshr_hits::cpu.inst 182 # number of overall MSHR hits
643system.cpu.icache.overall_mshr_hits::total 182 # number of overall MSHR hits
644system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses
645system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses
646system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses
647system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses
648system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses
649system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses

633system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23048750 # number of ReadReq MSHR miss cycles
634system.cpu.icache.ReadReq_mshr_miss_latency::total 23048750 # number of ReadReq MSHR miss cycles
635system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23048750 # number of demand (read+write) MSHR miss cycles
636system.cpu.icache.demand_mshr_miss_latency::total 23048750 # number of demand (read+write) MSHR miss cycles
637system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23048750 # number of overall MSHR miss cycles
638system.cpu.icache.overall_mshr_miss_latency::total 23048750 # number of overall MSHR miss cycles

650system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles
651system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles
652system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles
653system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles
654system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles
655system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles

639system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses
640system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses
641system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses
642system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses
643system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses
644system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses

656system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses
657system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses
658system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses
659system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses
660system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses
661system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses

645system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66614.884393 # average ReadReq mshr miss latency
646system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66614.884393 # average ReadReq mshr miss latency
647system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency
648system.cpu.icache.demand_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency
649system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66614.884393 # average overall mshr miss latency
650system.cpu.icache.overall_avg_mshr_miss_latency::total 66614.884393 # average overall mshr miss latency

662system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency
663system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency
664system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency
665system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency
666system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency
667system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency

651system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
652system.cpu.l2cache.tags.replacements 0 # number of replacements
653system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use
654system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
655system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks.
656system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks.
657system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

668system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
669system.cpu.l2cache.tags.replacements 0 # number of replacements
670system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use
671system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks.
672system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks.
673system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks.
674system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

658system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902478 # Average occupied blocks per requestor
659system.cpu.l2cache.tags.occ_blocks::cpu.data 34.634175 # Average occupied blocks per requestor

675system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor
676system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor

660system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy
661system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy
662system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy
663system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id
664system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
665system.cpu.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
666system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id
667system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses
668system.cpu.l2cache.tags.data_accesses 4443 # Number of data accesses
669system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
670system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
671system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
672system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
673system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
674system.cpu.l2cache.overall_hits::total 2 # number of overall hits
675system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses
676system.cpu.l2cache.ReadReq_misses::cpu.data 65 # number of ReadReq misses
677system.cpu.l2cache.ReadReq_misses::total 409 # number of ReadReq misses
678system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
679system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
680system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses
681system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses
682system.cpu.l2cache.demand_misses::total 492 # number of demand (read+write) misses
683system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses
684system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses
685system.cpu.l2cache.overall_misses::total 492 # number of overall misses

677system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy
678system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy
679system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy
680system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id
681system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
682system.cpu.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id
683system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id
684system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses
685system.cpu.l2cache.tags.data_accesses 4443 # Number of data accesses
686system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
687system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
688system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
689system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
690system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
691system.cpu.l2cache.overall_hits::total 2 # number of overall hits
692system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses
693system.cpu.l2cache.ReadReq_misses::cpu.data 65 # number of ReadReq misses
694system.cpu.l2cache.ReadReq_misses::total 409 # number of ReadReq misses
695system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses
696system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses
697system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses
698system.cpu.l2cache.demand_misses::cpu.data 148 # number of demand (read+write) misses
699system.cpu.l2cache.demand_misses::total 492 # number of demand (read+write) misses
700system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses
701system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses
702system.cpu.l2cache.overall_misses::total 492 # number of overall misses

686system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22682250 # number of ReadReq miss cycles
687system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4667500 # number of ReadReq miss cycles

703system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles
704system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles

688system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles
689system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles
690system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles

705system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles
706system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles
707system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles

691system.cpu.l2cache.demand_miss_latency::cpu.inst 22682250 # number of demand (read+write) miss cycles
692system.cpu.l2cache.demand_miss_latency::cpu.data 10818500 # number of demand (read+write) miss cycles

708system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles
709system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles

693system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles

710system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles

694system.cpu.l2cache.overall_miss_latency::cpu.inst 22682250 # number of overall miss cycles
695system.cpu.l2cache.overall_miss_latency::cpu.data 10818500 # number of overall miss cycles

711system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles
712system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles

696system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles
697system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses)
698system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses)
699system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses)
700system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
701system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
702system.cpu.l2cache.demand_accesses::cpu.inst 346 # number of demand (read+write) accesses
703system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
704system.cpu.l2cache.demand_accesses::total 494 # number of demand (read+write) accesses
705system.cpu.l2cache.overall_accesses::cpu.inst 346 # number of overall (read+write) accesses
706system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
707system.cpu.l2cache.overall_accesses::total 494 # number of overall (read+write) accesses
708system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994220 # miss rate for ReadReq accesses
709system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
710system.cpu.l2cache.ReadReq_miss_rate::total 0.995134 # miss rate for ReadReq accesses
711system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
712system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
713system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses
714system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
715system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses
716system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses
717system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
718system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses

713system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles
714system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses)
715system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses)
716system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses)
717system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses)
718system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses)
719system.cpu.l2cache.demand_accesses::cpu.inst 346 # number of demand (read+write) accesses
720system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses
721system.cpu.l2cache.demand_accesses::total 494 # number of demand (read+write) accesses
722system.cpu.l2cache.overall_accesses::cpu.inst 346 # number of overall (read+write) accesses
723system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses
724system.cpu.l2cache.overall_accesses::total 494 # number of overall (read+write) accesses
725system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994220 # miss rate for ReadReq accesses
726system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
727system.cpu.l2cache.ReadReq_miss_rate::total 0.995134 # miss rate for ReadReq accesses
728system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
729system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
730system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994220 # miss rate for demand accesses
731system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
732system.cpu.l2cache.demand_miss_rate::total 0.995951 # miss rate for demand accesses
733system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses
734system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
735system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses

719system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65936.773256 # average ReadReq miss latency
720system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71807.692308 # average ReadReq miss latency

736system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency
737system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency

721system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency
722system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency
723system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency

738system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency
739system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency
740system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency

724system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency
725system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency

741system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency
742system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency

726system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency

743system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency

727system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65936.773256 # average overall miss latency
728system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73097.972973 # average overall miss latency

744system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency
745system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency

729system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency
730system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
731system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
732system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
733system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
734system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
735system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
736system.cpu.l2cache.fast_writes 0 # number of fast writes performed
737system.cpu.l2cache.cache_copies 0 # number of cache copies performed
738system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses
739system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
740system.cpu.l2cache.ReadReq_mshr_misses::total 409 # number of ReadReq MSHR misses
741system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
742system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
743system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses
744system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
745system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses
746system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
747system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
748system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses

746system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency
747system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
748system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
749system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
750system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
751system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
752system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
753system.cpu.l2cache.fast_writes 0 # number of fast writes performed
754system.cpu.l2cache.cache_copies 0 # number of cache copies performed
755system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses
756system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
757system.cpu.l2cache.ReadReq_mshr_misses::total 409 # number of ReadReq MSHR misses
758system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses
759system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses
760system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses
761system.cpu.l2cache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
762system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses
763system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
764system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
765system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses

749system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18356250 # number of ReadReq MSHR miss cycles
750system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3880500 # number of ReadReq MSHR miss cycles

766system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles
767system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles

751system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles
752system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles
753system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles

768system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles
769system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles
770system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles

754system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18356250 # number of demand (read+write) MSHR miss cycles
755system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9012000 # number of demand (read+write) MSHR miss cycles

771system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles
772system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles

756system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles

773system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles

757system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18356250 # number of overall MSHR miss cycles
758system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9012000 # number of overall MSHR miss cycles

774system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles
775system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles

759system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles
760system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses
761system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
762system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses
763system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
764system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
765system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses
766system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
767system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses
768system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses
769system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
770system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses

776system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles
777system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses
778system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
779system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses
780system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
781system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
782system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for demand accesses
783system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
784system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 # mshr miss rate for demand accesses
785system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses
786system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
787system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses

771system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53361.191860 # average ReadReq mshr miss latency
772system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59700 # average ReadReq mshr miss latency

788system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency
789system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency

773system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency
774system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency
775system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency

790system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency
791system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency
792system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency

776system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency
777system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency

793system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency
794system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency

778system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency

795system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency

779system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53361.191860 # average overall mshr miss latency
780system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60891.891892 # average overall mshr miss latency

796system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency
797system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency

781system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency
782system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
783system.cpu.dcache.tags.replacements 0 # number of replacements

798system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency
799system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
800system.cpu.dcache.tags.replacements 0 # number of replacements

784system.cpu.dcache.tags.tagsinuse 98.823641 # Cycle average of tags in use

801system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use

785system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks.
786system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
787system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks.
788system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

802system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks.
803system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks.
804system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks.
805system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

789system.cpu.dcache.tags.occ_blocks::cpu.data 98.823641 # Average occupied blocks per requestor

806system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor

790system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy
791system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy
792system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
793system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
794system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
795system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id
796system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses
797system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses
798system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits
799system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits
800system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
801system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
802system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
803system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
804system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits
805system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits
806system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits
807system.cpu.dcache.overall_hits::total 4118 # number of overall hits
808system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses
809system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses
810system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
811system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
812system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses
813system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses
814system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses
815system.cpu.dcache.overall_misses::total 548 # number of overall misses

807system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy
808system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy
809system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id
810system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
811system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id
812system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id
813system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses
814system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses
815system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits
816system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits
817system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits
818system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits
819system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
820system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
821system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits
822system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits
823system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits
824system.cpu.dcache.overall_hits::total 4118 # number of overall hits
825system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses
826system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses
827system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses
828system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses
829system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses
830system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses
831system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses
832system.cpu.dcache.overall_misses::total 548 # number of overall misses

816system.cpu.dcache.ReadReq_miss_latency::cpu.data 8661750 # number of ReadReq miss cycles
817system.cpu.dcache.ReadReq_miss_latency::total 8661750 # number of ReadReq miss cycles

833system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles
834system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles

818system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles
819system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles

835system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles
836system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles

820system.cpu.dcache.demand_miss_latency::cpu.data 34754974 # number of demand (read+write) miss cycles
821system.cpu.dcache.demand_miss_latency::total 34754974 # number of demand (read+write) miss cycles
822system.cpu.dcache.overall_miss_latency::cpu.data 34754974 # number of overall miss cycles
823system.cpu.dcache.overall_miss_latency::total 34754974 # number of overall miss cycles

837system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles
838system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles
839system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles
840system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles

824system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses)
825system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses)
826system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
827system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
828system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
829system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
830system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses
831system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses
832system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses
833system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses
834system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses
835system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses
836system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
837system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
838system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses
839system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses
840system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses
841system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses

841system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses)
842system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses)
843system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
844system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
845system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
846system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
847system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses
848system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses
849system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses
850system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses
851system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses
852system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses
853system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses
854system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses
855system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses
856system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses
857system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses
858system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses

842system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62314.748201 # average ReadReq miss latency
843system.cpu.dcache.ReadReq_avg_miss_latency::total 62314.748201 # average ReadReq miss latency

859system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency
860system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency

844system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency
845system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency

861system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency
862system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency

846system.cpu.dcache.demand_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency
847system.cpu.dcache.demand_avg_miss_latency::total 63421.485401 # average overall miss latency
848system.cpu.dcache.overall_avg_miss_latency::cpu.data 63421.485401 # average overall miss latency
849system.cpu.dcache.overall_avg_miss_latency::total 63421.485401 # average overall miss latency

863system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency
864system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency
865system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency
866system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency

850system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked
851system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
852system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
853system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
854system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked
855system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
856system.cpu.dcache.fast_writes 0 # number of fast writes performed
857system.cpu.dcache.cache_copies 0 # number of cache copies performed
858system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits
859system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
860system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
861system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
862system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits
863system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits
864system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits
865system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits
866system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
867system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
868system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
869system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
870system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
871system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
872system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
873system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses

867system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked
868system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
869system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
870system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
871system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked
872system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
873system.cpu.dcache.fast_writes 0 # number of fast writes performed
874system.cpu.dcache.cache_copies 0 # number of cache copies performed
875system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits
876system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
877system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits
878system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits
879system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits
880system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits
881system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits
882system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits
883system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
884system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
885system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses
886system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses
887system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses
888system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses
889system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses
890system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses

874system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4732000 # number of ReadReq MSHR miss cycles
875system.cpu.dcache.ReadReq_mshr_miss_latency::total 4732000 # number of ReadReq MSHR miss cycles

891system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles
892system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles

876system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles
877system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles

893system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles
894system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles

878system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10967500 # number of demand (read+write) MSHR miss cycles
879system.cpu.dcache.demand_mshr_miss_latency::total 10967500 # number of demand (read+write) MSHR miss cycles
880system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10967500 # number of overall MSHR miss cycles
881system.cpu.dcache.overall_mshr_miss_latency::total 10967500 # number of overall MSHR miss cycles

895system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles
896system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles
897system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles
898system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles

882system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses
883system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses
884system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
885system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
886system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses
887system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses
888system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses
889system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses

899system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses
900system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses
901system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses
902system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses
903system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses
904system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses
905system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses
906system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses

890system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72800 # average ReadReq mshr miss latency
891system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72800 # average ReadReq mshr miss latency

907system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency
908system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency

892system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency
893system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency

909system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency
910system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency

894system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency
895system.cpu.dcache.demand_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency
896system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74104.729730 # average overall mshr miss latency
897system.cpu.dcache.overall_avg_mshr_miss_latency::total 74104.729730 # average overall mshr miss latency

911system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency
912system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency
913system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency
914system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency