1Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout
2Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr
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3gem5 Simulator System. http://gem5.org
4gem5 is copyrighted software; use the --copyright option for details.
5
| 1gem5 Simulator System. http://gem5.org
2gem5 is copyrighted software; use the --copyright option for details.
3
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6gem5 compiled Jun 21 2014 11:07:38
7gem5 started Jun 21 2014 11:08:19
| 4gem5 compiled Apr 22 2015 08:08:31
5gem5 started Apr 22 2015 08:14:03
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8gem5 executing on phenom
9command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
| 6gem5 executing on phenom
7command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
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| 8
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10Global frequency set at 1000000000000 ticks per second
11info: Entering event queue @ 0. Starting simulation...
12Begining test of difficult SPARC instructions...
13LDSTUB: Passed
14SWAP: Passed
15CAS FAIL: Passed
16CAS WORK: Passed
17CASX FAIL: Passed
18CASX WORK: Passed
19LDTX: Passed
20LDTW: Passed
21STTW: Passed
22Done
| 9Global frequency set at 1000000000000 ticks per second
10info: Entering event queue @ 0. Starting simulation...
11Begining test of difficult SPARC instructions...
12LDSTUB: Passed
13SWAP: Passed
14CAS FAIL: Passed
15CAS WORK: Passed
16CASX FAIL: Passed
17CASX WORK: Passed
18LDTX: Passed
19LDTW: Passed
20STTW: Passed
21Done
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23Exiting @ tick 26706500 because target called exit()
| 22Exiting @ tick 27482500 because target called exit()
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