| config.ini (9276:a5ede748a1d9) | config.ini (9348:44d31345e360) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a |
| 13clock=1 | 13clock=1000 |
| 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= --- 102 unchanged lines hidden (view full) --- 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 | 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= --- 102 unchanged lines hidden (view full) --- 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 |
| 132clock=1 | 132clock=500 |
| 133forward_snoops=true 134hash_delay=1 | 133forward_snoops=true 134hash_delay=1 |
| 135hit_latency=1000 | 135hit_latency=2 |
| 136is_top_level=true 137max_miss_count=0 | 136is_top_level=true 137max_miss_count=0 |
| 138mshrs=10 | 138mshrs=4 |
| 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null | 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null |
| 143response_latency=1000 | 143response_latency=2 |
| 144size=262144 145subblock_size=0 146system=system 147tgts_per_mshr=20 148trace_addr=0 149two_queue=false 150write_buffers=8 151cpu_side=system.cpu.dcache_port --- 266 unchanged lines hidden (view full) --- 418opClass=IprAccess 419opLat=3 420 421[system.cpu.icache] 422type=BaseCache 423addr_ranges=0:18446744073709551615 424assoc=2 425block_size=64 | 144size=262144 145subblock_size=0 146system=system 147tgts_per_mshr=20 148trace_addr=0 149two_queue=false 150write_buffers=8 151cpu_side=system.cpu.dcache_port --- 266 unchanged lines hidden (view full) --- 418opClass=IprAccess 419opLat=3 420 421[system.cpu.icache] 422type=BaseCache 423addr_ranges=0:18446744073709551615 424assoc=2 425block_size=64 |
| 426clock=1 | 426clock=500 |
| 427forward_snoops=true 428hash_delay=1 | 427forward_snoops=true 428hash_delay=1 |
| 429hit_latency=1000 | 429hit_latency=2 |
| 430is_top_level=true 431max_miss_count=0 | 430is_top_level=true 431max_miss_count=0 |
| 432mshrs=10 | 432mshrs=4 |
| 433prefetch_on_access=false 434prefetcher=Null 435prioritizeRequests=false 436repl=Null | 433prefetch_on_access=false 434prefetcher=Null 435prioritizeRequests=false 436repl=Null |
| 437response_latency=1000 | 437response_latency=2 |
| 438size=131072 439subblock_size=0 440system=system 441tgts_per_mshr=20 442trace_addr=0 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port --- 4 unchanged lines hidden (view full) --- 450 451[system.cpu.itb] 452type=SparcTLB 453size=64 454 455[system.cpu.l2cache] 456type=BaseCache 457addr_ranges=0:18446744073709551615 | 438size=131072 439subblock_size=0 440system=system 441tgts_per_mshr=20 442trace_addr=0 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port --- 4 unchanged lines hidden (view full) --- 450 451[system.cpu.itb] 452type=SparcTLB 453size=64 454 455[system.cpu.l2cache] 456type=BaseCache 457addr_ranges=0:18446744073709551615 |
| 458assoc=2 | 458assoc=8 |
| 459block_size=64 | 459block_size=64 |
| 460clock=1 | 460clock=500 |
| 461forward_snoops=true 462hash_delay=1 | 461forward_snoops=true 462hash_delay=1 |
| 463hit_latency=1000 | 463hit_latency=20 |
| 464is_top_level=false 465max_miss_count=0 | 464is_top_level=false 465max_miss_count=0 |
| 466mshrs=10 | 466mshrs=20 |
| 467prefetch_on_access=false 468prefetcher=Null 469prioritizeRequests=false 470repl=Null | 467prefetch_on_access=false 468prefetcher=Null 469prioritizeRequests=false 470repl=Null |
| 471response_latency=1000 | 471response_latency=20 |
| 472size=2097152 473subblock_size=0 474system=system | 472size=2097152 473subblock_size=0 474system=system |
| 475tgts_per_mshr=5 | 475tgts_per_mshr=12 |
| 476trace_addr=0 477two_queue=false 478write_buffers=8 479cpu_side=system.cpu.toL2Bus.master[0] 480mem_side=system.membus.slave[1] 481 482[system.cpu.toL2Bus] 483type=CoherentBus 484block_size=64 | 476trace_addr=0 477two_queue=false 478write_buffers=8 479cpu_side=system.cpu.toL2Bus.master[0] 480mem_side=system.membus.slave[1] 481 482[system.cpu.toL2Bus] 483type=CoherentBus 484block_size=64 |
| 485clock=1000 | 485clock=500 |
| 486header_cycles=1 487use_default_range=false | 486header_cycles=1 487use_default_range=false |
| 488width=8 | 488width=32 |
| 489master=system.cpu.l2cache.cpu_side 490slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 491 492[system.cpu.tracer] 493type=ExeTracer 494 495[system.cpu.workload] 496type=LiveProcess 497cmd=insttest 498cwd= 499egid=100 500env= 501errout=cerr 502euid=100 | 489master=system.cpu.l2cache.cpu_side 490slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 491 492[system.cpu.tracer] 493type=ExeTracer 494 495[system.cpu.workload] 496type=LiveProcess 497cmd=insttest 498cwd= 499egid=100 500env= 501errout=cerr 502euid=100 |
| 503executable=tests/test-progs/insttest/bin/sparc/linux/insttest | 503executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest |
| 504gid=100 505input=cin 506max_stack_size=67108864 507output=cout 508pid=100 509ppid=99 510simpoint=0 511system=system --- 5 unchanged lines hidden (view full) --- 517clock=1000 518header_cycles=1 519use_default_range=false 520width=8 521master=system.physmem.port 522slave=system.system_port system.cpu.l2cache.mem_side 523 524[system.physmem] | 504gid=100 505input=cin 506max_stack_size=67108864 507output=cout 508pid=100 509ppid=99 510simpoint=0 511system=system --- 5 unchanged lines hidden (view full) --- 517clock=1000 518header_cycles=1 519use_default_range=false 520width=8 521master=system.physmem.port 522slave=system.system_port system.cpu.l2cache.mem_side 523 524[system.physmem] |
| 525type=SimpleMemory 526bandwidth=73.000000 527clock=1 | 525type=SimpleDRAM 526addr_mapping=openmap 527banks_per_rank=8 528clock=1000 |
| 528conf_table_reported=false 529in_addr_map=true | 529conf_table_reported=false 530in_addr_map=true |
| 530latency=30000 531latency_var=0 | 531lines_per_rowbuffer=64 532mem_sched_policy=fcfs |
| 532null=false | 533null=false |
| 534page_policy=open |
|
| 533range=0:134217727 | 535range=0:134217727 |
| 536ranks_per_channel=2 537read_buffer_size=32 538tBURST=4000 539tCL=14000 540tRCD=14000 541tREFI=7800000 542tRFC=300000 543tRP=14000 544tWTR=1000 545write_buffer_size=32 546write_thresh_perc=70 |
|
| 534zero=false 535port=system.membus.master[0] 536 | 547zero=false 548port=system.membus.master[0] 549 |