| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 159 unchanged lines hidden (view full) --- 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171useIndirect=true 172 173[system.cpu.dcache] 174type=Cache 175children=tags | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 159 unchanged lines hidden (view full) --- 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171useIndirect=true 172 173[system.cpu.dcache] 174type=Cache 175children=tags |
| 176addr_ranges=0:18446744073709551615 | 176addr_ranges=0:18446744073709551615:0:0:0:0 |
| 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl 180default_p_state=UNDEFINED 181demand_mshr_reserve=1 182eventq_index=0 183hit_latency=2 184is_read_only=false --- 341 unchanged lines hidden (view full) --- 526eventq_index=0 527opClass=IprAccess 528opLat=3 529pipelined=false 530 531[system.cpu.icache] 532type=Cache 533children=tags | 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl 180default_p_state=UNDEFINED 181demand_mshr_reserve=1 182eventq_index=0 183hit_latency=2 184is_read_only=false --- 341 unchanged lines hidden (view full) --- 526eventq_index=0 527opClass=IprAccess 528opLat=3 529pipelined=false 530 531[system.cpu.icache] 532type=Cache 533children=tags |
| 534addr_ranges=0:18446744073709551615 | 534addr_ranges=0:18446744073709551615:0:0:0:0 |
| 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl 538default_p_state=UNDEFINED 539demand_mshr_reserve=1 540eventq_index=0 541hit_latency=2 542is_read_only=true --- 42 unchanged lines hidden (view full) --- 585[system.cpu.itb] 586type=SparcTLB 587eventq_index=0 588size=64 589 590[system.cpu.l2cache] 591type=Cache 592children=tags | 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl 538default_p_state=UNDEFINED 539demand_mshr_reserve=1 540eventq_index=0 541hit_latency=2 542is_read_only=true --- 42 unchanged lines hidden (view full) --- 585[system.cpu.itb] 586type=SparcTLB 587eventq_index=0 588size=64 589 590[system.cpu.l2cache] 591type=Cache 592children=tags |
| 593addr_ranges=0:18446744073709551615 | 593addr_ranges=0:18446744073709551615:0:0:0:0 |
| 594assoc=8 595clk_domain=system.cpu_clk_domain 596clusivity=mostly_incl 597default_p_state=UNDEFINED 598demand_mshr_reserve=1 599eventq_index=0 600hit_latency=20 601is_read_only=false --- 100 unchanged lines hidden (view full) --- 702domains= 703enable=false 704eventq_index=0 705sys_clk_domain=system.clk_domain 706transition_latency=100000000 707 708[system.membus] 709type=CoherentXBar | 594assoc=8 595clk_domain=system.cpu_clk_domain 596clusivity=mostly_incl 597default_p_state=UNDEFINED 598demand_mshr_reserve=1 599eventq_index=0 600hit_latency=20 601is_read_only=false --- 100 unchanged lines hidden (view full) --- 702domains= 703enable=false 704eventq_index=0 705sys_clk_domain=system.clk_domain 706transition_latency=100000000 707 708[system.membus] 709type=CoherentXBar |
| 710children=snoop_filter |
|
| 710clk_domain=system.clk_domain 711default_p_state=UNDEFINED 712eventq_index=0 713forward_latency=4 714frontend_latency=3 715p_state_clk_gate_bins=20 716p_state_clk_gate_max=1000000000000 717p_state_clk_gate_min=1000 718point_of_coherency=true 719power_model=Null 720response_latency=2 | 711clk_domain=system.clk_domain 712default_p_state=UNDEFINED 713eventq_index=0 714forward_latency=4 715frontend_latency=3 716p_state_clk_gate_bins=20 717p_state_clk_gate_max=1000000000000 718p_state_clk_gate_min=1000 719point_of_coherency=true 720power_model=Null 721response_latency=2 |
| 721snoop_filter=Null | 722snoop_filter=system.membus.snoop_filter |
| 722snoop_response_latency=4 723system=system 724use_default_range=false 725width=16 726master=system.physmem.port 727slave=system.system_port system.cpu.l2cache.mem_side 728 | 723snoop_response_latency=4 724system=system 725use_default_range=false 726width=16 727master=system.physmem.port 728slave=system.system_port system.cpu.l2cache.mem_side 729 |
| 730[system.membus.snoop_filter] 731type=SnoopFilter 732eventq_index=0 733lookup_latency=1 734max_capacity=8388608 735system=system 736 |
|
| 729[system.physmem] 730type=DRAMCtrl | 737[system.physmem] 738type=DRAMCtrl |
| 731IDD0=0.075000 | 739IDD0=0.055000 |
| 732IDD02=0.000000 | 740IDD02=0.000000 |
| 733IDD2N=0.050000 | 741IDD2N=0.032000 |
| 734IDD2N2=0.000000 735IDD2P0=0.000000 736IDD2P02=0.000000 | 742IDD2N2=0.000000 743IDD2P0=0.000000 744IDD2P02=0.000000 |
| 737IDD2P1=0.000000 | 745IDD2P1=0.032000 |
| 738IDD2P12=0.000000 | 746IDD2P12=0.000000 |
| 739IDD3N=0.057000 | 747IDD3N=0.038000 |
| 740IDD3N2=0.000000 741IDD3P0=0.000000 742IDD3P02=0.000000 | 748IDD3N2=0.000000 749IDD3P0=0.000000 750IDD3P02=0.000000 |
| 743IDD3P1=0.000000 | 751IDD3P1=0.038000 |
| 744IDD3P12=0.000000 | 752IDD3P12=0.000000 |
| 745IDD4R=0.187000 | 753IDD4R=0.157000 |
| 746IDD4R2=0.000000 | 754IDD4R2=0.000000 |
| 747IDD4W=0.165000 | 755IDD4W=0.125000 |
| 748IDD4W2=0.000000 | 756IDD4W2=0.000000 |
| 749IDD5=0.220000 | 757IDD5=0.235000 |
| 750IDD52=0.000000 | 758IDD52=0.000000 |
| 751IDD6=0.000000 | 759IDD6=0.020000 |
| 752IDD62=0.000000 753VDD=1.500000 754VDD2=0.000000 755activation_limit=4 756addr_mapping=RoRaBaCoCh 757bank_groups_per_rank=0 758banks_per_rank=8 759burst_length=8 760channels=1 761clk_domain=system.clk_domain 762conf_table_reported=true 763default_p_state=UNDEFINED 764device_bus_width=8 765device_rowbuffer_size=1024 766device_size=536870912 767devices_per_rank=8 768dll=true 769eventq_index=0 770in_addr_map=true | 760IDD62=0.000000 761VDD=1.500000 762VDD2=0.000000 763activation_limit=4 764addr_mapping=RoRaBaCoCh 765bank_groups_per_rank=0 766banks_per_rank=8 767burst_length=8 768channels=1 769clk_domain=system.clk_domain 770conf_table_reported=true 771default_p_state=UNDEFINED 772device_bus_width=8 773device_rowbuffer_size=1024 774device_size=536870912 775devices_per_rank=8 776dll=true 777eventq_index=0 778in_addr_map=true |
| 779kvm_map=true |
|
| 771max_accesses_per_row=16 772mem_sched_policy=frfcfs 773min_writes_per_switch=16 774null=false 775p_state_clk_gate_bins=20 776p_state_clk_gate_max=1000000000000 777p_state_clk_gate_min=1000 778page_policy=open_adaptive 779power_model=Null | 780max_accesses_per_row=16 781mem_sched_policy=frfcfs 782min_writes_per_switch=16 783null=false 784p_state_clk_gate_bins=20 785p_state_clk_gate_max=1000000000000 786p_state_clk_gate_min=1000 787page_policy=open_adaptive 788power_model=Null |
| 780range=0:134217727 | 789range=0:134217727:0:0:0:0 |
| 781ranks_per_channel=2 782read_buffer_size=32 783static_backend_latency=10000 784static_frontend_latency=10000 785tBURST=5000 786tCCD_L=0 787tCK=1250 788tCL=13750 --- 5 unchanged lines hidden (view full) --- 794tRP=13750 795tRRD=6000 796tRRD_L=0 797tRTP=7500 798tRTW=2500 799tWR=15000 800tWTR=7500 801tXAW=30000 | 790ranks_per_channel=2 791read_buffer_size=32 792static_backend_latency=10000 793static_frontend_latency=10000 794tBURST=5000 795tCCD_L=0 796tCK=1250 797tCL=13750 --- 5 unchanged lines hidden (view full) --- 803tRP=13750 804tRRD=6000 805tRRD_L=0 806tRTP=7500 807tRTW=2500 808tWR=15000 809tWTR=7500 810tXAW=30000 |
| 802tXP=0 | 811tXP=6000 |
| 803tXPDLL=0 | 812tXPDLL=0 |
| 804tXS=0 | 813tXS=270000 |
| 805tXSDLL=0 806write_buffer_size=64 807write_high_thresh_perc=85 808write_low_thresh_perc=50 809port=system.membus.master[0] 810 811[system.voltage_domain] 812type=VoltageDomain 813eventq_index=0 814voltage=1.000000 815 | 814tXSDLL=0 815write_buffer_size=64 816write_high_thresh_perc=85 817write_low_thresh_perc=50 818port=system.membus.master[0] 819 820[system.voltage_domain] 821type=VoltageDomain 822eventq_index=0 823voltage=1.000000 824 |