Cross Reference: /gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini

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config.ini (9348:44d31345e360)	config.ini (9449:56610ab73040)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775
17mem_mode=atomic	17mem_mode=timing 18mem_ranges=
18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU	19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[0] 31 32[system.cpu] 33type=DerivO3CPU
33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload	34children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8	35BTBEntries=4096 36BTBTagSize=16 37LFSTSize=1024 38LQEntries=32 39LSQCheckLoads=true 40LSQDepCheckShift=4 41RASSize=16 42SQEntries=32 43SSITSize=1024 44activity=0 45backComSize=5 46cachePorts=200 47checker=Null 48choiceCtrBits=2 49choicePredictorSize=8192 50clock=500 51commitToDecodeDelay=1 52commitToFetchDelay=1 53commitToIEWDelay=1 54commitToRenameDelay=1 55commitWidth=8 56cpu_id=0 57decodeToFetchDelay=1 58decodeToRenameDelay=1 59decodeWidth=8
59defer_registration=false
60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts	60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts
	81isa=system.cpu.isa
81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000	82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000
	119switched_out=false
118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 132clock=500 133forward_snoops=true	120system=system 121tracer=system.cpu.tracer 122trapLatency=13 123wbDepth=1 124wbWidth=8 125workload=system.cpu.workload 126dcache_port=system.cpu.dcache.cpu_side 127icache_port=system.cpu.icache.cpu_side 128 129[system.cpu.dcache] 130type=BaseCache 131addr_ranges=0:18446744073709551615 132assoc=2 133block_size=64 134clock=500 135forward_snoops=true
134hash_delay=1
135hit_latency=2 136is_top_level=true 137max_miss_count=0 138mshrs=4 139prefetch_on_access=false 140prefetcher=Null	136hit_latency=2 137is_top_level=true 138max_miss_count=0 139mshrs=4 140prefetch_on_access=false 141prefetcher=Null
141prioritizeRequests=false 142repl=Null
143response_latency=2 144size=262144	142response_latency=2 143size=262144
145subblock_size=0
146system=system 147tgts_per_mshr=20	144system=system 145tgts_per_mshr=20
148trace_addr=0
149two_queue=false 150write_buffers=8 151cpu_side=system.cpu.dcache_port 152mem_side=system.cpu.toL2Bus.slave[1] 153 154[system.cpu.dtb] 155type=SparcTLB 156size=64 157 158[system.cpu.fuPool] 159type=FUPool 160children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 161FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 162 163[system.cpu.fuPool.FUList0] 164type=FUDesc 165children=opList 166count=6 167opList=system.cpu.fuPool.FUList0.opList 168 169[system.cpu.fuPool.FUList0.opList] 170type=OpDesc 171issueLat=1 172opClass=IntAlu 173opLat=1 174 175[system.cpu.fuPool.FUList1] 176type=FUDesc 177children=opList0 opList1 178count=2 179opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 180 181[system.cpu.fuPool.FUList1.opList0] 182type=OpDesc 183issueLat=1 184opClass=IntMult 185opLat=3 186 187[system.cpu.fuPool.FUList1.opList1] 188type=OpDesc 189issueLat=19 190opClass=IntDiv 191opLat=20 192 193[system.cpu.fuPool.FUList2] 194type=FUDesc 195children=opList0 opList1 opList2 196count=4 197opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 198 199[system.cpu.fuPool.FUList2.opList0] 200type=OpDesc 201issueLat=1 202opClass=FloatAdd 203opLat=2 204 205[system.cpu.fuPool.FUList2.opList1] 206type=OpDesc 207issueLat=1 208opClass=FloatCmp 209opLat=2 210 211[system.cpu.fuPool.FUList2.opList2] 212type=OpDesc 213issueLat=1 214opClass=FloatCvt 215opLat=2 216 217[system.cpu.fuPool.FUList3] 218type=FUDesc 219children=opList0 opList1 opList2 220count=2 221opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 222 223[system.cpu.fuPool.FUList3.opList0] 224type=OpDesc 225issueLat=1 226opClass=FloatMult 227opLat=4 228 229[system.cpu.fuPool.FUList3.opList1] 230type=OpDesc 231issueLat=12 232opClass=FloatDiv 233opLat=12 234 235[system.cpu.fuPool.FUList3.opList2] 236type=OpDesc 237issueLat=24 238opClass=FloatSqrt 239opLat=24 240 241[system.cpu.fuPool.FUList4] 242type=FUDesc 243children=opList 244count=0 245opList=system.cpu.fuPool.FUList4.opList 246 247[system.cpu.fuPool.FUList4.opList] 248type=OpDesc 249issueLat=1 250opClass=MemRead 251opLat=1 252 253[system.cpu.fuPool.FUList5] 254type=FUDesc 255children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 256count=4 257opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 258 259[system.cpu.fuPool.FUList5.opList00] 260type=OpDesc 261issueLat=1 262opClass=SimdAdd 263opLat=1 264 265[system.cpu.fuPool.FUList5.opList01] 266type=OpDesc 267issueLat=1 268opClass=SimdAddAcc 269opLat=1 270 271[system.cpu.fuPool.FUList5.opList02] 272type=OpDesc 273issueLat=1 274opClass=SimdAlu 275opLat=1 276 277[system.cpu.fuPool.FUList5.opList03] 278type=OpDesc 279issueLat=1 280opClass=SimdCmp 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList04] 284type=OpDesc 285issueLat=1 286opClass=SimdCvt 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList05] 290type=OpDesc 291issueLat=1 292opClass=SimdMisc 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList06] 296type=OpDesc 297issueLat=1 298opClass=SimdMult 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList07] 302type=OpDesc 303issueLat=1 304opClass=SimdMultAcc 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList08] 308type=OpDesc 309issueLat=1 310opClass=SimdShift 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList09] 314type=OpDesc 315issueLat=1 316opClass=SimdShiftAcc 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList10] 320type=OpDesc 321issueLat=1 322opClass=SimdSqrt 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList11] 326type=OpDesc 327issueLat=1 328opClass=SimdFloatAdd 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList12] 332type=OpDesc 333issueLat=1 334opClass=SimdFloatAlu 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList13] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatCmp 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList14] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatCvt 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList15] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatDiv 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList16] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatMisc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList17] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatMult 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList18] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatMultAcc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList19] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatSqrt 377opLat=1 378 379[system.cpu.fuPool.FUList6] 380type=FUDesc 381children=opList 382count=0 383opList=system.cpu.fuPool.FUList6.opList 384 385[system.cpu.fuPool.FUList6.opList] 386type=OpDesc 387issueLat=1 388opClass=MemWrite 389opLat=1 390 391[system.cpu.fuPool.FUList7] 392type=FUDesc 393children=opList0 opList1 394count=4 395opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 396 397[system.cpu.fuPool.FUList7.opList0] 398type=OpDesc 399issueLat=1 400opClass=MemRead 401opLat=1 402 403[system.cpu.fuPool.FUList7.opList1] 404type=OpDesc 405issueLat=1 406opClass=MemWrite 407opLat=1 408 409[system.cpu.fuPool.FUList8] 410type=FUDesc 411children=opList 412count=1 413opList=system.cpu.fuPool.FUList8.opList 414 415[system.cpu.fuPool.FUList8.opList] 416type=OpDesc 417issueLat=3 418opClass=IprAccess 419opLat=3 420 421[system.cpu.icache] 422type=BaseCache 423addr_ranges=0:18446744073709551615 424assoc=2 425block_size=64 426clock=500 427forward_snoops=true	146two_queue=false 147write_buffers=8 148cpu_side=system.cpu.dcache_port 149mem_side=system.cpu.toL2Bus.slave[1] 150 151[system.cpu.dtb] 152type=SparcTLB 153size=64 154 155[system.cpu.fuPool] 156type=FUPool 157children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 158FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 159 160[system.cpu.fuPool.FUList0] 161type=FUDesc 162children=opList 163count=6 164opList=system.cpu.fuPool.FUList0.opList 165 166[system.cpu.fuPool.FUList0.opList] 167type=OpDesc 168issueLat=1 169opClass=IntAlu 170opLat=1 171 172[system.cpu.fuPool.FUList1] 173type=FUDesc 174children=opList0 opList1 175count=2 176opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 177 178[system.cpu.fuPool.FUList1.opList0] 179type=OpDesc 180issueLat=1 181opClass=IntMult 182opLat=3 183 184[system.cpu.fuPool.FUList1.opList1] 185type=OpDesc 186issueLat=19 187opClass=IntDiv 188opLat=20 189 190[system.cpu.fuPool.FUList2] 191type=FUDesc 192children=opList0 opList1 opList2 193count=4 194opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 195 196[system.cpu.fuPool.FUList2.opList0] 197type=OpDesc 198issueLat=1 199opClass=FloatAdd 200opLat=2 201 202[system.cpu.fuPool.FUList2.opList1] 203type=OpDesc 204issueLat=1 205opClass=FloatCmp 206opLat=2 207 208[system.cpu.fuPool.FUList2.opList2] 209type=OpDesc 210issueLat=1 211opClass=FloatCvt 212opLat=2 213 214[system.cpu.fuPool.FUList3] 215type=FUDesc 216children=opList0 opList1 opList2 217count=2 218opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 219 220[system.cpu.fuPool.FUList3.opList0] 221type=OpDesc 222issueLat=1 223opClass=FloatMult 224opLat=4 225 226[system.cpu.fuPool.FUList3.opList1] 227type=OpDesc 228issueLat=12 229opClass=FloatDiv 230opLat=12 231 232[system.cpu.fuPool.FUList3.opList2] 233type=OpDesc 234issueLat=24 235opClass=FloatSqrt 236opLat=24 237 238[system.cpu.fuPool.FUList4] 239type=FUDesc 240children=opList 241count=0 242opList=system.cpu.fuPool.FUList4.opList 243 244[system.cpu.fuPool.FUList4.opList] 245type=OpDesc 246issueLat=1 247opClass=MemRead 248opLat=1 249 250[system.cpu.fuPool.FUList5] 251type=FUDesc 252children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 253count=4 254opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 255 256[system.cpu.fuPool.FUList5.opList00] 257type=OpDesc 258issueLat=1 259opClass=SimdAdd 260opLat=1 261 262[system.cpu.fuPool.FUList5.opList01] 263type=OpDesc 264issueLat=1 265opClass=SimdAddAcc 266opLat=1 267 268[system.cpu.fuPool.FUList5.opList02] 269type=OpDesc 270issueLat=1 271opClass=SimdAlu 272opLat=1 273 274[system.cpu.fuPool.FUList5.opList03] 275type=OpDesc 276issueLat=1 277opClass=SimdCmp 278opLat=1 279 280[system.cpu.fuPool.FUList5.opList04] 281type=OpDesc 282issueLat=1 283opClass=SimdCvt 284opLat=1 285 286[system.cpu.fuPool.FUList5.opList05] 287type=OpDesc 288issueLat=1 289opClass=SimdMisc 290opLat=1 291 292[system.cpu.fuPool.FUList5.opList06] 293type=OpDesc 294issueLat=1 295opClass=SimdMult 296opLat=1 297 298[system.cpu.fuPool.FUList5.opList07] 299type=OpDesc 300issueLat=1 301opClass=SimdMultAcc 302opLat=1 303 304[system.cpu.fuPool.FUList5.opList08] 305type=OpDesc 306issueLat=1 307opClass=SimdShift 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList09] 311type=OpDesc 312issueLat=1 313opClass=SimdShiftAcc 314opLat=1 315 316[system.cpu.fuPool.FUList5.opList10] 317type=OpDesc 318issueLat=1 319opClass=SimdSqrt 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList11] 323type=OpDesc 324issueLat=1 325opClass=SimdFloatAdd 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList12] 329type=OpDesc 330issueLat=1 331opClass=SimdFloatAlu 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList13] 335type=OpDesc 336issueLat=1 337opClass=SimdFloatCmp 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList14] 341type=OpDesc 342issueLat=1 343opClass=SimdFloatCvt 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList15] 347type=OpDesc 348issueLat=1 349opClass=SimdFloatDiv 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList16] 353type=OpDesc 354issueLat=1 355opClass=SimdFloatMisc 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList17] 359type=OpDesc 360issueLat=1 361opClass=SimdFloatMult 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList18] 365type=OpDesc 366issueLat=1 367opClass=SimdFloatMultAcc 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList19] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatSqrt 374opLat=1 375 376[system.cpu.fuPool.FUList6] 377type=FUDesc 378children=opList 379count=0 380opList=system.cpu.fuPool.FUList6.opList 381 382[system.cpu.fuPool.FUList6.opList] 383type=OpDesc 384issueLat=1 385opClass=MemWrite 386opLat=1 387 388[system.cpu.fuPool.FUList7] 389type=FUDesc 390children=opList0 opList1 391count=4 392opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 393 394[system.cpu.fuPool.FUList7.opList0] 395type=OpDesc 396issueLat=1 397opClass=MemRead 398opLat=1 399 400[system.cpu.fuPool.FUList7.opList1] 401type=OpDesc 402issueLat=1 403opClass=MemWrite 404opLat=1 405 406[system.cpu.fuPool.FUList8] 407type=FUDesc 408children=opList 409count=1 410opList=system.cpu.fuPool.FUList8.opList 411 412[system.cpu.fuPool.FUList8.opList] 413type=OpDesc 414issueLat=3 415opClass=IprAccess 416opLat=3 417 418[system.cpu.icache] 419type=BaseCache 420addr_ranges=0:18446744073709551615 421assoc=2 422block_size=64 423clock=500 424forward_snoops=true
428hash_delay=1
429hit_latency=2 430is_top_level=true 431max_miss_count=0 432mshrs=4 433prefetch_on_access=false 434prefetcher=Null	425hit_latency=2 426is_top_level=true 427max_miss_count=0 428mshrs=4 429prefetch_on_access=false 430prefetcher=Null
435prioritizeRequests=false 436repl=Null
437response_latency=2 438size=131072	431response_latency=2 432size=131072
439subblock_size=0
440system=system 441tgts_per_mshr=20	433system=system 434tgts_per_mshr=20
442trace_addr=0
443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port 446mem_side=system.cpu.toL2Bus.slave[0] 447 448[system.cpu.interrupts] 449type=SparcInterrupts 450	435two_queue=false 436write_buffers=8 437cpu_side=system.cpu.icache_port 438mem_side=system.cpu.toL2Bus.slave[0] 439 440[system.cpu.interrupts] 441type=SparcInterrupts 442
	443[system.cpu.isa] 444type=SparcISA 445
451[system.cpu.itb] 452type=SparcTLB 453size=64 454 455[system.cpu.l2cache] 456type=BaseCache 457addr_ranges=0:18446744073709551615 458assoc=8 459block_size=64 460clock=500 461forward_snoops=true	446[system.cpu.itb] 447type=SparcTLB 448size=64 449 450[system.cpu.l2cache] 451type=BaseCache 452addr_ranges=0:18446744073709551615 453assoc=8 454block_size=64 455clock=500 456forward_snoops=true
462hash_delay=1
463hit_latency=20 464is_top_level=false 465max_miss_count=0 466mshrs=20 467prefetch_on_access=false 468prefetcher=Null	457hit_latency=20 458is_top_level=false 459max_miss_count=0 460mshrs=20 461prefetch_on_access=false 462prefetcher=Null
469prioritizeRequests=false 470repl=Null
471response_latency=20 472size=2097152	463response_latency=20 464size=2097152
473subblock_size=0
474system=system 475tgts_per_mshr=12	465system=system 466tgts_per_mshr=12
476trace_addr=0
477two_queue=false 478write_buffers=8 479cpu_side=system.cpu.toL2Bus.master[0] 480mem_side=system.membus.slave[1] 481 482[system.cpu.toL2Bus] 483type=CoherentBus 484block_size=64 485clock=500 486header_cycles=1 487use_default_range=false 488width=32 489master=system.cpu.l2cache.cpu_side 490slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 491 492[system.cpu.tracer] 493type=ExeTracer 494 495[system.cpu.workload] 496type=LiveProcess 497cmd=insttest 498cwd= 499egid=100 500env= 501errout=cerr 502euid=100	467two_queue=false 468write_buffers=8 469cpu_side=system.cpu.toL2Bus.master[0] 470mem_side=system.membus.slave[1] 471 472[system.cpu.toL2Bus] 473type=CoherentBus 474block_size=64 475clock=500 476header_cycles=1 477use_default_range=false 478width=32 479master=system.cpu.l2cache.cpu_side 480slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 481 482[system.cpu.tracer] 483type=ExeTracer 484 485[system.cpu.workload] 486type=LiveProcess 487cmd=insttest 488cwd= 489egid=100 490env= 491errout=cerr 492euid=100
503executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest	493executable=/gem5/dist/test-progs/insttest/bin/sparc/linux/insttest
504gid=100 505input=cin 506max_stack_size=67108864 507output=cout 508pid=100 509ppid=99 510simpoint=0 511system=system 512uid=100 513 514[system.membus] 515type=CoherentBus 516block_size=64 517clock=1000 518header_cycles=1 519use_default_range=false 520width=8 521master=system.physmem.port 522slave=system.system_port system.cpu.l2cache.mem_side 523 524[system.physmem] 525type=SimpleDRAM 526addr_mapping=openmap 527banks_per_rank=8 528clock=1000 529conf_table_reported=false 530in_addr_map=true 531lines_per_rowbuffer=64 532mem_sched_policy=fcfs 533null=false 534page_policy=open 535range=0:134217727 536ranks_per_channel=2 537read_buffer_size=32 538tBURST=4000 539tCL=14000 540tRCD=14000 541tREFI=7800000 542tRFC=300000 543tRP=14000 544tWTR=1000 545write_buffer_size=32 546write_thresh_perc=70 547zero=false 548port=system.membus.master[0] 549	494gid=100 495input=cin 496max_stack_size=67108864 497output=cout 498pid=100 499ppid=99 500simpoint=0 501system=system 502uid=100 503 504[system.membus] 505type=CoherentBus 506block_size=64 507clock=1000 508header_cycles=1 509use_default_range=false 510width=8 511master=system.physmem.port 512slave=system.system_port system.cpu.l2cache.mem_side 513 514[system.physmem] 515type=SimpleDRAM 516addr_mapping=openmap 517banks_per_rank=8 518clock=1000 519conf_table_reported=false 520in_addr_map=true 521lines_per_rowbuffer=64 522mem_sched_policy=fcfs 523null=false 524page_policy=open 525range=0:134217727 526ranks_per_channel=2 527read_buffer_size=32 528tBURST=4000 529tCL=14000 530tRCD=14000 531tREFI=7800000 532tRFC=300000 533tRP=14000 534tWTR=1000 535write_buffer_size=32 536write_thresh_perc=70 537zero=false 538port=system.membus.master[0] 539