Cross Reference: /gem5/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/simple-timing-ruby/simout

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simout (11731:c473ca7cc650)	simout (12137:d877205ec1bc)
1Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simout 2Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simerr 3gem5 Simulator System. http://gem5.org 4gem5 is copyrighted software; use the --copyright option for details. 5	1Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simout 2Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby/simerr 3gem5 Simulator System. http://gem5.org 4gem5 is copyrighted software; use the --copyright option for details. 5
6gem5 compiled Nov 30 2016 14:33:35 7gem5 started Nov 30 2016 16:18:53 8gem5 executing on zizzer, pid 34103 9command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby	6gem5 compiled Jul 13 2017 17:09:45 7gem5 started Jul 13 2017 17:09:50 8gem5 executing on boldrock, pid 1343 9command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/simple-timing-ruby
10 11Global frequency set at 1000000000 ticks per second	10 11Global frequency set at 1000000000 ticks per second
12info: Entering event queue @ 0. Starting simulation... 13info: Increasing stack size by one page.
14mul: PASS 15mul, overflow: PASS 16mulh: PASS 17mulh, negative: PASS 18mulh, all bits set: PASS 19mulhsu, all bits set: PASS 20mulhsu: PASS 21mulhu: PASS 22mulhu, all bits set: PASS 23div: PASS 24div/0: PASS 25div, overflow: PASS 26divu: PASS 27divu/0: PASS 28divu, "overflow": PASS 29rem: PASS 30rem/0: PASS 31rem, overflow: PASS 32remu: PASS 33remu/0: PASS 34remu, "overflow": PASS 35mulw, truncate: PASS 36mulw, overflow: PASS 37divw, truncate: PASS 38divw/0: PASS 39divw, overflow: PASS 40divuw, truncate: PASS 41divuw/0: PASS 42divuw, "overflow": PASS 43divuw, sign extend: PASS 44remw, truncate: PASS 45remw/0: PASS 46remw, overflow: PASS 47remuw, truncate: PASS 48remuw/0: PASS 49remuw, "overflow": PASS 50remuw, sign extend: PASS	12mul: PASS 13mul, overflow: PASS 14mulh: PASS 15mulh, negative: PASS 16mulh, all bits set: PASS 17mulhsu, all bits set: PASS 18mulhsu: PASS 19mulhu: PASS 20mulhu, all bits set: PASS 21div: PASS 22div/0: PASS 23div, overflow: PASS 24divu: PASS 25divu/0: PASS 26divu, "overflow": PASS 27rem: PASS 28rem/0: PASS 29rem, overflow: PASS 30remu: PASS 31remu/0: PASS 32remu, "overflow": PASS 33mulw, truncate: PASS 34mulw, overflow: PASS 35divw, truncate: PASS 36divw/0: PASS 37divw, overflow: PASS 38divuw, truncate: PASS 39divuw/0: PASS 40divuw, "overflow": PASS 41divuw, sign extend: PASS 42remw, truncate: PASS 43remw/0: PASS 44remw, overflow: PASS 45remuw, truncate: PASS 46remuw/0: PASS 47remuw, "overflow": PASS 48remuw, sign extend: PASS
51Exiting @ tick 1841805 because target called exit()	49Exiting @ tick 1858825 because exiting with last active thread context