| simout (11731:c473ca7cc650) | simout (12137:d877205ec1bc) |
|---|---|
| 1Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing/simout 2Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing/simerr 3gem5 Simulator System. http://gem5.org 4gem5 is copyrighted software; use the --copyright option for details. 5 | 1Redirecting stdout to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing/simout 2Redirecting stderr to build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing/simerr 3gem5 Simulator System. http://gem5.org 4gem5 is copyrighted software; use the --copyright option for details. 5 |
| 6gem5 compiled Nov 30 2016 14:33:35 7gem5 started Nov 30 2016 16:18:44 8gem5 executing on zizzer, pid 34095 9command line: /z/powerjg/gem5-upstream/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/o3-timing | 6gem5 compiled Jul 13 2017 17:09:45 7gem5 started Jul 13 2017 17:11:34 8gem5 executing on boldrock, pid 1866 9command line: /home/ar4jc/gem5/build/RISCV/gem5.opt -d build/RISCV/tests/opt/quick/se/02.insttest/riscv/linux-rv64m/o3-timing --stats-file 'text://stats.txt?desc=False' -re /home/ar4jc/gem5/tests/testing/../run.py quick/se/02.insttest/riscv/linux-rv64m/o3-timing |
| 10 11Global frequency set at 1000000000000 ticks per second | 10 11Global frequency set at 1000000000000 ticks per second |
| 12info: Entering event queue @ 0. Starting simulation... 13info: Increasing stack size by one page. | |
| 14mul: PASS 15mul, overflow: PASS 16mulh: PASS 17mulh, negative: PASS 18mulh, all bits set: PASS 19mulhsu, all bits set: PASS 20mulhsu: PASS 21mulhu: PASS --- 21 unchanged lines hidden (view full) --- 43divuw, sign extend: PASS 44remw, truncate: PASS 45remw/0: PASS 46remw, overflow: PASS 47remuw, truncate: PASS 48remuw/0: PASS 49remuw, "overflow": PASS 50remuw, sign extend: PASS | 12mul: PASS 13mul, overflow: PASS 14mulh: PASS 15mulh, negative: PASS 16mulh, all bits set: PASS 17mulhsu, all bits set: PASS 18mulhsu: PASS 19mulhu: PASS --- 21 unchanged lines hidden (view full) --- 41divuw, sign extend: PASS 42remw, truncate: PASS 43remw/0: PASS 44remw, overflow: PASS 45remuw, truncate: PASS 46remuw/0: PASS 47remuw, "overflow": PASS 48remuw, sign extend: PASS |
| 51Exiting @ tick 66726000 because target called exit() | 49Exiting @ tick 124491500 because exiting with last active thread context |