Cross Reference: /gem5/tests/quick/se/02.insttest/ref/riscv/linux-rv64m/minor-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000165 # Number of seconds simulated
4sim_ticks 165091500 # Number of ticks simulated
5final_tick 165091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 30601 # Simulator instruction rate (inst/s)
8host_op_rate 30601 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 44574860 # Simulator tick rate (ticks/s)
10host_mem_usage 244264 # Number of bytes of host memory used
11host_seconds 3.70 # Real time elapsed on the host

7host_inst_rate 261359 # Simulator instruction rate (inst/s)
8host_op_rate 261351 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 380682439 # Simulator tick rate (ticks/s)
10host_mem_usage 261856 # Number of bytes of host memory used
11host_seconds 0.43 # Real time elapsed on the host

12sim_insts 113337 # Number of instructions simulated
13sim_ops 113337 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 49984 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 16768 # Number of bytes read from this memory
19system.physmem.bytes_read::total 66752 # Number of bytes read from this memory

--- 176 unchanged lines hidden (view full) ---

196system.physmem.bytesPerActivate::256-383 39 18.66% 70.33% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 19 9.09% 79.43% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 9 4.31% 83.73% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 8 3.83% 87.56% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 6 2.87% 90.43% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 3 1.44% 91.87% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 17 8.13% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation

204system.physmem.totQLat 16657750 # Total ticks spent queuing
205system.physmem.totMemAccLat 36214000 # Total ticks spent from burst creation until serviced by the DRAM

204system.physmem.totQLat 16727250 # Total ticks spent queuing
205system.physmem.totMemAccLat 36283500 # Total ticks spent from burst creation until serviced by the DRAM

206system.physmem.totBusLat 5215000 # Total ticks spent in databus transfers

207system.physmem.avgQLat 15971.00 # Average queueing delay per DRAM burst

207system.physmem.avgQLat 16037.63 # Average queueing delay per DRAM burst

208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst

209system.physmem.avgMemAccLat 34721.00 # Average memory access latency per DRAM burst

209system.physmem.avgMemAccLat 34787.63 # Average memory access latency per DRAM burst

210system.physmem.avgRdBW 404.33 # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys 404.33 # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil 3.16 # Data bus utilization in percentage
216system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes

--- 6 unchanged lines hidden (view full) ---

224system.physmem.avgGap 157971.24 # Average gap between requests
225system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined
226system.physmem_0.actEnergy 778260 # Energy for activate commands per rank (pJ)
227system.physmem_0.preEnergy 409860 # Energy for precharge commands per rank (pJ)
228system.physmem_0.readEnergy 3348660 # Energy for read commands per rank (pJ)
229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ)
231system.physmem_0.actBackEnergy 9067560 # Energy for active background per rank (pJ)

232system.physmem_0.preBackEnergy 480480 # Energy for precharge background per rank (pJ)
233system.physmem_0.actPowerDownEnergy 54701760 # Energy for active power-down per rank (pJ)
234system.physmem_0.prePowerDownEnergy 6869760 # Energy for precharge power-down per rank (pJ)

232system.physmem_0.preBackEnergy 480000 # Energy for precharge background per rank (pJ)
233system.physmem_0.actPowerDownEnergy 54713160 # Energy for active power-down per rank (pJ)
234system.physmem_0.prePowerDownEnergy 6860640 # Energy for precharge power-down per rank (pJ)

235system.physmem_0.selfRefreshEnergy 2569980 # Energy for self refresh per rank (pJ)

236system.physmem_0.totalEnergy 91748400 # Total energy per rank (pJ)
237system.physmem_0.averagePower 555.739358 # Core power per rank (mW)

236system.physmem_0.totalEnergy 91750200 # Total energy per rank (pJ)
237system.physmem_0.averagePower 555.750261 # Core power per rank (mW)

238system.physmem_0.totalIdleTime 143461250 # Total Idle time Per DRAM Rank
239system.physmem_0.memoryStateTime::IDLE 642000 # Time in different power states
240system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states
241system.physmem_0.memoryStateTime::SREF 6106000 # Time in different power states

242system.physmem_0.memoryStateTime::PRE_PDN 17892500 # Time in different power states

242system.physmem_0.memoryStateTime::PRE_PDN 17868500 # Time in different power states

243system.physmem_0.memoryStateTime::ACT 14770000 # Time in different power states

244system.physmem_0.memoryStateTime::ACT_PDN 119949000 # Time in different power states

244system.physmem_0.memoryStateTime::ACT_PDN 119973000 # Time in different power states

245system.physmem_1.actEnergy 749700 # Energy for activate commands per rank (pJ)
246system.physmem_1.preEnergy 383295 # Energy for precharge commands per rank (pJ)
247system.physmem_1.readEnergy 4098360 # Energy for read commands per rank (pJ)
248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ)
250system.physmem_1.actBackEnergy 9572580 # Energy for active background per rank (pJ)
251system.physmem_1.preBackEnergy 409440 # Energy for precharge background per rank (pJ)

252system.physmem_1.actPowerDownEnergy 46964580 # Energy for active power-down per rank (pJ)
253system.physmem_1.prePowerDownEnergy 13642080 # Energy for precharge power-down per rank (pJ)

252system.physmem_1.actPowerDownEnergy 46966860 # Energy for active power-down per rank (pJ)
253system.physmem_1.prePowerDownEnergy 13640160 # Energy for precharge power-down per rank (pJ)

254system.physmem_1.selfRefreshEnergy 1635840 # Energy for self refresh per rank (pJ)

255system.physmem_1.totalEnergy 90363315 # Total energy per rank (pJ)
256system.physmem_1.averagePower 547.349607 # Core power per rank (mW)

255system.physmem_1.totalEnergy 90363675 # Total energy per rank (pJ)
256system.physmem_1.averagePower 547.351788 # Core power per rank (mW)

257system.physmem_1.totalIdleTime 142759500 # Total Idle time Per DRAM Rank
258system.physmem_1.memoryStateTime::IDLE 477500 # Time in different power states
259system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states
260system.physmem_1.memoryStateTime::SREF 4514500 # Time in different power states

261system.physmem_1.memoryStateTime::PRE_PDN 35521500 # Time in different power states

261system.physmem_1.memoryStateTime::PRE_PDN 35516500 # Time in different power states

262system.physmem_1.memoryStateTime::ACT 16091750 # Time in different power states

263system.physmem_1.memoryStateTime::ACT_PDN 103014250 # Time in different power states

263system.physmem_1.memoryStateTime::ACT_PDN 103019250 # Time in different power states

264system.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states

265system.cpu.branchPred.lookups 31704 # Number of BP lookups
266system.cpu.branchPred.condPredicted 20239 # Number of conditional branches predicted
267system.cpu.branchPred.condIncorrect 2235 # Number of conditional branches incorrect
268system.cpu.branchPred.BTBLookups 27881 # Number of BTB lookups
269system.cpu.branchPred.BTBHits 15332 # Number of BTB hits

265system.cpu.branchPred.lookups 31695 # Number of BP lookups
266system.cpu.branchPred.condPredicted 20247 # Number of conditional branches predicted
267system.cpu.branchPred.condIncorrect 2223 # Number of conditional branches incorrect
268system.cpu.branchPred.BTBLookups 27548 # Number of BTB lookups
269system.cpu.branchPred.BTBHits 15330 # Number of BTB hits

270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

271system.cpu.branchPred.BTBHitPct 54.990854 # BTB Hit Percentage

271system.cpu.branchPred.BTBHitPct 55.648323 # BTB Hit Percentage

272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.

274system.cpu.branchPred.indirectLookups 5600 # Number of indirect predictor lookups.
275system.cpu.branchPred.indirectHits 3678 # Number of indirect target hits.
276system.cpu.branchPred.indirectMisses 1922 # Number of indirect misses.

274system.cpu.branchPred.indirectLookups 5583 # Number of indirect predictor lookups.
275system.cpu.branchPred.indirectHits 3675 # Number of indirect target hits.
276system.cpu.branchPred.indirectMisses 1908 # Number of indirect misses.

277system.cpu.branchPredindirectMispredicted 1024 # Number of mispredicted indirect branches.
278system.cpu_clk_domain.clock 500 # Clock period in ticks
279system.cpu.dtb.read_hits 0 # DTB read hits
280system.cpu.dtb.read_misses 0 # DTB read misses
281system.cpu.dtb.read_accesses 0 # DTB read accesses
282system.cpu.dtb.write_hits 0 # DTB write hits
283system.cpu.dtb.write_misses 0 # DTB write misses
284system.cpu.dtb.write_accesses 0 # DTB write accesses

--- 11 unchanged lines hidden (view full) ---

296system.cpu.itb.accesses 0 # DTB accesses
297system.cpu.workload.num_syscalls 45 # Number of system calls
298system.cpu.pwrStateResidencyTicks::ON 165091500 # Cumulative time (in ticks) in various power states
299system.cpu.numCycles 330183 # number of cpu cycles simulated
300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
302system.cpu.committedInsts 113337 # Number of instructions committed
303system.cpu.committedOps 113337 # Number of ops (including micro ops) committed

304system.cpu.discardedOps 5814 # Number of ops (including micro ops) which were discarded before commit

304system.cpu.discardedOps 5802 # Number of ops (including micro ops) which were discarded before commit

305system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
306system.cpu.cpi 2.913285 # CPI: cycles per instruction
307system.cpu.ipc 0.343255 # IPC: instructions per cycle
308system.cpu.op_class_0::No_OpClass 45 0.04% 0.04% # Class of committed instruction
309system.cpu.op_class_0::IntAlu 69651 61.45% 61.49% # Class of committed instruction
310system.cpu.op_class_0::IntMult 122 0.11% 61.60% # Class of committed instruction
311system.cpu.op_class_0::IntDiv 26 0.02% 61.63% # Class of committed instruction
312system.cpu.op_class_0::FloatAdd 0 0.00% 61.63% # Class of committed instruction

--- 26 unchanged lines hidden (view full) ---

339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.63% # Class of committed instruction
340system.cpu.op_class_0::MemRead 23780 20.98% 82.61% # Class of committed instruction
341system.cpu.op_class_0::MemWrite 19713 17.39% 100.00% # Class of committed instruction
342system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
343system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
346system.cpu.op_class_0::total 113337 # Class of committed instruction

347system.cpu.tickCycles 171254 # Number of cycles that the object actually ticked
348system.cpu.idleCycles 158929 # Total number of cycles that the object has spent stopped

347system.cpu.tickCycles 171128 # Number of cycles that the object actually ticked
348system.cpu.idleCycles 159055 # Total number of cycles that the object has spent stopped

349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
350system.cpu.dcache.tags.replacements 0 # number of replacements

351system.cpu.dcache.tags.tagsinuse 213.474286 # Cycle average of tags in use
352system.cpu.dcache.tags.total_refs 43868 # Total number of references to valid blocks.

351system.cpu.dcache.tags.tagsinuse 213.474358 # Cycle average of tags in use
352system.cpu.dcache.tags.total_refs 43871 # Total number of references to valid blocks.

353system.cpu.dcache.tags.sampled_refs 263 # Sample count of references to valid blocks.

354system.cpu.dcache.tags.avg_refs 166.798479 # Average number of references to valid blocks.

354system.cpu.dcache.tags.avg_refs 166.809886 # Average number of references to valid blocks.

355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

356system.cpu.dcache.tags.occ_blocks::cpu.data 213.474286 # Average occupied blocks per requestor

356system.cpu.dcache.tags.occ_blocks::cpu.data 213.474358 # Average occupied blocks per requestor

357system.cpu.dcache.tags.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy
358system.cpu.dcache.tags.occ_percent::total 0.052118 # Average percentage of cache occupancy
359system.cpu.dcache.tags.occ_task_id_blocks::1024 263 # Occupied blocks per task id
360system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
361system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
362system.cpu.dcache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id
363system.cpu.dcache.tags.occ_task_id_percent::1024 0.064209 # Percentage of cache occupancy per task id

364system.cpu.dcache.tags.tag_accesses 88905 # Number of tag accesses
365system.cpu.dcache.tags.data_accesses 88905 # Number of data accesses

364system.cpu.dcache.tags.tag_accesses 88911 # Number of tag accesses
365system.cpu.dcache.tags.data_accesses 88911 # Number of data accesses

366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states

367system.cpu.dcache.ReadReq_hits::cpu.data 24540 # number of ReadReq hits
368system.cpu.dcache.ReadReq_hits::total 24540 # number of ReadReq hits

367system.cpu.dcache.ReadReq_hits::cpu.data 24543 # number of ReadReq hits
368system.cpu.dcache.ReadReq_hits::total 24543 # number of ReadReq hits

369system.cpu.dcache.WriteReq_hits::cpu.data 19328 # number of WriteReq hits
370system.cpu.dcache.WriteReq_hits::total 19328 # number of WriteReq hits

371system.cpu.dcache.demand_hits::cpu.data 43868 # number of demand (read+write) hits
372system.cpu.dcache.demand_hits::total 43868 # number of demand (read+write) hits
373system.cpu.dcache.overall_hits::cpu.data 43868 # number of overall hits
374system.cpu.dcache.overall_hits::total 43868 # number of overall hits

371system.cpu.dcache.demand_hits::cpu.data 43871 # number of demand (read+write) hits
372system.cpu.dcache.demand_hits::total 43871 # number of demand (read+write) hits
373system.cpu.dcache.overall_hits::cpu.data 43871 # number of overall hits
374system.cpu.dcache.overall_hits::total 43871 # number of overall hits

375system.cpu.dcache.ReadReq_misses::cpu.data 69 # number of ReadReq misses
376system.cpu.dcache.ReadReq_misses::total 69 # number of ReadReq misses
377system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses
378system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses
379system.cpu.dcache.demand_misses::cpu.data 453 # number of demand (read+write) misses
380system.cpu.dcache.demand_misses::total 453 # number of demand (read+write) misses
381system.cpu.dcache.overall_misses::cpu.data 453 # number of overall misses
382system.cpu.dcache.overall_misses::total 453 # number of overall misses

383system.cpu.dcache.ReadReq_miss_latency::cpu.data 7586500 # number of ReadReq miss cycles
384system.cpu.dcache.ReadReq_miss_latency::total 7586500 # number of ReadReq miss cycles

383system.cpu.dcache.ReadReq_miss_latency::cpu.data 7619000 # number of ReadReq miss cycles
384system.cpu.dcache.ReadReq_miss_latency::total 7619000 # number of ReadReq miss cycles

385system.cpu.dcache.WriteReq_miss_latency::cpu.data 31133500 # number of WriteReq miss cycles
386system.cpu.dcache.WriteReq_miss_latency::total 31133500 # number of WriteReq miss cycles

387system.cpu.dcache.demand_miss_latency::cpu.data 38720000 # number of demand (read+write) miss cycles
388system.cpu.dcache.demand_miss_latency::total 38720000 # number of demand (read+write) miss cycles
389system.cpu.dcache.overall_miss_latency::cpu.data 38720000 # number of overall miss cycles
390system.cpu.dcache.overall_miss_latency::total 38720000 # number of overall miss cycles
391system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses)
392system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses)

387system.cpu.dcache.demand_miss_latency::cpu.data 38752500 # number of demand (read+write) miss cycles
388system.cpu.dcache.demand_miss_latency::total 38752500 # number of demand (read+write) miss cycles
389system.cpu.dcache.overall_miss_latency::cpu.data 38752500 # number of overall miss cycles
390system.cpu.dcache.overall_miss_latency::total 38752500 # number of overall miss cycles
391system.cpu.dcache.ReadReq_accesses::cpu.data 24612 # number of ReadReq accesses(hits+misses)
392system.cpu.dcache.ReadReq_accesses::total 24612 # number of ReadReq accesses(hits+misses)

393system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses)
394system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses)

395system.cpu.dcache.demand_accesses::cpu.data 44321 # number of demand (read+write) accesses
396system.cpu.dcache.demand_accesses::total 44321 # number of demand (read+write) accesses
397system.cpu.dcache.overall_accesses::cpu.data 44321 # number of overall (read+write) accesses
398system.cpu.dcache.overall_accesses::total 44321 # number of overall (read+write) accesses

395system.cpu.dcache.demand_accesses::cpu.data 44324 # number of demand (read+write) accesses
396system.cpu.dcache.demand_accesses::total 44324 # number of demand (read+write) accesses
397system.cpu.dcache.overall_accesses::cpu.data 44324 # number of overall (read+write) accesses
398system.cpu.dcache.overall_accesses::total 44324 # number of overall (read+write) accesses

399system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002804 # miss rate for ReadReq accesses
400system.cpu.dcache.ReadReq_miss_rate::total 0.002804 # miss rate for ReadReq accesses
401system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019481 # miss rate for WriteReq accesses
402system.cpu.dcache.WriteReq_miss_rate::total 0.019481 # miss rate for WriteReq accesses

403system.cpu.dcache.demand_miss_rate::cpu.data 0.010221 # miss rate for demand accesses
404system.cpu.dcache.demand_miss_rate::total 0.010221 # miss rate for demand accesses
405system.cpu.dcache.overall_miss_rate::cpu.data 0.010221 # miss rate for overall accesses
406system.cpu.dcache.overall_miss_rate::total 0.010221 # miss rate for overall accesses
407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 109949.275362 # average ReadReq miss latency
408system.cpu.dcache.ReadReq_avg_miss_latency::total 109949.275362 # average ReadReq miss latency

403system.cpu.dcache.demand_miss_rate::cpu.data 0.010220 # miss rate for demand accesses
404system.cpu.dcache.demand_miss_rate::total 0.010220 # miss rate for demand accesses
405system.cpu.dcache.overall_miss_rate::cpu.data 0.010220 # miss rate for overall accesses
406system.cpu.dcache.overall_miss_rate::total 0.010220 # miss rate for overall accesses
407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 110420.289855 # average ReadReq miss latency
408system.cpu.dcache.ReadReq_avg_miss_latency::total 110420.289855 # average ReadReq miss latency

409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81076.822917 # average WriteReq miss latency
410system.cpu.dcache.WriteReq_avg_miss_latency::total 81076.822917 # average WriteReq miss latency

411system.cpu.dcache.demand_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency
412system.cpu.dcache.demand_avg_miss_latency::total 85474.613687 # average overall miss latency
413system.cpu.dcache.overall_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency
414system.cpu.dcache.overall_avg_miss_latency::total 85474.613687 # average overall miss latency

411system.cpu.dcache.demand_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
412system.cpu.dcache.demand_avg_miss_latency::total 85546.357616 # average overall miss latency
413system.cpu.dcache.overall_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
414system.cpu.dcache.overall_avg_miss_latency::total 85546.357616 # average overall miss latency

415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
421system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits
422system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits

--- 6 unchanged lines hidden (view full) ---

429system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses
430system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses
431system.cpu.dcache.WriteReq_mshr_misses::cpu.data 198 # number of WriteReq MSHR misses
432system.cpu.dcache.WriteReq_mshr_misses::total 198 # number of WriteReq MSHR misses
433system.cpu.dcache.demand_mshr_misses::cpu.data 263 # number of demand (read+write) MSHR misses
434system.cpu.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses
435system.cpu.dcache.overall_mshr_misses::cpu.data 263 # number of overall MSHR misses
436system.cpu.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses

437system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121500 # number of ReadReq MSHR miss cycles
438system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121500 # number of ReadReq MSHR miss cycles

437system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7154000 # number of ReadReq MSHR miss cycles
438system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154000 # number of ReadReq MSHR miss cycles

439system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16117500 # number of WriteReq MSHR miss cycles
440system.cpu.dcache.WriteReq_mshr_miss_latency::total 16117500 # number of WriteReq MSHR miss cycles

441system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23239000 # number of demand (read+write) MSHR miss cycles
442system.cpu.dcache.demand_mshr_miss_latency::total 23239000 # number of demand (read+write) MSHR miss cycles
443system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23239000 # number of overall MSHR miss cycles
444system.cpu.dcache.overall_mshr_miss_latency::total 23239000 # number of overall MSHR miss cycles

441system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23271500 # number of demand (read+write) MSHR miss cycles
442system.cpu.dcache.demand_mshr_miss_latency::total 23271500 # number of demand (read+write) MSHR miss cycles
443system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23271500 # number of overall MSHR miss cycles
444system.cpu.dcache.overall_mshr_miss_latency::total 23271500 # number of overall MSHR miss cycles

445system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002641 # mshr miss rate for ReadReq accesses
446system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002641 # mshr miss rate for ReadReq accesses
447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010045 # mshr miss rate for WriteReq accesses
448system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010045 # mshr miss rate for WriteReq accesses
449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for demand accesses
450system.cpu.dcache.demand_mshr_miss_rate::total 0.005934 # mshr miss rate for demand accesses
451system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for overall accesses
452system.cpu.dcache.overall_mshr_miss_rate::total 0.005934 # mshr miss rate for overall accesses

453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 109561.538462 # average ReadReq mshr miss latency
454system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 109561.538462 # average ReadReq mshr miss latency

453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 110061.538462 # average ReadReq mshr miss latency
454system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 110061.538462 # average ReadReq mshr miss latency

455system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81401.515152 # average WriteReq mshr miss latency
456system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81401.515152 # average WriteReq mshr miss latency

457system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency
458system.cpu.dcache.demand_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency
459system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency
460system.cpu.dcache.overall_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency

457system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency
458system.cpu.dcache.demand_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency
459system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency
460system.cpu.dcache.overall_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency

461system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
462system.cpu.icache.tags.replacements 14 # number of replacements

463system.cpu.icache.tags.tagsinuse 386.834879 # Cycle average of tags in use
464system.cpu.icache.tags.total_refs 49717 # Total number of references to valid blocks.

463system.cpu.icache.tags.tagsinuse 386.835866 # Cycle average of tags in use
464system.cpu.icache.tags.total_refs 49670 # Total number of references to valid blocks.

465system.cpu.icache.tags.sampled_refs 781 # Sample count of references to valid blocks.

466system.cpu.icache.tags.avg_refs 63.658131 # Average number of references to valid blocks.

466system.cpu.icache.tags.avg_refs 63.597951 # Average number of references to valid blocks.

467system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

468system.cpu.icache.tags.occ_blocks::cpu.inst 386.834879 # Average occupied blocks per requestor
469system.cpu.icache.tags.occ_percent::cpu.inst 0.188884 # Average percentage of cache occupancy
470system.cpu.icache.tags.occ_percent::total 0.188884 # Average percentage of cache occupancy

468system.cpu.icache.tags.occ_blocks::cpu.inst 386.835866 # Average occupied blocks per requestor
469system.cpu.icache.tags.occ_percent::cpu.inst 0.188885 # Average percentage of cache occupancy
470system.cpu.icache.tags.occ_percent::total 0.188885 # Average percentage of cache occupancy

471system.cpu.icache.tags.occ_task_id_blocks::1024 767 # Occupied blocks per task id
472system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
473system.cpu.icache.tags.age_task_id_blocks_1024::1 497 # Occupied blocks per task id
474system.cpu.icache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id
475system.cpu.icache.tags.occ_task_id_percent::1024 0.374512 # Percentage of cache occupancy per task id

476system.cpu.icache.tags.tag_accesses 101777 # Number of tag accesses
477system.cpu.icache.tags.data_accesses 101777 # Number of data accesses

476system.cpu.icache.tags.tag_accesses 101683 # Number of tag accesses
477system.cpu.icache.tags.data_accesses 101683 # Number of data accesses

478system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states

479system.cpu.icache.ReadReq_hits::cpu.inst 49717 # number of ReadReq hits
480system.cpu.icache.ReadReq_hits::total 49717 # number of ReadReq hits
481system.cpu.icache.demand_hits::cpu.inst 49717 # number of demand (read+write) hits
482system.cpu.icache.demand_hits::total 49717 # number of demand (read+write) hits
483system.cpu.icache.overall_hits::cpu.inst 49717 # number of overall hits
484system.cpu.icache.overall_hits::total 49717 # number of overall hits

479system.cpu.icache.ReadReq_hits::cpu.inst 49670 # number of ReadReq hits
480system.cpu.icache.ReadReq_hits::total 49670 # number of ReadReq hits
481system.cpu.icache.demand_hits::cpu.inst 49670 # number of demand (read+write) hits
482system.cpu.icache.demand_hits::total 49670 # number of demand (read+write) hits
483system.cpu.icache.overall_hits::cpu.inst 49670 # number of overall hits
484system.cpu.icache.overall_hits::total 49670 # number of overall hits

485system.cpu.icache.ReadReq_misses::cpu.inst 781 # number of ReadReq misses
486system.cpu.icache.ReadReq_misses::total 781 # number of ReadReq misses
487system.cpu.icache.demand_misses::cpu.inst 781 # number of demand (read+write) misses
488system.cpu.icache.demand_misses::total 781 # number of demand (read+write) misses
489system.cpu.icache.overall_misses::cpu.inst 781 # number of overall misses
490system.cpu.icache.overall_misses::total 781 # number of overall misses

491system.cpu.icache.ReadReq_miss_latency::cpu.inst 68473000 # number of ReadReq miss cycles
492system.cpu.icache.ReadReq_miss_latency::total 68473000 # number of ReadReq miss cycles
493system.cpu.icache.demand_miss_latency::cpu.inst 68473000 # number of demand (read+write) miss cycles
494system.cpu.icache.demand_miss_latency::total 68473000 # number of demand (read+write) miss cycles
495system.cpu.icache.overall_miss_latency::cpu.inst 68473000 # number of overall miss cycles
496system.cpu.icache.overall_miss_latency::total 68473000 # number of overall miss cycles
497system.cpu.icache.ReadReq_accesses::cpu.inst 50498 # number of ReadReq accesses(hits+misses)
498system.cpu.icache.ReadReq_accesses::total 50498 # number of ReadReq accesses(hits+misses)
499system.cpu.icache.demand_accesses::cpu.inst 50498 # number of demand (read+write) accesses
500system.cpu.icache.demand_accesses::total 50498 # number of demand (read+write) accesses
501system.cpu.icache.overall_accesses::cpu.inst 50498 # number of overall (read+write) accesses
502system.cpu.icache.overall_accesses::total 50498 # number of overall (read+write) accesses
503system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015466 # miss rate for ReadReq accesses
504system.cpu.icache.ReadReq_miss_rate::total 0.015466 # miss rate for ReadReq accesses
505system.cpu.icache.demand_miss_rate::cpu.inst 0.015466 # miss rate for demand accesses
506system.cpu.icache.demand_miss_rate::total 0.015466 # miss rate for demand accesses
507system.cpu.icache.overall_miss_rate::cpu.inst 0.015466 # miss rate for overall accesses
508system.cpu.icache.overall_miss_rate::total 0.015466 # miss rate for overall accesses
509system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87673.495519 # average ReadReq miss latency
510system.cpu.icache.ReadReq_avg_miss_latency::total 87673.495519 # average ReadReq miss latency
511system.cpu.icache.demand_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency
512system.cpu.icache.demand_avg_miss_latency::total 87673.495519 # average overall miss latency
513system.cpu.icache.overall_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency
514system.cpu.icache.overall_avg_miss_latency::total 87673.495519 # average overall miss latency

491system.cpu.icache.ReadReq_miss_latency::cpu.inst 68509500 # number of ReadReq miss cycles
492system.cpu.icache.ReadReq_miss_latency::total 68509500 # number of ReadReq miss cycles
493system.cpu.icache.demand_miss_latency::cpu.inst 68509500 # number of demand (read+write) miss cycles
494system.cpu.icache.demand_miss_latency::total 68509500 # number of demand (read+write) miss cycles
495system.cpu.icache.overall_miss_latency::cpu.inst 68509500 # number of overall miss cycles
496system.cpu.icache.overall_miss_latency::total 68509500 # number of overall miss cycles
497system.cpu.icache.ReadReq_accesses::cpu.inst 50451 # number of ReadReq accesses(hits+misses)
498system.cpu.icache.ReadReq_accesses::total 50451 # number of ReadReq accesses(hits+misses)
499system.cpu.icache.demand_accesses::cpu.inst 50451 # number of demand (read+write) accesses
500system.cpu.icache.demand_accesses::total 50451 # number of demand (read+write) accesses
501system.cpu.icache.overall_accesses::cpu.inst 50451 # number of overall (read+write) accesses
502system.cpu.icache.overall_accesses::total 50451 # number of overall (read+write) accesses
503system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015480 # miss rate for ReadReq accesses
504system.cpu.icache.ReadReq_miss_rate::total 0.015480 # miss rate for ReadReq accesses
505system.cpu.icache.demand_miss_rate::cpu.inst 0.015480 # miss rate for demand accesses
506system.cpu.icache.demand_miss_rate::total 0.015480 # miss rate for demand accesses
507system.cpu.icache.overall_miss_rate::cpu.inst 0.015480 # miss rate for overall accesses
508system.cpu.icache.overall_miss_rate::total 0.015480 # miss rate for overall accesses
509system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87720.230474 # average ReadReq miss latency
510system.cpu.icache.ReadReq_avg_miss_latency::total 87720.230474 # average ReadReq miss latency
511system.cpu.icache.demand_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency
512system.cpu.icache.demand_avg_miss_latency::total 87720.230474 # average overall miss latency
513system.cpu.icache.overall_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency
514system.cpu.icache.overall_avg_miss_latency::total 87720.230474 # average overall miss latency

515system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
516system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
517system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
518system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
519system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
520system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
521system.cpu.icache.writebacks::writebacks 14 # number of writebacks
522system.cpu.icache.writebacks::total 14 # number of writebacks
523system.cpu.icache.ReadReq_mshr_misses::cpu.inst 781 # number of ReadReq MSHR misses
524system.cpu.icache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses
525system.cpu.icache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses
526system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses
527system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses
528system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses

529system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67692000 # number of ReadReq MSHR miss cycles
530system.cpu.icache.ReadReq_mshr_miss_latency::total 67692000 # number of ReadReq MSHR miss cycles
531system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67692000 # number of demand (read+write) MSHR miss cycles
532system.cpu.icache.demand_mshr_miss_latency::total 67692000 # number of demand (read+write) MSHR miss cycles
533system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67692000 # number of overall MSHR miss cycles
534system.cpu.icache.overall_mshr_miss_latency::total 67692000 # number of overall MSHR miss cycles
535system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for ReadReq accesses
536system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015466 # mshr miss rate for ReadReq accesses
537system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for demand accesses
538system.cpu.icache.demand_mshr_miss_rate::total 0.015466 # mshr miss rate for demand accesses
539system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for overall accesses
540system.cpu.icache.overall_mshr_miss_rate::total 0.015466 # mshr miss rate for overall accesses
541system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86673.495519 # average ReadReq mshr miss latency
542system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86673.495519 # average ReadReq mshr miss latency
543system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency
544system.cpu.icache.demand_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency
545system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency
546system.cpu.icache.overall_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency

529system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67728500 # number of ReadReq MSHR miss cycles
530system.cpu.icache.ReadReq_mshr_miss_latency::total 67728500 # number of ReadReq MSHR miss cycles
531system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67728500 # number of demand (read+write) MSHR miss cycles
532system.cpu.icache.demand_mshr_miss_latency::total 67728500 # number of demand (read+write) MSHR miss cycles
533system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67728500 # number of overall MSHR miss cycles
534system.cpu.icache.overall_mshr_miss_latency::total 67728500 # number of overall MSHR miss cycles
535system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for ReadReq accesses
536system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015480 # mshr miss rate for ReadReq accesses
537system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for demand accesses
538system.cpu.icache.demand_mshr_miss_rate::total 0.015480 # mshr miss rate for demand accesses
539system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for overall accesses
540system.cpu.icache.overall_mshr_miss_rate::total 0.015480 # mshr miss rate for overall accesses
541system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86720.230474 # average ReadReq mshr miss latency
542system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86720.230474 # average ReadReq mshr miss latency
543system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency
544system.cpu.icache.demand_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency
545system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency
546system.cpu.icache.overall_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency

547system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
548system.cpu.l2cache.tags.replacements 0 # number of replacements

549system.cpu.l2cache.tags.tagsinuse 603.610931 # Cycle average of tags in use

549system.cpu.l2cache.tags.tagsinuse 603.611991 # Cycle average of tags in use

550system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
551system.cpu.l2cache.tags.sampled_refs 1043 # Sample count of references to valid blocks.
552system.cpu.l2cache.tags.avg_refs 0.014382 # Average number of references to valid blocks.
553system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

554system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.574887 # Average occupied blocks per requestor
555system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036044 # Average occupied blocks per requestor

554system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.575874 # Average occupied blocks per requestor
555system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036117 # Average occupied blocks per requestor

556system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy
557system.cpu.l2cache.tags.occ_percent::cpu.data 0.006501 # Average percentage of cache occupancy
558system.cpu.l2cache.tags.occ_percent::total 0.018421 # Average percentage of cache occupancy
559system.cpu.l2cache.tags.occ_task_id_blocks::1024 1043 # Occupied blocks per task id
560system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id
561system.cpu.l2cache.tags.age_task_id_blocks_1024::1 556 # Occupied blocks per task id
562system.cpu.l2cache.tags.age_task_id_blocks_1024::2 437 # Occupied blocks per task id
563system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031830 # Percentage of cache occupancy per task id

--- 17 unchanged lines hidden (view full) ---

581system.cpu.l2cache.demand_misses::cpu.inst 781 # number of demand (read+write) misses
582system.cpu.l2cache.demand_misses::cpu.data 262 # number of demand (read+write) misses
583system.cpu.l2cache.demand_misses::total 1043 # number of demand (read+write) misses
584system.cpu.l2cache.overall_misses::cpu.inst 781 # number of overall misses
585system.cpu.l2cache.overall_misses::cpu.data 262 # number of overall misses
586system.cpu.l2cache.overall_misses::total 1043 # number of overall misses
587system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15820000 # number of ReadExReq miss cycles
588system.cpu.l2cache.ReadExReq_miss_latency::total 15820000 # number of ReadExReq miss cycles

589system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66520500 # number of ReadCleanReq miss cycles
590system.cpu.l2cache.ReadCleanReq_miss_latency::total 66520500 # number of ReadCleanReq miss cycles
591system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7011500 # number of ReadSharedReq miss cycles
592system.cpu.l2cache.ReadSharedReq_miss_latency::total 7011500 # number of ReadSharedReq miss cycles
593system.cpu.l2cache.demand_miss_latency::cpu.inst 66520500 # number of demand (read+write) miss cycles
594system.cpu.l2cache.demand_miss_latency::cpu.data 22831500 # number of demand (read+write) miss cycles
595system.cpu.l2cache.demand_miss_latency::total 89352000 # number of demand (read+write) miss cycles
596system.cpu.l2cache.overall_miss_latency::cpu.inst 66520500 # number of overall miss cycles
597system.cpu.l2cache.overall_miss_latency::cpu.data 22831500 # number of overall miss cycles
598system.cpu.l2cache.overall_miss_latency::total 89352000 # number of overall miss cycles

589system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66557000 # number of ReadCleanReq miss cycles
590system.cpu.l2cache.ReadCleanReq_miss_latency::total 66557000 # number of ReadCleanReq miss cycles
591system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7044000 # number of ReadSharedReq miss cycles
592system.cpu.l2cache.ReadSharedReq_miss_latency::total 7044000 # number of ReadSharedReq miss cycles
593system.cpu.l2cache.demand_miss_latency::cpu.inst 66557000 # number of demand (read+write) miss cycles
594system.cpu.l2cache.demand_miss_latency::cpu.data 22864000 # number of demand (read+write) miss cycles
595system.cpu.l2cache.demand_miss_latency::total 89421000 # number of demand (read+write) miss cycles
596system.cpu.l2cache.overall_miss_latency::cpu.inst 66557000 # number of overall miss cycles
597system.cpu.l2cache.overall_miss_latency::cpu.data 22864000 # number of overall miss cycles
598system.cpu.l2cache.overall_miss_latency::total 89421000 # number of overall miss cycles

599system.cpu.l2cache.WritebackClean_accesses::writebacks 14 # number of WritebackClean accesses(hits+misses)
600system.cpu.l2cache.WritebackClean_accesses::total 14 # number of WritebackClean accesses(hits+misses)
601system.cpu.l2cache.ReadExReq_accesses::cpu.data 198 # number of ReadExReq accesses(hits+misses)
602system.cpu.l2cache.ReadExReq_accesses::total 198 # number of ReadExReq accesses(hits+misses)
603system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 781 # number of ReadCleanReq accesses(hits+misses)
604system.cpu.l2cache.ReadCleanReq_accesses::total 781 # number of ReadCleanReq accesses(hits+misses)
605system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses)
606system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses)

--- 12 unchanged lines hidden (view full) ---

619system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
620system.cpu.l2cache.demand_miss_rate::cpu.data 0.996198 # miss rate for demand accesses
621system.cpu.l2cache.demand_miss_rate::total 0.999042 # miss rate for demand accesses
622system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
623system.cpu.l2cache.overall_miss_rate::cpu.data 0.996198 # miss rate for overall accesses
624system.cpu.l2cache.overall_miss_rate::total 0.999042 # miss rate for overall accesses
625system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79898.989899 # average ReadExReq miss latency
626system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79898.989899 # average ReadExReq miss latency

627system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85173.495519 # average ReadCleanReq miss latency
628system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85173.495519 # average ReadCleanReq miss latency
629system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109554.687500 # average ReadSharedReq miss latency
630system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109554.687500 # average ReadSharedReq miss latency
631system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency
632system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency
633system.cpu.l2cache.demand_avg_miss_latency::total 85668.264621 # average overall miss latency
634system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency
635system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency
636system.cpu.l2cache.overall_avg_miss_latency::total 85668.264621 # average overall miss latency

627system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85220.230474 # average ReadCleanReq miss latency
628system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85220.230474 # average ReadCleanReq miss latency
629system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110062.500000 # average ReadSharedReq miss latency
630system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 110062.500000 # average ReadSharedReq miss latency
631system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency
632system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency
633system.cpu.l2cache.demand_avg_miss_latency::total 85734.419942 # average overall miss latency
634system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency
635system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency
636system.cpu.l2cache.overall_avg_miss_latency::total 85734.419942 # average overall miss latency

637system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
638system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
639system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
640system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
641system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
642system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
643system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 198 # number of ReadExReq MSHR misses
644system.cpu.l2cache.ReadExReq_mshr_misses::total 198 # number of ReadExReq MSHR misses

--- 4 unchanged lines hidden (view full) ---

649system.cpu.l2cache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses
650system.cpu.l2cache.demand_mshr_misses::cpu.data 262 # number of demand (read+write) MSHR misses
651system.cpu.l2cache.demand_mshr_misses::total 1043 # number of demand (read+write) MSHR misses
652system.cpu.l2cache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses
653system.cpu.l2cache.overall_mshr_misses::cpu.data 262 # number of overall MSHR misses
654system.cpu.l2cache.overall_mshr_misses::total 1043 # number of overall MSHR misses
655system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13840000 # number of ReadExReq MSHR miss cycles
656system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13840000 # number of ReadExReq MSHR miss cycles

657system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58710500 # number of ReadCleanReq MSHR miss cycles
658system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58710500 # number of ReadCleanReq MSHR miss cycles
659system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6371500 # number of ReadSharedReq MSHR miss cycles
660system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6371500 # number of ReadSharedReq MSHR miss cycles
661system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58710500 # number of demand (read+write) MSHR miss cycles
662system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20211500 # number of demand (read+write) MSHR miss cycles
663system.cpu.l2cache.demand_mshr_miss_latency::total 78922000 # number of demand (read+write) MSHR miss cycles
664system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58710500 # number of overall MSHR miss cycles
665system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20211500 # number of overall MSHR miss cycles
666system.cpu.l2cache.overall_mshr_miss_latency::total 78922000 # number of overall MSHR miss cycles

657system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58747000 # number of ReadCleanReq MSHR miss cycles
658system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58747000 # number of ReadCleanReq MSHR miss cycles
659system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6404000 # number of ReadSharedReq MSHR miss cycles
660system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6404000 # number of ReadSharedReq MSHR miss cycles
661system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58747000 # number of demand (read+write) MSHR miss cycles
662system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20244000 # number of demand (read+write) MSHR miss cycles
663system.cpu.l2cache.demand_mshr_miss_latency::total 78991000 # number of demand (read+write) MSHR miss cycles
664system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58747000 # number of overall MSHR miss cycles
665system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20244000 # number of overall MSHR miss cycles
666system.cpu.l2cache.overall_mshr_miss_latency::total 78991000 # number of overall MSHR miss cycles

667system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
668system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
669system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
670system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
671system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.984615 # mshr miss rate for ReadSharedReq accesses
672system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.984615 # mshr miss rate for ReadSharedReq accesses
673system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
674system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996198 # mshr miss rate for demand accesses
675system.cpu.l2cache.demand_mshr_miss_rate::total 0.999042 # mshr miss rate for demand accesses
676system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
677system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996198 # mshr miss rate for overall accesses
678system.cpu.l2cache.overall_mshr_miss_rate::total 0.999042 # mshr miss rate for overall accesses
679system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69898.989899 # average ReadExReq mshr miss latency
680system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69898.989899 # average ReadExReq mshr miss latency

681system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75173.495519 # average ReadCleanReq mshr miss latency
682system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75173.495519 # average ReadCleanReq mshr miss latency
683system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99554.687500 # average ReadSharedReq mshr miss latency
684system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99554.687500 # average ReadSharedReq mshr miss latency
685system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency
686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency
687system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency
688system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency
689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency
690system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency

681system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75220.230474 # average ReadCleanReq mshr miss latency
682system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75220.230474 # average ReadCleanReq mshr miss latency
683system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 100062.500000 # average ReadSharedReq mshr miss latency
684system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 100062.500000 # average ReadSharedReq mshr miss latency
685system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
687system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
688system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
690system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency

691system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter.
692system.cpu.toL2Bus.snoop_filter.hit_single_requests 15 # Number of requests hitting in the snoop filter with a single holder of the requested data.
693system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
694system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
695system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
696system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
697system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states
698system.cpu.toL2Bus.trans_dist::ReadResp 846 # Transaction distribution

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748system.membus.snoop_fanout::stdev 0 # Request fanout histogram
749system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
750system.membus.snoop_fanout::0 1043 100.00% 100.00% # Request fanout histogram
751system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
752system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
753system.membus.snoop_fanout::min_value 0 # Request fanout histogram
754system.membus.snoop_fanout::max_value 0 # Request fanout histogram
755system.membus.snoop_fanout::total 1043 # Request fanout histogram

756system.membus.reqLayer0.occupancy 1170500 # Layer occupancy (ticks)

756system.membus.reqLayer0.occupancy 1170000 # Layer occupancy (ticks)

757system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)

758system.membus.respLayer1.occupancy 5536250 # Layer occupancy (ticks)

758system.membus.respLayer1.occupancy 5535750 # Layer occupancy (ticks)