7,11c7,11
< host_inst_rate 30601 # Simulator instruction rate (inst/s)
< host_op_rate 30601 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 44574860 # Simulator tick rate (ticks/s)
< host_mem_usage 244264 # Number of bytes of host memory used
< host_seconds 3.70 # Real time elapsed on the host
---
> host_inst_rate 261359 # Simulator instruction rate (inst/s)
> host_op_rate 261351 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 380682439 # Simulator tick rate (ticks/s)
> host_mem_usage 261856 # Number of bytes of host memory used
> host_seconds 0.43 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 16657750 # Total ticks spent queuing
< system.physmem.totMemAccLat 36214000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 16727250 # Total ticks spent queuing
> system.physmem.totMemAccLat 36283500 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 15971.00 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16037.63 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 34721.00 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 34787.63 # Average memory access latency per DRAM burst
232,234c232,234
< system.physmem_0.preBackEnergy 480480 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 54701760 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 6869760 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.preBackEnergy 480000 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 54713160 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 6860640 # Energy for precharge power-down per rank (pJ)
236,237c236,237
< system.physmem_0.totalEnergy 91748400 # Total energy per rank (pJ)
< system.physmem_0.averagePower 555.739358 # Core power per rank (mW)
---
> system.physmem_0.totalEnergy 91750200 # Total energy per rank (pJ)
> system.physmem_0.averagePower 555.750261 # Core power per rank (mW)
242c242
< system.physmem_0.memoryStateTime::PRE_PDN 17892500 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 17868500 # Time in different power states
244c244
< system.physmem_0.memoryStateTime::ACT_PDN 119949000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT_PDN 119973000 # Time in different power states
252,253c252,253
< system.physmem_1.actPowerDownEnergy 46964580 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 13642080 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 46966860 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 13640160 # Energy for precharge power-down per rank (pJ)
255,256c255,256
< system.physmem_1.totalEnergy 90363315 # Total energy per rank (pJ)
< system.physmem_1.averagePower 547.349607 # Core power per rank (mW)
---
> system.physmem_1.totalEnergy 90363675 # Total energy per rank (pJ)
> system.physmem_1.averagePower 547.351788 # Core power per rank (mW)
261c261
< system.physmem_1.memoryStateTime::PRE_PDN 35521500 # Time in different power states
---
> system.physmem_1.memoryStateTime::PRE_PDN 35516500 # Time in different power states
263c263
< system.physmem_1.memoryStateTime::ACT_PDN 103014250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT_PDN 103019250 # Time in different power states
265,269c265,269
< system.cpu.branchPred.lookups 31704 # Number of BP lookups
< system.cpu.branchPred.condPredicted 20239 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2235 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 27881 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 15332 # Number of BTB hits
---
> system.cpu.branchPred.lookups 31695 # Number of BP lookups
> system.cpu.branchPred.condPredicted 20247 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2223 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 27548 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 15330 # Number of BTB hits
271c271
< system.cpu.branchPred.BTBHitPct 54.990854 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 55.648323 # BTB Hit Percentage
274,276c274,276
< system.cpu.branchPred.indirectLookups 5600 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 3678 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 1922 # Number of indirect misses.
---
> system.cpu.branchPred.indirectLookups 5583 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 3675 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 1908 # Number of indirect misses.
304c304
< system.cpu.discardedOps 5814 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 5802 # Number of ops (including micro ops) which were discarded before commit
347,348c347,348
< system.cpu.tickCycles 171254 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 158929 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 171128 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 159055 # Total number of cycles that the object has spent stopped
351,352c351,352
< system.cpu.dcache.tags.tagsinuse 213.474286 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 43868 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 213.474358 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 43871 # Total number of references to valid blocks.
354c354
< system.cpu.dcache.tags.avg_refs 166.798479 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 166.809886 # Average number of references to valid blocks.
356c356
< system.cpu.dcache.tags.occ_blocks::cpu.data 213.474286 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 213.474358 # Average occupied blocks per requestor
364,365c364,365
< system.cpu.dcache.tags.tag_accesses 88905 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 88905 # Number of data accesses
---
> system.cpu.dcache.tags.tag_accesses 88911 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 88911 # Number of data accesses
367,368c367,368
< system.cpu.dcache.ReadReq_hits::cpu.data 24540 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 24540 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 24543 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 24543 # number of ReadReq hits
371,374c371,374
< system.cpu.dcache.demand_hits::cpu.data 43868 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 43868 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 43868 # number of overall hits
< system.cpu.dcache.overall_hits::total 43868 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 43871 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 43871 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 43871 # number of overall hits
> system.cpu.dcache.overall_hits::total 43871 # number of overall hits
383,384c383,384
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7586500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7586500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7619000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7619000 # number of ReadReq miss cycles
387,392c387,392
< system.cpu.dcache.demand_miss_latency::cpu.data 38720000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 38720000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 38720000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 38720000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 38752500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 38752500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 38752500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 38752500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24612 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24612 # number of ReadReq accesses(hits+misses)
395,398c395,398
< system.cpu.dcache.demand_accesses::cpu.data 44321 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 44321 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 44321 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 44321 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 44324 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 44324 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 44324 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 44324 # number of overall (read+write) accesses
403,408c403,408
< system.cpu.dcache.demand_miss_rate::cpu.data 0.010221 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.010221 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.010221 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.010221 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 109949.275362 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 109949.275362 # average ReadReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.010220 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.010220 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.010220 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.010220 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 110420.289855 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 110420.289855 # average ReadReq miss latency
411,414c411,414
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 85474.613687 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 85474.613687 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 85546.357616 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 85546.357616 # average overall miss latency
437,438c437,438
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7154000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154000 # number of ReadReq MSHR miss cycles
441,444c441,444
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23239000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23239000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23239000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23239000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23271500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23271500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23271500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23271500 # number of overall MSHR miss cycles
453,454c453,454
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 109561.538462 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 109561.538462 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 110061.538462 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 110061.538462 # average ReadReq mshr miss latency
457,460c457,460
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency
463,464c463,464
< system.cpu.icache.tags.tagsinuse 386.834879 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 49717 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 386.835866 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 49670 # Total number of references to valid blocks.
466c466
< system.cpu.icache.tags.avg_refs 63.658131 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 63.597951 # Average number of references to valid blocks.
468,470c468,470
< system.cpu.icache.tags.occ_blocks::cpu.inst 386.834879 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.188884 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.188884 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 386.835866 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.188885 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.188885 # Average percentage of cache occupancy
476,477c476,477
< system.cpu.icache.tags.tag_accesses 101777 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 101777 # Number of data accesses
---
> system.cpu.icache.tags.tag_accesses 101683 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 101683 # Number of data accesses
479,484c479,484
< system.cpu.icache.ReadReq_hits::cpu.inst 49717 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 49717 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 49717 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 49717 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 49717 # number of overall hits
< system.cpu.icache.overall_hits::total 49717 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 49670 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 49670 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 49670 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 49670 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 49670 # number of overall hits
> system.cpu.icache.overall_hits::total 49670 # number of overall hits
491,514c491,514
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 68473000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 68473000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 68473000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 68473000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 68473000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 68473000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 50498 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 50498 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 50498 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 50498 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 50498 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 50498 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015466 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.015466 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.015466 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.015466 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.015466 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.015466 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87673.495519 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 87673.495519 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 87673.495519 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 87673.495519 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 68509500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 68509500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 68509500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 68509500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 68509500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 68509500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 50451 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 50451 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 50451 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 50451 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 50451 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 50451 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015480 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.015480 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.015480 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.015480 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.015480 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.015480 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87720.230474 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 87720.230474 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 87720.230474 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 87720.230474 # average overall miss latency
529,546c529,546
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67692000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 67692000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67692000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 67692000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67692000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 67692000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015466 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.015466 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.015466 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86673.495519 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86673.495519 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67728500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 67728500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67728500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 67728500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67728500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 67728500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015480 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.015480 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.015480 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86720.230474 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86720.230474 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency
549c549
< system.cpu.l2cache.tags.tagsinuse 603.610931 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 603.611991 # Cycle average of tags in use
554,555c554,555
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.574887 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036044 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.575874 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036117 # Average occupied blocks per requestor
589,598c589,598
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66520500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 66520500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7011500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7011500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 66520500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 22831500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 89352000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 66520500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 22831500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 89352000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66557000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 66557000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7044000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7044000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 66557000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 22864000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 89421000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 66557000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 22864000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 89421000 # number of overall miss cycles
627,636c627,636
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85173.495519 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85173.495519 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109554.687500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109554.687500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 85668.264621 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 85668.264621 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85220.230474 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85220.230474 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110062.500000 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 110062.500000 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 85734.419942 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 85734.419942 # average overall miss latency
657,666c657,666
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58710500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58710500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6371500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6371500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58710500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20211500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 78922000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58710500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20211500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 78922000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58747000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58747000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6404000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6404000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58747000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20244000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 78991000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58747000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20244000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 78991000 # number of overall MSHR miss cycles
681,690c681,690
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75173.495519 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75173.495519 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99554.687500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99554.687500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75220.230474 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75220.230474 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 100062.500000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 100062.500000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
756c756
< system.membus.reqLayer0.occupancy 1170500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1170000 # Layer occupancy (ticks)
758c758
< system.membus.respLayer1.occupancy 5536250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 5535750 # Layer occupancy (ticks)
< host_inst_rate 30601 # Simulator instruction rate (inst/s)
< host_op_rate 30601 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 44574860 # Simulator tick rate (ticks/s)
< host_mem_usage 244264 # Number of bytes of host memory used
< host_seconds 3.70 # Real time elapsed on the host
---
> host_inst_rate 261359 # Simulator instruction rate (inst/s)
> host_op_rate 261351 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 380682439 # Simulator tick rate (ticks/s)
> host_mem_usage 261856 # Number of bytes of host memory used
> host_seconds 0.43 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 16657750 # Total ticks spent queuing
< system.physmem.totMemAccLat 36214000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 16727250 # Total ticks spent queuing
> system.physmem.totMemAccLat 36283500 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 15971.00 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16037.63 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 34721.00 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 34787.63 # Average memory access latency per DRAM burst
232,234c232,234
< system.physmem_0.preBackEnergy 480480 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 54701760 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 6869760 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.preBackEnergy 480000 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 54713160 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 6860640 # Energy for precharge power-down per rank (pJ)
236,237c236,237
< system.physmem_0.totalEnergy 91748400 # Total energy per rank (pJ)
< system.physmem_0.averagePower 555.739358 # Core power per rank (mW)
---
> system.physmem_0.totalEnergy 91750200 # Total energy per rank (pJ)
> system.physmem_0.averagePower 555.750261 # Core power per rank (mW)
242c242
< system.physmem_0.memoryStateTime::PRE_PDN 17892500 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 17868500 # Time in different power states
244c244
< system.physmem_0.memoryStateTime::ACT_PDN 119949000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT_PDN 119973000 # Time in different power states
252,253c252,253
< system.physmem_1.actPowerDownEnergy 46964580 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 13642080 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 46966860 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 13640160 # Energy for precharge power-down per rank (pJ)
255,256c255,256
< system.physmem_1.totalEnergy 90363315 # Total energy per rank (pJ)
< system.physmem_1.averagePower 547.349607 # Core power per rank (mW)
---
> system.physmem_1.totalEnergy 90363675 # Total energy per rank (pJ)
> system.physmem_1.averagePower 547.351788 # Core power per rank (mW)
261c261
< system.physmem_1.memoryStateTime::PRE_PDN 35521500 # Time in different power states
---
> system.physmem_1.memoryStateTime::PRE_PDN 35516500 # Time in different power states
263c263
< system.physmem_1.memoryStateTime::ACT_PDN 103014250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT_PDN 103019250 # Time in different power states
265,269c265,269
< system.cpu.branchPred.lookups 31704 # Number of BP lookups
< system.cpu.branchPred.condPredicted 20239 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 2235 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 27881 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 15332 # Number of BTB hits
---
> system.cpu.branchPred.lookups 31695 # Number of BP lookups
> system.cpu.branchPred.condPredicted 20247 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 2223 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 27548 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 15330 # Number of BTB hits
271c271
< system.cpu.branchPred.BTBHitPct 54.990854 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 55.648323 # BTB Hit Percentage
274,276c274,276
< system.cpu.branchPred.indirectLookups 5600 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 3678 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 1922 # Number of indirect misses.
---
> system.cpu.branchPred.indirectLookups 5583 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 3675 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 1908 # Number of indirect misses.
304c304
< system.cpu.discardedOps 5814 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 5802 # Number of ops (including micro ops) which were discarded before commit
347,348c347,348
< system.cpu.tickCycles 171254 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 158929 # Total number of cycles that the object has spent stopped
---
> system.cpu.tickCycles 171128 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 159055 # Total number of cycles that the object has spent stopped
351,352c351,352
< system.cpu.dcache.tags.tagsinuse 213.474286 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 43868 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 213.474358 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 43871 # Total number of references to valid blocks.
354c354
< system.cpu.dcache.tags.avg_refs 166.798479 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 166.809886 # Average number of references to valid blocks.
356c356
< system.cpu.dcache.tags.occ_blocks::cpu.data 213.474286 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 213.474358 # Average occupied blocks per requestor
364,365c364,365
< system.cpu.dcache.tags.tag_accesses 88905 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 88905 # Number of data accesses
---
> system.cpu.dcache.tags.tag_accesses 88911 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 88911 # Number of data accesses
367,368c367,368
< system.cpu.dcache.ReadReq_hits::cpu.data 24540 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 24540 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 24543 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 24543 # number of ReadReq hits
371,374c371,374
< system.cpu.dcache.demand_hits::cpu.data 43868 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 43868 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 43868 # number of overall hits
< system.cpu.dcache.overall_hits::total 43868 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 43871 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 43871 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 43871 # number of overall hits
> system.cpu.dcache.overall_hits::total 43871 # number of overall hits
383,384c383,384
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 7586500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 7586500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 7619000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 7619000 # number of ReadReq miss cycles
387,392c387,392
< system.cpu.dcache.demand_miss_latency::cpu.data 38720000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 38720000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 38720000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 38720000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 24609 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 24609 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 38752500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 38752500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 38752500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 38752500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 24612 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 24612 # number of ReadReq accesses(hits+misses)
395,398c395,398
< system.cpu.dcache.demand_accesses::cpu.data 44321 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 44321 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 44321 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 44321 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 44324 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 44324 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 44324 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 44324 # number of overall (read+write) accesses
403,408c403,408
< system.cpu.dcache.demand_miss_rate::cpu.data 0.010221 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.010221 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.010221 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.010221 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 109949.275362 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 109949.275362 # average ReadReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.010220 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.010220 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.010220 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.010220 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 110420.289855 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 110420.289855 # average ReadReq miss latency
411,414c411,414
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 85474.613687 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 85474.613687 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 85474.613687 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 85546.357616 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 85546.357616 # average overall miss latency
437,438c437,438
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7154000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154000 # number of ReadReq MSHR miss cycles
441,444c441,444
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23239000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23239000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23239000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23239000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23271500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23271500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23271500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23271500 # number of overall MSHR miss cycles
453,454c453,454
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 109561.538462 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 109561.538462 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 110061.538462 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 110061.538462 # average ReadReq mshr miss latency
457,460c457,460
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88361.216730 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 88361.216730 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency
463,464c463,464
< system.cpu.icache.tags.tagsinuse 386.834879 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 49717 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 386.835866 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 49670 # Total number of references to valid blocks.
466c466
< system.cpu.icache.tags.avg_refs 63.658131 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 63.597951 # Average number of references to valid blocks.
468,470c468,470
< system.cpu.icache.tags.occ_blocks::cpu.inst 386.834879 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.188884 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.188884 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 386.835866 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.188885 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.188885 # Average percentage of cache occupancy
476,477c476,477
< system.cpu.icache.tags.tag_accesses 101777 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 101777 # Number of data accesses
---
> system.cpu.icache.tags.tag_accesses 101683 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 101683 # Number of data accesses
479,484c479,484
< system.cpu.icache.ReadReq_hits::cpu.inst 49717 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 49717 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 49717 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 49717 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 49717 # number of overall hits
< system.cpu.icache.overall_hits::total 49717 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 49670 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 49670 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 49670 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 49670 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 49670 # number of overall hits
> system.cpu.icache.overall_hits::total 49670 # number of overall hits
491,514c491,514
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 68473000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 68473000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 68473000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 68473000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 68473000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 68473000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 50498 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 50498 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 50498 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 50498 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 50498 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 50498 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015466 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.015466 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.015466 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.015466 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.015466 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.015466 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87673.495519 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 87673.495519 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 87673.495519 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 87673.495519 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 87673.495519 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 68509500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 68509500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 68509500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 68509500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 68509500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 68509500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 50451 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 50451 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 50451 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 50451 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 50451 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 50451 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015480 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.015480 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.015480 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.015480 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.015480 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.015480 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87720.230474 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 87720.230474 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 87720.230474 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 87720.230474 # average overall miss latency
529,546c529,546
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67692000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 67692000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67692000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 67692000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67692000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 67692000 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015466 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.015466 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015466 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.015466 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86673.495519 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86673.495519 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86673.495519 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 86673.495519 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67728500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 67728500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67728500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 67728500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67728500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 67728500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015480 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.015480 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.015480 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86720.230474 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86720.230474 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency
549c549
< system.cpu.l2cache.tags.tagsinuse 603.610931 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 603.611991 # Cycle average of tags in use
554,555c554,555
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.574887 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036044 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.575874 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036117 # Average occupied blocks per requestor
589,598c589,598
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66520500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 66520500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7011500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7011500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 66520500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 22831500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 89352000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 66520500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 22831500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 89352000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66557000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 66557000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7044000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7044000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 66557000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 22864000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 89421000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 66557000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 22864000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 89421000 # number of overall miss cycles
627,636c627,636
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85173.495519 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85173.495519 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 109554.687500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 109554.687500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 85668.264621 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85173.495519 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87143.129771 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 85668.264621 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85220.230474 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85220.230474 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110062.500000 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 110062.500000 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 85734.419942 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 85734.419942 # average overall miss latency
657,666c657,666
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58710500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58710500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6371500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6371500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58710500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20211500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 78922000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58710500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20211500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 78922000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58747000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58747000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6404000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6404000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58747000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20244000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 78991000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58747000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20244000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 78991000 # number of overall MSHR miss cycles
681,690c681,690
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75173.495519 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75173.495519 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99554.687500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99554.687500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75173.495519 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77143.129771 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75668.264621 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75220.230474 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75220.230474 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 100062.500000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 100062.500000 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency
756c756
< system.membus.reqLayer0.occupancy 1170500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1170000 # Layer occupancy (ticks)
758c758
< system.membus.respLayer1.occupancy 5536250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 5535750 # Layer occupancy (ticks)