3sim_seconds 0.000165 # Number of seconds simulated 4sim_ticks 165091500 # Number of ticks simulated 5final_tick 165091500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 261359 # Simulator instruction rate (inst/s) 8host_op_rate 261351 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 380682439 # Simulator tick rate (ticks/s) 10host_mem_usage 261856 # Number of bytes of host memory used 11host_seconds 0.43 # Real time elapsed on the host 12sim_insts 113337 # Number of instructions simulated 13sim_ops 113337 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 49984 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 16768 # Number of bytes read from this memory 19system.physmem.bytes_read::total 66752 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 49984 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 49984 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 781 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 262 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 1043 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 302765436 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 101567918 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 404333355 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 302765436 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 302765436 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 302765436 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 101567918 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 404333355 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 1043 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 1043 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 66752 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 66752 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 93 # Per bank write bursts 46system.physmem.perBankRdBursts::1 5 # Per bank write bursts 47system.physmem.perBankRdBursts::2 17 # Per bank write bursts 48system.physmem.perBankRdBursts::3 108 # Per bank write bursts 49system.physmem.perBankRdBursts::4 59 # Per bank write bursts 50system.physmem.perBankRdBursts::5 95 # Per bank write bursts 51system.physmem.perBankRdBursts::6 66 # Per bank write bursts 52system.physmem.perBankRdBursts::7 26 # Per bank write bursts 53system.physmem.perBankRdBursts::8 58 # Per bank write bursts 54system.physmem.perBankRdBursts::9 78 # Per bank write bursts 55system.physmem.perBankRdBursts::10 82 # Per bank write bursts 56system.physmem.perBankRdBursts::11 51 # Per bank write bursts 57system.physmem.perBankRdBursts::12 133 # Per bank write bursts 58system.physmem.perBankRdBursts::13 67 # Per bank write bursts 59system.physmem.perBankRdBursts::14 98 # Per bank write bursts 60system.physmem.perBankRdBursts::15 7 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 164764000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 1043 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 988 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 51 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 4 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 209 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 312.956938 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 206.620752 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 291.549711 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 58 27.75% 27.75% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 50 23.92% 51.67% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 39 18.66% 70.33% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 19 9.09% 79.43% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 9 4.31% 83.73% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 8 3.83% 87.56% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 6 2.87% 90.43% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 1.44% 91.87% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 17 8.13% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation 204system.physmem.totQLat 16727250 # Total ticks spent queuing 205system.physmem.totMemAccLat 36283500 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 5215000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 16037.63 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 34787.63 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 404.33 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 404.33 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 3.16 # Data bus utilization in percentage 216system.physmem.busUtilRead 3.16 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 829 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 79.48 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 157971.24 # Average gap between requests 225system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 778260 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 409860 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 3348660 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 13522080.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 9067560 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 480000 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 54713160 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 6860640 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 2569980 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 91750200 # Total energy per rank (pJ) 237system.physmem_0.averagePower 555.750261 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 143461250 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 642000 # Time in different power states 240system.physmem_0.memoryStateTime::REF 5732000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 6106000 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 17868500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 14770000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 119973000 # Time in different power states 245system.physmem_1.actEnergy 749700 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 383295 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 4098360 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 12907440.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 9572580 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 409440 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 46966860 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 13640160 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 1635840 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 90363675 # Total energy per rank (pJ) 256system.physmem_1.averagePower 547.351788 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 142759500 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 477500 # Time in different power states 259system.physmem_1.memoryStateTime::REF 5472000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 4514500 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 35516500 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 16091750 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 103019250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 31695 # Number of BP lookups 266system.cpu.branchPred.condPredicted 20247 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 2223 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 27548 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 15330 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 55.648323 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 5583 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 3675 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 1908 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 1024 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.write_accesses 0 # DTB write accesses 285system.cpu.dtb.hits 0 # DTB hits 286system.cpu.dtb.misses 0 # DTB misses 287system.cpu.dtb.accesses 0 # DTB accesses 288system.cpu.itb.read_hits 0 # DTB read hits 289system.cpu.itb.read_misses 0 # DTB read misses 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.numSyscalls 45 # Number of system calls 298system.cpu.pwrStateResidencyTicks::ON 165091500 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 330183 # number of cpu cycles simulated 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.committedInsts 113337 # Number of instructions committed 303system.cpu.committedOps 113337 # Number of ops (including micro ops) committed 304system.cpu.discardedOps 5802 # Number of ops (including micro ops) which were discarded before commit 305system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 306system.cpu.cpi 2.913285 # CPI: cycles per instruction 307system.cpu.ipc 0.343255 # IPC: instructions per cycle 308system.cpu.op_class_0::No_OpClass 45 0.04% 0.04% # Class of committed instruction 309system.cpu.op_class_0::IntAlu 69651 61.45% 61.49% # Class of committed instruction 310system.cpu.op_class_0::IntMult 122 0.11% 61.60% # Class of committed instruction 311system.cpu.op_class_0::IntDiv 26 0.02% 61.63% # Class of committed instruction 312system.cpu.op_class_0::FloatAdd 0 0.00% 61.63% # Class of committed instruction 313system.cpu.op_class_0::FloatCmp 0 0.00% 61.63% # Class of committed instruction 314system.cpu.op_class_0::FloatCvt 0 0.00% 61.63% # Class of committed instruction 315system.cpu.op_class_0::FloatMult 0 0.00% 61.63% # Class of committed instruction 316system.cpu.op_class_0::FloatMultAcc 0 0.00% 61.63% # Class of committed instruction 317system.cpu.op_class_0::FloatDiv 0 0.00% 61.63% # Class of committed instruction 318system.cpu.op_class_0::FloatMisc 0 0.00% 61.63% # Class of committed instruction 319system.cpu.op_class_0::FloatSqrt 0 0.00% 61.63% # Class of committed instruction 320system.cpu.op_class_0::SimdAdd 0 0.00% 61.63% # Class of committed instruction 321system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.63% # Class of committed instruction 322system.cpu.op_class_0::SimdAlu 0 0.00% 61.63% # Class of committed instruction 323system.cpu.op_class_0::SimdCmp 0 0.00% 61.63% # Class of committed instruction 324system.cpu.op_class_0::SimdCvt 0 0.00% 61.63% # Class of committed instruction 325system.cpu.op_class_0::SimdMisc 0 0.00% 61.63% # Class of committed instruction 326system.cpu.op_class_0::SimdMult 0 0.00% 61.63% # Class of committed instruction 327system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.63% # Class of committed instruction 328system.cpu.op_class_0::SimdShift 0 0.00% 61.63% # Class of committed instruction 329system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.63% # Class of committed instruction 330system.cpu.op_class_0::SimdSqrt 0 0.00% 61.63% # Class of committed instruction 331system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.63% # Class of committed instruction 332system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.63% # Class of committed instruction 333system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.63% # Class of committed instruction 334system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.63% # Class of committed instruction 335system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.63% # Class of committed instruction 336system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.63% # Class of committed instruction 337system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.63% # Class of committed instruction 338system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.63% # Class of committed instruction 339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.63% # Class of committed instruction 340system.cpu.op_class_0::MemRead 23780 20.98% 82.61% # Class of committed instruction 341system.cpu.op_class_0::MemWrite 19713 17.39% 100.00% # Class of committed instruction 342system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 343system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 113337 # Class of committed instruction 347system.cpu.tickCycles 171128 # Number of cycles that the object actually ticked 348system.cpu.idleCycles 159055 # Total number of cycles that the object has spent stopped 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states 350system.cpu.dcache.tags.replacements 0 # number of replacements 351system.cpu.dcache.tags.tagsinuse 213.474358 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 43871 # Total number of references to valid blocks. 353system.cpu.dcache.tags.sampled_refs 263 # Sample count of references to valid blocks. 354system.cpu.dcache.tags.avg_refs 166.809886 # Average number of references to valid blocks. 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 356system.cpu.dcache.tags.occ_blocks::cpu.data 213.474358 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.052118 # Average percentage of cache occupancy 359system.cpu.dcache.tags.occ_task_id_blocks::1024 263 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 362system.cpu.dcache.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id 363system.cpu.dcache.tags.occ_task_id_percent::1024 0.064209 # Percentage of cache occupancy per task id 364system.cpu.dcache.tags.tag_accesses 88911 # Number of tag accesses 365system.cpu.dcache.tags.data_accesses 88911 # Number of data accesses 366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states 367system.cpu.dcache.ReadReq_hits::cpu.data 24543 # number of ReadReq hits 368system.cpu.dcache.ReadReq_hits::total 24543 # number of ReadReq hits 369system.cpu.dcache.WriteReq_hits::cpu.data 19328 # number of WriteReq hits 370system.cpu.dcache.WriteReq_hits::total 19328 # number of WriteReq hits 371system.cpu.dcache.demand_hits::cpu.data 43871 # number of demand (read+write) hits 372system.cpu.dcache.demand_hits::total 43871 # number of demand (read+write) hits 373system.cpu.dcache.overall_hits::cpu.data 43871 # number of overall hits 374system.cpu.dcache.overall_hits::total 43871 # number of overall hits 375system.cpu.dcache.ReadReq_misses::cpu.data 69 # number of ReadReq misses 376system.cpu.dcache.ReadReq_misses::total 69 # number of ReadReq misses 377system.cpu.dcache.WriteReq_misses::cpu.data 384 # number of WriteReq misses 378system.cpu.dcache.WriteReq_misses::total 384 # number of WriteReq misses 379system.cpu.dcache.demand_misses::cpu.data 453 # number of demand (read+write) misses 380system.cpu.dcache.demand_misses::total 453 # number of demand (read+write) misses 381system.cpu.dcache.overall_misses::cpu.data 453 # number of overall misses 382system.cpu.dcache.overall_misses::total 453 # number of overall misses 383system.cpu.dcache.ReadReq_miss_latency::cpu.data 7619000 # number of ReadReq miss cycles 384system.cpu.dcache.ReadReq_miss_latency::total 7619000 # number of ReadReq miss cycles 385system.cpu.dcache.WriteReq_miss_latency::cpu.data 31133500 # number of WriteReq miss cycles 386system.cpu.dcache.WriteReq_miss_latency::total 31133500 # number of WriteReq miss cycles 387system.cpu.dcache.demand_miss_latency::cpu.data 38752500 # number of demand (read+write) miss cycles 388system.cpu.dcache.demand_miss_latency::total 38752500 # number of demand (read+write) miss cycles 389system.cpu.dcache.overall_miss_latency::cpu.data 38752500 # number of overall miss cycles 390system.cpu.dcache.overall_miss_latency::total 38752500 # number of overall miss cycles 391system.cpu.dcache.ReadReq_accesses::cpu.data 24612 # number of ReadReq accesses(hits+misses) 392system.cpu.dcache.ReadReq_accesses::total 24612 # number of ReadReq accesses(hits+misses) 393system.cpu.dcache.WriteReq_accesses::cpu.data 19712 # number of WriteReq accesses(hits+misses) 394system.cpu.dcache.WriteReq_accesses::total 19712 # number of WriteReq accesses(hits+misses) 395system.cpu.dcache.demand_accesses::cpu.data 44324 # number of demand (read+write) accesses 396system.cpu.dcache.demand_accesses::total 44324 # number of demand (read+write) accesses 397system.cpu.dcache.overall_accesses::cpu.data 44324 # number of overall (read+write) accesses 398system.cpu.dcache.overall_accesses::total 44324 # number of overall (read+write) accesses 399system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002804 # miss rate for ReadReq accesses 400system.cpu.dcache.ReadReq_miss_rate::total 0.002804 # miss rate for ReadReq accesses 401system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019481 # miss rate for WriteReq accesses 402system.cpu.dcache.WriteReq_miss_rate::total 0.019481 # miss rate for WriteReq accesses 403system.cpu.dcache.demand_miss_rate::cpu.data 0.010220 # miss rate for demand accesses 404system.cpu.dcache.demand_miss_rate::total 0.010220 # miss rate for demand accesses 405system.cpu.dcache.overall_miss_rate::cpu.data 0.010220 # miss rate for overall accesses 406system.cpu.dcache.overall_miss_rate::total 0.010220 # miss rate for overall accesses 407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 110420.289855 # average ReadReq miss latency 408system.cpu.dcache.ReadReq_avg_miss_latency::total 110420.289855 # average ReadReq miss latency 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81076.822917 # average WriteReq miss latency 410system.cpu.dcache.WriteReq_avg_miss_latency::total 81076.822917 # average WriteReq miss latency 411system.cpu.dcache.demand_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency 412system.cpu.dcache.demand_avg_miss_latency::total 85546.357616 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::cpu.data 85546.357616 # average overall miss latency 414system.cpu.dcache.overall_avg_miss_latency::total 85546.357616 # average overall miss latency 415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 422system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 423system.cpu.dcache.WriteReq_mshr_hits::cpu.data 186 # number of WriteReq MSHR hits 424system.cpu.dcache.WriteReq_mshr_hits::total 186 # number of WriteReq MSHR hits 425system.cpu.dcache.demand_mshr_hits::cpu.data 190 # number of demand (read+write) MSHR hits 426system.cpu.dcache.demand_mshr_hits::total 190 # number of demand (read+write) MSHR hits 427system.cpu.dcache.overall_mshr_hits::cpu.data 190 # number of overall MSHR hits 428system.cpu.dcache.overall_mshr_hits::total 190 # number of overall MSHR hits 429system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses 430system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses 431system.cpu.dcache.WriteReq_mshr_misses::cpu.data 198 # number of WriteReq MSHR misses 432system.cpu.dcache.WriteReq_mshr_misses::total 198 # number of WriteReq MSHR misses 433system.cpu.dcache.demand_mshr_misses::cpu.data 263 # number of demand (read+write) MSHR misses 434system.cpu.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses 435system.cpu.dcache.overall_mshr_misses::cpu.data 263 # number of overall MSHR misses 436system.cpu.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses 437system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7154000 # number of ReadReq MSHR miss cycles 438system.cpu.dcache.ReadReq_mshr_miss_latency::total 7154000 # number of ReadReq MSHR miss cycles 439system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16117500 # number of WriteReq MSHR miss cycles 440system.cpu.dcache.WriteReq_mshr_miss_latency::total 16117500 # number of WriteReq MSHR miss cycles 441system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23271500 # number of demand (read+write) MSHR miss cycles 442system.cpu.dcache.demand_mshr_miss_latency::total 23271500 # number of demand (read+write) MSHR miss cycles 443system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23271500 # number of overall MSHR miss cycles 444system.cpu.dcache.overall_mshr_miss_latency::total 23271500 # number of overall MSHR miss cycles 445system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002641 # mshr miss rate for ReadReq accesses 446system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002641 # mshr miss rate for ReadReq accesses 447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010045 # mshr miss rate for WriteReq accesses 448system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010045 # mshr miss rate for WriteReq accesses 449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for demand accesses 450system.cpu.dcache.demand_mshr_miss_rate::total 0.005934 # mshr miss rate for demand accesses 451system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005934 # mshr miss rate for overall accesses 452system.cpu.dcache.overall_mshr_miss_rate::total 0.005934 # mshr miss rate for overall accesses 453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 110061.538462 # average ReadReq mshr miss latency 454system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 110061.538462 # average ReadReq mshr miss latency 455system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81401.515152 # average WriteReq mshr miss latency 456system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81401.515152 # average WriteReq mshr miss latency 457system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency 458system.cpu.dcache.demand_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency 459system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88484.790875 # average overall mshr miss latency 460system.cpu.dcache.overall_avg_mshr_miss_latency::total 88484.790875 # average overall mshr miss latency 461system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states 462system.cpu.icache.tags.replacements 14 # number of replacements 463system.cpu.icache.tags.tagsinuse 386.835866 # Cycle average of tags in use 464system.cpu.icache.tags.total_refs 49670 # Total number of references to valid blocks. 465system.cpu.icache.tags.sampled_refs 781 # Sample count of references to valid blocks. 466system.cpu.icache.tags.avg_refs 63.597951 # Average number of references to valid blocks. 467system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 468system.cpu.icache.tags.occ_blocks::cpu.inst 386.835866 # Average occupied blocks per requestor 469system.cpu.icache.tags.occ_percent::cpu.inst 0.188885 # Average percentage of cache occupancy 470system.cpu.icache.tags.occ_percent::total 0.188885 # Average percentage of cache occupancy 471system.cpu.icache.tags.occ_task_id_blocks::1024 767 # Occupied blocks per task id 472system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 473system.cpu.icache.tags.age_task_id_blocks_1024::1 497 # Occupied blocks per task id 474system.cpu.icache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id 475system.cpu.icache.tags.occ_task_id_percent::1024 0.374512 # Percentage of cache occupancy per task id 476system.cpu.icache.tags.tag_accesses 101683 # Number of tag accesses 477system.cpu.icache.tags.data_accesses 101683 # Number of data accesses 478system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states 479system.cpu.icache.ReadReq_hits::cpu.inst 49670 # number of ReadReq hits 480system.cpu.icache.ReadReq_hits::total 49670 # number of ReadReq hits 481system.cpu.icache.demand_hits::cpu.inst 49670 # number of demand (read+write) hits 482system.cpu.icache.demand_hits::total 49670 # number of demand (read+write) hits 483system.cpu.icache.overall_hits::cpu.inst 49670 # number of overall hits 484system.cpu.icache.overall_hits::total 49670 # number of overall hits 485system.cpu.icache.ReadReq_misses::cpu.inst 781 # number of ReadReq misses 486system.cpu.icache.ReadReq_misses::total 781 # number of ReadReq misses 487system.cpu.icache.demand_misses::cpu.inst 781 # number of demand (read+write) misses 488system.cpu.icache.demand_misses::total 781 # number of demand (read+write) misses 489system.cpu.icache.overall_misses::cpu.inst 781 # number of overall misses 490system.cpu.icache.overall_misses::total 781 # number of overall misses 491system.cpu.icache.ReadReq_miss_latency::cpu.inst 68509500 # number of ReadReq miss cycles 492system.cpu.icache.ReadReq_miss_latency::total 68509500 # number of ReadReq miss cycles 493system.cpu.icache.demand_miss_latency::cpu.inst 68509500 # number of demand (read+write) miss cycles 494system.cpu.icache.demand_miss_latency::total 68509500 # number of demand (read+write) miss cycles 495system.cpu.icache.overall_miss_latency::cpu.inst 68509500 # number of overall miss cycles 496system.cpu.icache.overall_miss_latency::total 68509500 # number of overall miss cycles 497system.cpu.icache.ReadReq_accesses::cpu.inst 50451 # number of ReadReq accesses(hits+misses) 498system.cpu.icache.ReadReq_accesses::total 50451 # number of ReadReq accesses(hits+misses) 499system.cpu.icache.demand_accesses::cpu.inst 50451 # number of demand (read+write) accesses 500system.cpu.icache.demand_accesses::total 50451 # number of demand (read+write) accesses 501system.cpu.icache.overall_accesses::cpu.inst 50451 # number of overall (read+write) accesses 502system.cpu.icache.overall_accesses::total 50451 # number of overall (read+write) accesses 503system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015480 # miss rate for ReadReq accesses 504system.cpu.icache.ReadReq_miss_rate::total 0.015480 # miss rate for ReadReq accesses 505system.cpu.icache.demand_miss_rate::cpu.inst 0.015480 # miss rate for demand accesses 506system.cpu.icache.demand_miss_rate::total 0.015480 # miss rate for demand accesses 507system.cpu.icache.overall_miss_rate::cpu.inst 0.015480 # miss rate for overall accesses 508system.cpu.icache.overall_miss_rate::total 0.015480 # miss rate for overall accesses 509system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 87720.230474 # average ReadReq miss latency 510system.cpu.icache.ReadReq_avg_miss_latency::total 87720.230474 # average ReadReq miss latency 511system.cpu.icache.demand_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency 512system.cpu.icache.demand_avg_miss_latency::total 87720.230474 # average overall miss latency 513system.cpu.icache.overall_avg_miss_latency::cpu.inst 87720.230474 # average overall miss latency 514system.cpu.icache.overall_avg_miss_latency::total 87720.230474 # average overall miss latency 515system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 516system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 517system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 518system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 519system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 520system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 521system.cpu.icache.writebacks::writebacks 14 # number of writebacks 522system.cpu.icache.writebacks::total 14 # number of writebacks 523system.cpu.icache.ReadReq_mshr_misses::cpu.inst 781 # number of ReadReq MSHR misses 524system.cpu.icache.ReadReq_mshr_misses::total 781 # number of ReadReq MSHR misses 525system.cpu.icache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses 526system.cpu.icache.demand_mshr_misses::total 781 # number of demand (read+write) MSHR misses 527system.cpu.icache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses 528system.cpu.icache.overall_mshr_misses::total 781 # number of overall MSHR misses 529system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 67728500 # number of ReadReq MSHR miss cycles 530system.cpu.icache.ReadReq_mshr_miss_latency::total 67728500 # number of ReadReq MSHR miss cycles 531system.cpu.icache.demand_mshr_miss_latency::cpu.inst 67728500 # number of demand (read+write) MSHR miss cycles 532system.cpu.icache.demand_mshr_miss_latency::total 67728500 # number of demand (read+write) MSHR miss cycles 533system.cpu.icache.overall_mshr_miss_latency::cpu.inst 67728500 # number of overall MSHR miss cycles 534system.cpu.icache.overall_mshr_miss_latency::total 67728500 # number of overall MSHR miss cycles 535system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for ReadReq accesses 536system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015480 # mshr miss rate for ReadReq accesses 537system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for demand accesses 538system.cpu.icache.demand_mshr_miss_rate::total 0.015480 # mshr miss rate for demand accesses 539system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015480 # mshr miss rate for overall accesses 540system.cpu.icache.overall_mshr_miss_rate::total 0.015480 # mshr miss rate for overall accesses 541system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86720.230474 # average ReadReq mshr miss latency 542system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86720.230474 # average ReadReq mshr miss latency 543system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency 544system.cpu.icache.demand_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency 545system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86720.230474 # average overall mshr miss latency 546system.cpu.icache.overall_avg_mshr_miss_latency::total 86720.230474 # average overall mshr miss latency 547system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states 548system.cpu.l2cache.tags.replacements 0 # number of replacements 549system.cpu.l2cache.tags.tagsinuse 603.611991 # Cycle average of tags in use 550system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. 551system.cpu.l2cache.tags.sampled_refs 1043 # Sample count of references to valid blocks. 552system.cpu.l2cache.tags.avg_refs 0.014382 # Average number of references to valid blocks. 553system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 554system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.575874 # Average occupied blocks per requestor 555system.cpu.l2cache.tags.occ_blocks::cpu.data 213.036117 # Average occupied blocks per requestor 556system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy 557system.cpu.l2cache.tags.occ_percent::cpu.data 0.006501 # Average percentage of cache occupancy 558system.cpu.l2cache.tags.occ_percent::total 0.018421 # Average percentage of cache occupancy 559system.cpu.l2cache.tags.occ_task_id_blocks::1024 1043 # Occupied blocks per task id 560system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 561system.cpu.l2cache.tags.age_task_id_blocks_1024::1 556 # Occupied blocks per task id 562system.cpu.l2cache.tags.age_task_id_blocks_1024::2 437 # Occupied blocks per task id 563system.cpu.l2cache.tags.occ_task_id_percent::1024 0.031830 # Percentage of cache occupancy per task id 564system.cpu.l2cache.tags.tag_accesses 9507 # Number of tag accesses 565system.cpu.l2cache.tags.data_accesses 9507 # Number of data accesses 566system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states 567system.cpu.l2cache.WritebackClean_hits::writebacks 14 # number of WritebackClean hits 568system.cpu.l2cache.WritebackClean_hits::total 14 # number of WritebackClean hits 569system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 570system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 571system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 572system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 573system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 574system.cpu.l2cache.overall_hits::total 1 # number of overall hits 575system.cpu.l2cache.ReadExReq_misses::cpu.data 198 # number of ReadExReq misses 576system.cpu.l2cache.ReadExReq_misses::total 198 # number of ReadExReq misses 577system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 781 # number of ReadCleanReq misses 578system.cpu.l2cache.ReadCleanReq_misses::total 781 # number of ReadCleanReq misses 579system.cpu.l2cache.ReadSharedReq_misses::cpu.data 64 # number of ReadSharedReq misses 580system.cpu.l2cache.ReadSharedReq_misses::total 64 # number of ReadSharedReq misses 581system.cpu.l2cache.demand_misses::cpu.inst 781 # number of demand (read+write) misses 582system.cpu.l2cache.demand_misses::cpu.data 262 # number of demand (read+write) misses 583system.cpu.l2cache.demand_misses::total 1043 # number of demand (read+write) misses 584system.cpu.l2cache.overall_misses::cpu.inst 781 # number of overall misses 585system.cpu.l2cache.overall_misses::cpu.data 262 # number of overall misses 586system.cpu.l2cache.overall_misses::total 1043 # number of overall misses 587system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15820000 # number of ReadExReq miss cycles 588system.cpu.l2cache.ReadExReq_miss_latency::total 15820000 # number of ReadExReq miss cycles 589system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 66557000 # number of ReadCleanReq miss cycles 590system.cpu.l2cache.ReadCleanReq_miss_latency::total 66557000 # number of ReadCleanReq miss cycles 591system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7044000 # number of ReadSharedReq miss cycles 592system.cpu.l2cache.ReadSharedReq_miss_latency::total 7044000 # number of ReadSharedReq miss cycles 593system.cpu.l2cache.demand_miss_latency::cpu.inst 66557000 # number of demand (read+write) miss cycles 594system.cpu.l2cache.demand_miss_latency::cpu.data 22864000 # number of demand (read+write) miss cycles 595system.cpu.l2cache.demand_miss_latency::total 89421000 # number of demand (read+write) miss cycles 596system.cpu.l2cache.overall_miss_latency::cpu.inst 66557000 # number of overall miss cycles 597system.cpu.l2cache.overall_miss_latency::cpu.data 22864000 # number of overall miss cycles 598system.cpu.l2cache.overall_miss_latency::total 89421000 # number of overall miss cycles 599system.cpu.l2cache.WritebackClean_accesses::writebacks 14 # number of WritebackClean accesses(hits+misses) 600system.cpu.l2cache.WritebackClean_accesses::total 14 # number of WritebackClean accesses(hits+misses) 601system.cpu.l2cache.ReadExReq_accesses::cpu.data 198 # number of ReadExReq accesses(hits+misses) 602system.cpu.l2cache.ReadExReq_accesses::total 198 # number of ReadExReq accesses(hits+misses) 603system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 781 # number of ReadCleanReq accesses(hits+misses) 604system.cpu.l2cache.ReadCleanReq_accesses::total 781 # number of ReadCleanReq accesses(hits+misses) 605system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 65 # number of ReadSharedReq accesses(hits+misses) 606system.cpu.l2cache.ReadSharedReq_accesses::total 65 # number of ReadSharedReq accesses(hits+misses) 607system.cpu.l2cache.demand_accesses::cpu.inst 781 # number of demand (read+write) accesses 608system.cpu.l2cache.demand_accesses::cpu.data 263 # number of demand (read+write) accesses 609system.cpu.l2cache.demand_accesses::total 1044 # number of demand (read+write) accesses 610system.cpu.l2cache.overall_accesses::cpu.inst 781 # number of overall (read+write) accesses 611system.cpu.l2cache.overall_accesses::cpu.data 263 # number of overall (read+write) accesses 612system.cpu.l2cache.overall_accesses::total 1044 # number of overall (read+write) accesses 613system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 614system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 615system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses 616system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses 617system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.984615 # miss rate for ReadSharedReq accesses 618system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.984615 # miss rate for ReadSharedReq accesses 619system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 620system.cpu.l2cache.demand_miss_rate::cpu.data 0.996198 # miss rate for demand accesses 621system.cpu.l2cache.demand_miss_rate::total 0.999042 # miss rate for demand accesses 622system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 623system.cpu.l2cache.overall_miss_rate::cpu.data 0.996198 # miss rate for overall accesses 624system.cpu.l2cache.overall_miss_rate::total 0.999042 # miss rate for overall accesses 625system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79898.989899 # average ReadExReq miss latency 626system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79898.989899 # average ReadExReq miss latency 627system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85220.230474 # average ReadCleanReq miss latency 628system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85220.230474 # average ReadCleanReq miss latency 629system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 110062.500000 # average ReadSharedReq miss latency 630system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 110062.500000 # average ReadSharedReq miss latency 631system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency 632system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency 633system.cpu.l2cache.demand_avg_miss_latency::total 85734.419942 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85220.230474 # average overall miss latency 635system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87267.175573 # average overall miss latency 636system.cpu.l2cache.overall_avg_miss_latency::total 85734.419942 # average overall miss latency 637system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 640system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 641system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 642system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 198 # number of ReadExReq MSHR misses 644system.cpu.l2cache.ReadExReq_mshr_misses::total 198 # number of ReadExReq MSHR misses 645system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 781 # number of ReadCleanReq MSHR misses 646system.cpu.l2cache.ReadCleanReq_mshr_misses::total 781 # number of ReadCleanReq MSHR misses 647system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 64 # number of ReadSharedReq MSHR misses 648system.cpu.l2cache.ReadSharedReq_mshr_misses::total 64 # number of ReadSharedReq MSHR misses 649system.cpu.l2cache.demand_mshr_misses::cpu.inst 781 # number of demand (read+write) MSHR misses 650system.cpu.l2cache.demand_mshr_misses::cpu.data 262 # number of demand (read+write) MSHR misses 651system.cpu.l2cache.demand_mshr_misses::total 1043 # number of demand (read+write) MSHR misses 652system.cpu.l2cache.overall_mshr_misses::cpu.inst 781 # number of overall MSHR misses 653system.cpu.l2cache.overall_mshr_misses::cpu.data 262 # number of overall MSHR misses 654system.cpu.l2cache.overall_mshr_misses::total 1043 # number of overall MSHR misses 655system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13840000 # number of ReadExReq MSHR miss cycles 656system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13840000 # number of ReadExReq MSHR miss cycles 657system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 58747000 # number of ReadCleanReq MSHR miss cycles 658system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 58747000 # number of ReadCleanReq MSHR miss cycles 659system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6404000 # number of ReadSharedReq MSHR miss cycles 660system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6404000 # number of ReadSharedReq MSHR miss cycles 661system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58747000 # number of demand (read+write) MSHR miss cycles 662system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20244000 # number of demand (read+write) MSHR miss cycles 663system.cpu.l2cache.demand_mshr_miss_latency::total 78991000 # number of demand (read+write) MSHR miss cycles 664system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58747000 # number of overall MSHR miss cycles 665system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20244000 # number of overall MSHR miss cycles 666system.cpu.l2cache.overall_mshr_miss_latency::total 78991000 # number of overall MSHR miss cycles 667system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 668system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 669system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 670system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 671system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.984615 # mshr miss rate for ReadSharedReq accesses 672system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.984615 # mshr miss rate for ReadSharedReq accesses 673system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 674system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996198 # mshr miss rate for demand accesses 675system.cpu.l2cache.demand_mshr_miss_rate::total 0.999042 # mshr miss rate for demand accesses 676system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 677system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996198 # mshr miss rate for overall accesses 678system.cpu.l2cache.overall_mshr_miss_rate::total 0.999042 # mshr miss rate for overall accesses 679system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69898.989899 # average ReadExReq mshr miss latency 680system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69898.989899 # average ReadExReq mshr miss latency 681system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75220.230474 # average ReadCleanReq mshr miss latency 682system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75220.230474 # average ReadCleanReq mshr miss latency 683system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 100062.500000 # average ReadSharedReq mshr miss latency 684system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 100062.500000 # average ReadSharedReq mshr miss latency 685system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency 686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency 687system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency 688system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75220.230474 # average overall mshr miss latency 689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77267.175573 # average overall mshr miss latency 690system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75734.419942 # average overall mshr miss latency 691system.cpu.toL2Bus.snoop_filter.tot_requests 1058 # Total number of requests made to the snoop filter. 692system.cpu.toL2Bus.snoop_filter.hit_single_requests 15 # Number of requests hitting in the snoop filter with a single holder of the requested data. 693system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 694system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 695system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 696system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 697system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states 698system.cpu.toL2Bus.trans_dist::ReadResp 846 # Transaction distribution 699system.cpu.toL2Bus.trans_dist::WritebackClean 14 # Transaction distribution 700system.cpu.toL2Bus.trans_dist::ReadExReq 198 # Transaction distribution 701system.cpu.toL2Bus.trans_dist::ReadExResp 198 # Transaction distribution 702system.cpu.toL2Bus.trans_dist::ReadCleanReq 781 # Transaction distribution 703system.cpu.toL2Bus.trans_dist::ReadSharedReq 65 # Transaction distribution 704system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1576 # Packet count per connected master and slave (bytes) 705system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 526 # Packet count per connected master and slave (bytes) 706system.cpu.toL2Bus.pkt_count::total 2102 # Packet count per connected master and slave (bytes) 707system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50880 # Cumulative packet size per connected master and slave (bytes) 708system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16832 # Cumulative packet size per connected master and slave (bytes) 709system.cpu.toL2Bus.pkt_size::total 67712 # Cumulative packet size per connected master and slave (bytes) 710system.cpu.toL2Bus.snoops 0 # Total snoops (count) 711system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 712system.cpu.toL2Bus.snoop_fanout::samples 1044 # Request fanout histogram 713system.cpu.toL2Bus.snoop_fanout::mean 0.000958 # Request fanout histogram 714system.cpu.toL2Bus.snoop_fanout::stdev 0.030949 # Request fanout histogram 715system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 716system.cpu.toL2Bus.snoop_fanout::0 1043 99.90% 99.90% # Request fanout histogram 717system.cpu.toL2Bus.snoop_fanout::1 1 0.10% 100.00% # Request fanout histogram 718system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 719system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 720system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 721system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 722system.cpu.toL2Bus.snoop_fanout::total 1044 # Request fanout histogram 723system.cpu.toL2Bus.reqLayer0.occupancy 543000 # Layer occupancy (ticks) 724system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 725system.cpu.toL2Bus.respLayer0.occupancy 1171500 # Layer occupancy (ticks) 726system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) 727system.cpu.toL2Bus.respLayer1.occupancy 394500 # Layer occupancy (ticks) 728system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 729system.membus.snoop_filter.tot_requests 1043 # Total number of requests made to the snoop filter. 730system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 731system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 732system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 733system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 734system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 735system.membus.pwrStateResidencyTicks::UNDEFINED 165091500 # Cumulative time (in ticks) in various power states 736system.membus.trans_dist::ReadResp 845 # Transaction distribution 737system.membus.trans_dist::ReadExReq 198 # Transaction distribution 738system.membus.trans_dist::ReadExResp 198 # Transaction distribution 739system.membus.trans_dist::ReadSharedReq 845 # Transaction distribution 740system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2086 # Packet count per connected master and slave (bytes) 741system.membus.pkt_count::total 2086 # Packet count per connected master and slave (bytes) 742system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 66752 # Cumulative packet size per connected master and slave (bytes) 743system.membus.pkt_size::total 66752 # Cumulative packet size per connected master and slave (bytes) 744system.membus.snoops 0 # Total snoops (count) 745system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 746system.membus.snoop_fanout::samples 1043 # Request fanout histogram 747system.membus.snoop_fanout::mean 0 # Request fanout histogram 748system.membus.snoop_fanout::stdev 0 # Request fanout histogram 749system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 750system.membus.snoop_fanout::0 1043 100.00% 100.00% # Request fanout histogram 751system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 752system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 753system.membus.snoop_fanout::min_value 0 # Request fanout histogram 754system.membus.snoop_fanout::max_value 0 # Request fanout histogram 755system.membus.snoop_fanout::total 1043 # Request fanout histogram 756system.membus.reqLayer0.occupancy 1170000 # Layer occupancy (ticks) 757system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 758system.membus.respLayer1.occupancy 5535750 # Layer occupancy (ticks) 759system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
| 3sim_seconds 0.000178 4sim_ticks 177558500 5final_tick 177558500 6sim_freq 1000000000000 7host_inst_rate 5771 8host_op_rate 5782 9host_tick_rate 9526846 10host_mem_usage 272764 11host_seconds 18.64 12sim_insts 107550 13sim_ops 107762 14system.voltage_domain.voltage 1 15system.clk_domain.clock 1000 16system.physmem.pwrStateResidencyTicks::UNDEFINED 177558500 17system.physmem.bytes_read::cpu.inst 60544 18system.physmem.bytes_read::cpu.data 29504 19system.physmem.bytes_read::total 90048 20system.physmem.bytes_inst_read::cpu.inst 60544 21system.physmem.bytes_inst_read::total 60544 22system.physmem.num_reads::cpu.inst 946 23system.physmem.num_reads::cpu.data 461 24system.physmem.num_reads::total 1407 25system.physmem.bw_read::cpu.inst 340980578 26system.physmem.bw_read::cpu.data 166164954 27system.physmem.bw_read::total 507145532 28system.physmem.bw_inst_read::cpu.inst 340980578 29system.physmem.bw_inst_read::total 340980578 30system.physmem.bw_total::cpu.inst 340980578 31system.physmem.bw_total::cpu.data 166164954 32system.physmem.bw_total::total 507145532 33system.physmem.readReqs 1407 34system.physmem.writeReqs 0 35system.physmem.readBursts 1407 36system.physmem.writeBursts 0 37system.physmem.bytesReadDRAM 90048 38system.physmem.bytesReadWrQ 0 39system.physmem.bytesWritten 0 40system.physmem.bytesReadSys 90048 41system.physmem.bytesWrittenSys 0 42system.physmem.servicedByWrQ 0 43system.physmem.mergedWrBursts 0 44system.physmem.neitherReadNorWriteReqs 0 45system.physmem.perBankRdBursts::0 165 46system.physmem.perBankRdBursts::1 82 47system.physmem.perBankRdBursts::2 125 48system.physmem.perBankRdBursts::3 86 49system.physmem.perBankRdBursts::4 28 50system.physmem.perBankRdBursts::5 90 51system.physmem.perBankRdBursts::6 29 52system.physmem.perBankRdBursts::7 35 53system.physmem.perBankRdBursts::8 84 54system.physmem.perBankRdBursts::9 137 55system.physmem.perBankRdBursts::10 194 56system.physmem.perBankRdBursts::11 146 57system.physmem.perBankRdBursts::12 52 58system.physmem.perBankRdBursts::13 53 59system.physmem.perBankRdBursts::14 55 60system.physmem.perBankRdBursts::15 46 61system.physmem.perBankWrBursts::0 0 62system.physmem.perBankWrBursts::1 0 63system.physmem.perBankWrBursts::2 0 64system.physmem.perBankWrBursts::3 0 65system.physmem.perBankWrBursts::4 0 66system.physmem.perBankWrBursts::5 0 67system.physmem.perBankWrBursts::6 0 68system.physmem.perBankWrBursts::7 0 69system.physmem.perBankWrBursts::8 0 70system.physmem.perBankWrBursts::9 0 71system.physmem.perBankWrBursts::10 0 72system.physmem.perBankWrBursts::11 0 73system.physmem.perBankWrBursts::12 0 74system.physmem.perBankWrBursts::13 0 75system.physmem.perBankWrBursts::14 0 76system.physmem.perBankWrBursts::15 0 77system.physmem.numRdRetry 0 78system.physmem.numWrRetry 0 79system.physmem.totGap 177461500 80system.physmem.readPktSize::0 0 81system.physmem.readPktSize::1 0 82system.physmem.readPktSize::2 0 83system.physmem.readPktSize::3 0 84system.physmem.readPktSize::4 0 85system.physmem.readPktSize::5 0 86system.physmem.readPktSize::6 1407 87system.physmem.writePktSize::0 0 88system.physmem.writePktSize::1 0 89system.physmem.writePktSize::2 0 90system.physmem.writePktSize::3 0 91system.physmem.writePktSize::4 0 92system.physmem.writePktSize::5 0 93system.physmem.writePktSize::6 0 94system.physmem.rdQLenPdf::0 1197 95system.physmem.rdQLenPdf::1 197 96system.physmem.rdQLenPdf::2 13 97system.physmem.rdQLenPdf::3 0 98system.physmem.rdQLenPdf::4 0 99system.physmem.rdQLenPdf::5 0 100system.physmem.rdQLenPdf::6 0 101system.physmem.rdQLenPdf::7 0 102system.physmem.rdQLenPdf::8 0 103system.physmem.rdQLenPdf::9 0 104system.physmem.rdQLenPdf::10 0 105system.physmem.rdQLenPdf::11 0 106system.physmem.rdQLenPdf::12 0 107system.physmem.rdQLenPdf::13 0 108system.physmem.rdQLenPdf::14 0 109system.physmem.rdQLenPdf::15 0 110system.physmem.rdQLenPdf::16 0 111system.physmem.rdQLenPdf::17 0 112system.physmem.rdQLenPdf::18 0 113system.physmem.rdQLenPdf::19 0 114system.physmem.rdQLenPdf::20 0 115system.physmem.rdQLenPdf::21 0 116system.physmem.rdQLenPdf::22 0 117system.physmem.rdQLenPdf::23 0 118system.physmem.rdQLenPdf::24 0 119system.physmem.rdQLenPdf::25 0 120system.physmem.rdQLenPdf::26 0 121system.physmem.rdQLenPdf::27 0 122system.physmem.rdQLenPdf::28 0 123system.physmem.rdQLenPdf::29 0 124system.physmem.rdQLenPdf::30 0 125system.physmem.rdQLenPdf::31 0 126system.physmem.wrQLenPdf::0 0 127system.physmem.wrQLenPdf::1 0 128system.physmem.wrQLenPdf::2 0 129system.physmem.wrQLenPdf::3 0 130system.physmem.wrQLenPdf::4 0 131system.physmem.wrQLenPdf::5 0 132system.physmem.wrQLenPdf::6 0 133system.physmem.wrQLenPdf::7 0 134system.physmem.wrQLenPdf::8 0 135system.physmem.wrQLenPdf::9 0 136system.physmem.wrQLenPdf::10 0 137system.physmem.wrQLenPdf::11 0 138system.physmem.wrQLenPdf::12 0 139system.physmem.wrQLenPdf::13 0 140system.physmem.wrQLenPdf::14 0 141system.physmem.wrQLenPdf::15 0 142system.physmem.wrQLenPdf::16 0 143system.physmem.wrQLenPdf::17 0 144system.physmem.wrQLenPdf::18 0 145system.physmem.wrQLenPdf::19 0 146system.physmem.wrQLenPdf::20 0 147system.physmem.wrQLenPdf::21 0 148system.physmem.wrQLenPdf::22 0 149system.physmem.wrQLenPdf::23 0 150system.physmem.wrQLenPdf::24 0 151system.physmem.wrQLenPdf::25 0 152system.physmem.wrQLenPdf::26 0 153system.physmem.wrQLenPdf::27 0 154system.physmem.wrQLenPdf::28 0 155system.physmem.wrQLenPdf::29 0 156system.physmem.wrQLenPdf::30 0 157system.physmem.wrQLenPdf::31 0 158system.physmem.wrQLenPdf::32 0 159system.physmem.wrQLenPdf::33 0 160system.physmem.wrQLenPdf::34 0 161system.physmem.wrQLenPdf::35 0 162system.physmem.wrQLenPdf::36 0 163system.physmem.wrQLenPdf::37 0 164system.physmem.wrQLenPdf::38 0 165system.physmem.wrQLenPdf::39 0 166system.physmem.wrQLenPdf::40 0 167system.physmem.wrQLenPdf::41 0 168system.physmem.wrQLenPdf::42 0 169system.physmem.wrQLenPdf::43 0 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49.82% 196system.physmem.bytesPerActivate::256-383 48 17.58% 67.40% 197system.physmem.bytesPerActivate::384-511 26 9.52% 76.92% 198system.physmem.bytesPerActivate::512-639 16 5.86% 82.78% 199system.physmem.bytesPerActivate::640-767 15 5.49% 88.28% 200system.physmem.bytesPerActivate::768-895 7 2.56% 90.84% 201system.physmem.bytesPerActivate::896-1023 7 2.56% 93.41% 202system.physmem.bytesPerActivate::1024-1151 18 6.59% 100.00% 203system.physmem.bytesPerActivate::total 273 204system.physmem.totQLat 18087250 205system.physmem.totMemAccLat 44468500 206system.physmem.totBusLat 7035000 207system.physmem.avgQLat 12855.19 208system.physmem.avgBusLat 5000.00 209system.physmem.avgMemAccLat 31605.19 210system.physmem.avgRdBW 507.15 211system.physmem.avgWrBW 0.00 212system.physmem.avgRdBWSys 507.15 213system.physmem.avgWrBWSys 0.00 214system.physmem.peakBW 12800.00 215system.physmem.busUtil 3.96 216system.physmem.busUtilRead 3.96 217system.physmem.busUtilWrite 0.00 218system.physmem.avgRdQLen 1.13 219system.physmem.avgWrQLen 0.00 220system.physmem.readRowHits 1122 221system.physmem.writeRowHits 0 222system.physmem.readRowHitRate 79.74 223system.physmem.writeRowHitRate nan 224system.physmem.avgGap 126127.58 225system.physmem.pageHitRate 79.74 226system.physmem_0.actEnergy 821100 227system.physmem_0.preEnergy 413655 228system.physmem_0.readEnergy 4569600 229system.physmem_0.writeEnergy 0 230system.physmem_0.refreshEnergy 13522080.000000 231system.physmem_0.actBackEnergy 11049450 232system.physmem_0.preBackEnergy 315840 233system.physmem_0.actPowerDownEnergy 64094790 234system.physmem_0.prePowerDownEnergy 4587360 235system.physmem_0.selfRefreshEnergy 0 236system.physmem_0.totalEnergy 99373875 237system.physmem_0.averagePower 559.667575 238system.physmem_0.totalIdleTime 152474000 239system.physmem_0.memoryStateTime::IDLE 144000 240system.physmem_0.memoryStateTime::REF 5720000 241system.physmem_0.memoryStateTime::SREF 0 242system.physmem_0.memoryStateTime::PRE_PDN 11945000 243system.physmem_0.memoryStateTime::ACT 19174000 244system.physmem_0.memoryStateTime::ACT_PDN 140575500 245system.physmem_1.actEnergy 1213800 246system.physmem_1.preEnergy 622380 247system.physmem_1.readEnergy 5476380 248system.physmem_1.writeEnergy 0 249system.physmem_1.refreshEnergy 13522080.000000 250system.physmem_1.actBackEnergy 12400350 251system.physmem_1.preBackEnergy 386400 252system.physmem_1.actPowerDownEnergy 59656770 253system.physmem_1.prePowerDownEnergy 7116480 254system.physmem_1.selfRefreshEnergy 0 255system.physmem_1.totalEnergy 100394640 256system.physmem_1.averagePower 565.416461 257system.physmem_1.totalIdleTime 149184750 258system.physmem_1.memoryStateTime::IDLE 398000 259system.physmem_1.memoryStateTime::REF 5720000 260system.physmem_1.memoryStateTime::SREF 0 261system.physmem_1.memoryStateTime::PRE_PDN 18527500 262system.physmem_1.memoryStateTime::ACT 22078000 263system.physmem_1.memoryStateTime::ACT_PDN 130835000 264system.pwrStateResidencyTicks::UNDEFINED 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317system.cpu.op_class_0::FloatDiv 0 0.00% 61.39% 318system.cpu.op_class_0::FloatMisc 0 0.00% 61.39% 319system.cpu.op_class_0::FloatSqrt 0 0.00% 61.39% 320system.cpu.op_class_0::SimdAdd 0 0.00% 61.39% 321system.cpu.op_class_0::SimdAddAcc 0 0.00% 61.39% 322system.cpu.op_class_0::SimdAlu 0 0.00% 61.39% 323system.cpu.op_class_0::SimdCmp 0 0.00% 61.39% 324system.cpu.op_class_0::SimdCvt 0 0.00% 61.39% 325system.cpu.op_class_0::SimdMisc 0 0.00% 61.39% 326system.cpu.op_class_0::SimdMult 0 0.00% 61.39% 327system.cpu.op_class_0::SimdMultAcc 0 0.00% 61.39% 328system.cpu.op_class_0::SimdShift 0 0.00% 61.39% 329system.cpu.op_class_0::SimdShiftAcc 0 0.00% 61.39% 330system.cpu.op_class_0::SimdSqrt 0 0.00% 61.39% 331system.cpu.op_class_0::SimdFloatAdd 0 0.00% 61.39% 332system.cpu.op_class_0::SimdFloatAlu 0 0.00% 61.39% 333system.cpu.op_class_0::SimdFloatCmp 0 0.00% 61.39% 334system.cpu.op_class_0::SimdFloatCvt 0 0.00% 61.39% 335system.cpu.op_class_0::SimdFloatDiv 0 0.00% 61.39% 336system.cpu.op_class_0::SimdFloatMisc 0 0.00% 61.39% 337system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.39% 338system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.39% 339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.39% 340system.cpu.op_class_0::MemRead 25266 23.45% 84.84% 341system.cpu.op_class_0::MemWrite 16327 15.15% 99.99% 342system.cpu.op_class_0::FloatMemRead 0 0.00% 99.99% 343system.cpu.op_class_0::FloatMemWrite 12 0.01% 100.00% 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% 346system.cpu.op_class_0::total 107762 347system.cpu.tickCycles 166468 348system.cpu.idleCycles 188649 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 177558500 350system.cpu.dcache.tags.replacements 0 351system.cpu.dcache.tags.tagsinuse 305.890276 352system.cpu.dcache.tags.total_refs 42081 353system.cpu.dcache.tags.sampled_refs 462 354system.cpu.dcache.tags.avg_refs 91.084416 355system.cpu.dcache.tags.warmup_cycle 0 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