3,513c3,547
< sim_seconds 0.000353 # Number of seconds simulated
< sim_ticks 352925500 # Number of ticks simulated
< final_tick 352925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
< sim_freq 1000000000000 # Frequency of simulated ticks
< host_inst_rate 23308 # Simulator instruction rate (inst/s)
< host_op_rate 23308 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 40827277 # Simulator tick rate (ticks/s)
< host_mem_usage 243536 # Number of bytes of host memory used
< host_seconds 8.64 # Real time elapsed on the host
< sim_insts 201478 # Number of instructions simulated
< sim_ops 201478 # Number of ops (including micro ops) simulated
< system.voltage_domain.voltage 1 # Voltage in Volts
< system.clk_domain.clock 1000 # Clock period in ticks
< system.physmem.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 55168 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 18368 # Number of bytes read from this memory
< system.physmem.bytes_read::total 73536 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 55168 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 55168 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 862 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 287 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1149 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 156316276 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 52044978 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 208361255 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 156316276 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 156316276 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 156316276 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 52044978 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 208361255 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.cpu.dtb.read_hits 0 # DTB read hits
< system.cpu.dtb.read_misses 0 # DTB read misses
< system.cpu.dtb.read_accesses 0 # DTB read accesses
< system.cpu.dtb.write_hits 0 # DTB write hits
< system.cpu.dtb.write_misses 0 # DTB write misses
< system.cpu.dtb.write_accesses 0 # DTB write accesses
< system.cpu.dtb.hits 0 # DTB hits
< system.cpu.dtb.misses 0 # DTB misses
< system.cpu.dtb.accesses 0 # DTB accesses
< system.cpu.itb.read_hits 0 # DTB read hits
< system.cpu.itb.read_misses 0 # DTB read misses
< system.cpu.itb.read_accesses 0 # DTB read accesses
< system.cpu.itb.write_hits 0 # DTB write hits
< system.cpu.itb.write_misses 0 # DTB write misses
< system.cpu.itb.write_accesses 0 # DTB write accesses
< system.cpu.itb.hits 0 # DTB hits
< system.cpu.itb.misses 0 # DTB misses
< system.cpu.itb.accesses 0 # DTB accesses
< system.cpu.workload.num_syscalls 130 # Number of system calls
< system.cpu.pwrStateResidencyTicks::ON 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 705851 # number of cpu cycles simulated
< system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
< system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
< system.cpu.committedInsts 201478 # Number of instructions committed
< system.cpu.committedOps 201478 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 201477 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
< system.cpu.num_func_calls 14627 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 30164 # number of instructions that are conditional controls
< system.cpu.num_int_insts 201477 # number of integer instructions
< system.cpu.num_fp_insts 0 # number of float instructions
< system.cpu.num_int_register_reads 266871 # number of times the integer registers were read
< system.cpu.num_int_register_writes 137624 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
< system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
< system.cpu.num_mem_refs 80078 # number of memory refs
< system.cpu.num_load_insts 46389 # Number of load instructions
< system.cpu.num_store_insts 33689 # Number of store instructions
< system.cpu.num_idle_cycles 0 # Number of idle cycles
< system.cpu.num_busy_cycles 705851 # Number of busy cycles
< system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0 # Percentage of idle cycles
< system.cpu.Branches 44791 # Number of branches fetched
< system.cpu.op_class::No_OpClass 132 0.07% 0.07% # Class of executed instruction
< system.cpu.op_class::IntAlu 120936 59.99% 60.05% # Class of executed instruction
< system.cpu.op_class::IntMult 297 0.15% 60.20% # Class of executed instruction
< system.cpu.op_class::IntDiv 166 0.08% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatAdd 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatCmp 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatCvt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatMult 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatMultAcc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatDiv 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatMisc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatSqrt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdAdd 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdAddAcc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdAlu 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdCmp 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdCvt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdMisc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdMult 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdMultAcc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdShift 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdShiftAcc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdSqrt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatAdd 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatAlu 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatCmp 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatCvt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatDiv 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatMisc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatMult 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::MemRead 46389 23.01% 83.29% # Class of executed instruction
< system.cpu.op_class::MemWrite 33689 16.71% 100.00% # Class of executed instruction
< system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
< system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
< system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
< system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
< system.cpu.op_class::total 201609 # Class of executed instruction
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 237.806291 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 79790 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 287 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 278.013937 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 237.806291 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.058058 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.058058 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 287 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.070068 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 160441 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 160441 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 46314 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 46314 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 33476 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 33476 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 79790 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 79790 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 79790 # number of overall hits
< system.cpu.dcache.overall_hits::total 79790 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 212 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 212 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 287 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 287 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 287 # number of overall misses
< system.cpu.dcache.overall_misses::total 287 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4725000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4725000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 13356000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 13356000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 18081000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 18081000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 18081000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 18081000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 46389 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 46389 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 80077 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 80077 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 80077 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 80077 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001617 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.001617 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006293 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.006293 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.003584 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.003584 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.003584 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.003584 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 75 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 75 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 212 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 212 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4650000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4650000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13144000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 13144000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17794000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 17794000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17794000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 17794000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001617 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001617 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006293 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006293 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.003584 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.003584 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 16 # number of replacements
< system.cpu.icache.tags.tagsinuse 467.242122 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 200748 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 862 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 232.886311 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 467.242122 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.228146 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.228146 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 846 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 632 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.413086 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 404082 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 404082 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 200748 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 200748 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 200748 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 200748 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 200748 # number of overall hits
< system.cpu.icache.overall_hits::total 200748 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 862 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 862 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 862 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 862 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 862 # number of overall misses
< system.cpu.icache.overall_misses::total 862 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 54307500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 54307500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 54307500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 54307500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 54307500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 54307500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 201610 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 201610 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 201610 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 201610 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 201610 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 201610 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004276 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.004276 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.004276 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.004276 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.004276 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.004276 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63001.740139 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 63001.740139 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 63001.740139 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 63001.740139 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 16 # number of writebacks
< system.cpu.icache.writebacks::total 16 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 862 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 862 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 862 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 862 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53445500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 53445500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53445500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 53445500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53445500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 53445500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004276 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.004276 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.004276 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62001.740139 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62001.740139 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62001.740139 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 62001.740139 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62001.740139 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 62001.740139 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 0 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 708.129693 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1149 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.013925 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 470.314864 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 237.814829 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.014353 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.007258 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.021610 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 1149 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.035065 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 10469 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 10469 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackClean_hits::writebacks 16 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 16 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 212 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 212 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 862 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 862 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 75 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 862 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 287 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1149 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 862 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 287 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1149 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12826000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 12826000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52152000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 52152000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4537500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 4537500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 52152000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 17363500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 69515500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 52152000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 17363500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 69515500 # number of overall miss cycles
< system.cpu.l2cache.WritebackClean_accesses::writebacks 16 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 16 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 212 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 212 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 862 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 862 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 75 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 75 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 862 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 287 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1149 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 862 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 287 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1149 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.160093 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.160093 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.160093 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 60500.870322 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.160093 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 60500.870322 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 212 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 212 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 862 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 862 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 75 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 75 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1149 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1149 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10706000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10706000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43532000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43532000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3787500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3787500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43532000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14493500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 58025500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43532000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14493500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 58025500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.160093 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.160093 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 1165 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 16 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 937 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 212 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 212 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 862 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 75 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1740 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 574 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 2314 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56192 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 74560 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 0 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 1149 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 1149 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 598500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 1293000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 430500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
< system.membus.snoop_filter.tot_requests 1149 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
< system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.membus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 937 # Transaction distribution
< system.membus.trans_dist::ReadExReq 212 # Transaction distribution
< system.membus.trans_dist::ReadExResp 212 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 937 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2298 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 2298 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73536 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 73536 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 1149 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 1149 # Request fanout histogram
< system.membus.reqLayer0.occupancy 1150000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
< system.membus.respLayer1.occupancy 5745000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 1.6 # Layer utilization (%)
---
> sim_seconds 0.000509
> sim_ticks 508585500
> final_tick 508585500
> sim_freq 1000000000000
> host_inst_rate 3721
> host_op_rate 3732
> host_tick_rate 7088392
> host_mem_usage 270008
> host_seconds 71.75
> sim_insts 266983
> sim_ops 267753
> system.voltage_domain.voltage 1
> system.clk_domain.clock 1000
> system.physmem.pwrStateResidencyTicks::UNDEFINED 508585500
> system.physmem.bytes_read::cpu.inst 60992
> system.physmem.bytes_read::cpu.data 30976
> system.physmem.bytes_read::total 91968
> system.physmem.bytes_inst_read::cpu.inst 60992
> system.physmem.bytes_inst_read::total 60992
> system.physmem.num_reads::cpu.inst 953
> system.physmem.num_reads::cpu.data 484
> system.physmem.num_reads::total 1437
> system.physmem.bw_read::cpu.inst 119924772
> system.physmem.bw_read::cpu.data 60906180
> system.physmem.bw_read::total 180830952
> system.physmem.bw_inst_read::cpu.inst 119924772
> system.physmem.bw_inst_read::total 119924772
> system.physmem.bw_total::cpu.inst 119924772
> system.physmem.bw_total::cpu.data 60906180
> system.physmem.bw_total::total 180830952
> system.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu_clk_domain.clock 500
> system.cpu.dtb.read_hits 0
> system.cpu.dtb.read_misses 0
> system.cpu.dtb.read_accesses 0
> system.cpu.dtb.write_hits 0
> system.cpu.dtb.write_misses 0
> system.cpu.dtb.write_accesses 0
> system.cpu.dtb.hits 0
> system.cpu.dtb.misses 0
> system.cpu.dtb.accesses 0
> system.cpu.itb.read_hits 0
> system.cpu.itb.read_misses 0
> system.cpu.itb.read_accesses 0
> system.cpu.itb.write_hits 0
> system.cpu.itb.write_misses 0
> system.cpu.itb.write_accesses 0
> system.cpu.itb.hits 0
> system.cpu.itb.misses 0
> system.cpu.itb.accesses 0
> system.cpu.workload.numSyscalls 182
> system.cpu.pwrStateResidencyTicks::ON 508585500
> system.cpu.numCycles 1017171
> system.cpu.numWorkItemsStarted 0
> system.cpu.numWorkItemsCompleted 0
> system.cpu.committedInsts 266983
> system.cpu.committedOps 267753
> system.cpu.num_int_alu_accesses 266336
> system.cpu.num_fp_alu_accesses 12
> system.cpu.num_vec_alu_accesses 0
> system.cpu.num_func_calls 15688
> system.cpu.num_conditional_control_insts 41227
> system.cpu.num_int_insts 266336
> system.cpu.num_fp_insts 12
> system.cpu.num_vec_insts 0
> system.cpu.num_int_register_reads 334534
> system.cpu.num_int_register_writes 178355
> system.cpu.num_fp_register_reads 12
> system.cpu.num_fp_register_writes 0
> system.cpu.num_vec_register_reads 0
> system.cpu.num_vec_register_writes 0
> system.cpu.num_mem_refs 109337
> system.cpu.num_load_insts 67806
> system.cpu.num_store_insts 41531
> system.cpu.num_idle_cycles 0
> system.cpu.num_busy_cycles 1017171
> system.cpu.not_idle_fraction 1
> system.cpu.idle_fraction 0
> system.cpu.Branches 56915
> system.cpu.op_class::No_OpClass 191 0.07% 0.07%
> system.cpu.op_class::IntAlu 157741 58.87% 58.94%
> system.cpu.op_class::IntMult 436 0.16% 59.11%
> system.cpu.op_class::IntDiv 230 0.09% 59.19%
> system.cpu.op_class::FloatAdd 0 0.00% 59.19%
> system.cpu.op_class::FloatCmp 0 0.00% 59.19%
> system.cpu.op_class::FloatCvt 0 0.00% 59.19%
> system.cpu.op_class::FloatMult 0 0.00% 59.19%
> system.cpu.op_class::FloatMultAcc 0 0.00% 59.19%
> system.cpu.op_class::FloatDiv 0 0.00% 59.19%
> system.cpu.op_class::FloatMisc 0 0.00% 59.19%
> system.cpu.op_class::FloatSqrt 0 0.00% 59.19%
> system.cpu.op_class::SimdAdd 0 0.00% 59.19%
> system.cpu.op_class::SimdAddAcc 0 0.00% 59.19%
> system.cpu.op_class::SimdAlu 0 0.00% 59.19%
> system.cpu.op_class::SimdCmp 0 0.00% 59.19%
> system.cpu.op_class::SimdCvt 0 0.00% 59.19%
> system.cpu.op_class::SimdMisc 0 0.00% 59.19%
> system.cpu.op_class::SimdMult 0 0.00% 59.19%
> system.cpu.op_class::SimdMultAcc 0 0.00% 59.19%
> system.cpu.op_class::SimdShift 0 0.00% 59.19%
> system.cpu.op_class::SimdShiftAcc 0 0.00% 59.19%
> system.cpu.op_class::SimdSqrt 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatAdd 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatAlu 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatCmp 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatCvt 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatDiv 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatMisc 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatMult 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.19%
> system.cpu.op_class::MemRead 67806 25.31% 84.50%
> system.cpu.op_class::MemWrite 41519 15.50% 100.00%
> system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
> system.cpu.op_class::FloatMemWrite 12 0.00% 100.00%
> system.cpu.op_class::IprAccess 0 0.00% 100.00%
> system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
> system.cpu.op_class::total 267935
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.dcache.tags.replacements 0
> system.cpu.dcache.tags.tagsinuse 397.981012
> system.cpu.dcache.tags.total_refs 108853
> system.cpu.dcache.tags.sampled_refs 484
> system.cpu.dcache.tags.avg_refs 224.902893
> system.cpu.dcache.tags.warmup_cycle 0
> system.cpu.dcache.tags.occ_blocks::cpu.data 397.981012
> system.cpu.dcache.tags.occ_percent::cpu.data 0.097163
> system.cpu.dcache.tags.occ_percent::total 0.097163
> system.cpu.dcache.tags.occ_task_id_blocks::1024 484
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 14
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 7
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 463
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.118164
> system.cpu.dcache.tags.tag_accesses 219158
> system.cpu.dcache.tags.data_accesses 219158
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.dcache.ReadReq_hits::cpu.data 66769
> system.cpu.dcache.ReadReq_hits::total 66769
> system.cpu.dcache.WriteReq_hits::cpu.data 40527
> system.cpu.dcache.WriteReq_hits::total 40527
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 778
> system.cpu.dcache.LoadLockedReq_hits::total 778
> system.cpu.dcache.StoreCondReq_hits::cpu.data 779
> system.cpu.dcache.StoreCondReq_hits::total 779
> system.cpu.dcache.demand_hits::cpu.data 107296
> system.cpu.dcache.demand_hits::total 107296
> system.cpu.dcache.overall_hits::cpu.data 107296
> system.cpu.dcache.overall_hits::total 107296
> system.cpu.dcache.ReadReq_misses::cpu.data 258
> system.cpu.dcache.ReadReq_misses::total 258
> system.cpu.dcache.WriteReq_misses::cpu.data 225
> system.cpu.dcache.WriteReq_misses::total 225
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 1
> system.cpu.dcache.LoadLockedReq_misses::total 1
> system.cpu.dcache.demand_misses::cpu.data 483
> system.cpu.dcache.demand_misses::total 483
> system.cpu.dcache.overall_misses::cpu.data 483
> system.cpu.dcache.overall_misses::total 483
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 16254000
> system.cpu.dcache.ReadReq_miss_latency::total 16254000
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 14175000
> system.cpu.dcache.WriteReq_miss_latency::total 14175000
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63000
> system.cpu.dcache.LoadLockedReq_miss_latency::total 63000
> system.cpu.dcache.demand_miss_latency::cpu.data 30429000
> system.cpu.dcache.demand_miss_latency::total 30429000
> system.cpu.dcache.overall_miss_latency::cpu.data 30429000
> system.cpu.dcache.overall_miss_latency::total 30429000
> system.cpu.dcache.ReadReq_accesses::cpu.data 67027
> system.cpu.dcache.ReadReq_accesses::total 67027
> system.cpu.dcache.WriteReq_accesses::cpu.data 40752
> system.cpu.dcache.WriteReq_accesses::total 40752
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 779
> system.cpu.dcache.LoadLockedReq_accesses::total 779
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 779
> system.cpu.dcache.StoreCondReq_accesses::total 779
> system.cpu.dcache.demand_accesses::cpu.data 107779
> system.cpu.dcache.demand_accesses::total 107779
> system.cpu.dcache.overall_accesses::cpu.data 107779
> system.cpu.dcache.overall_accesses::total 107779
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003849
> system.cpu.dcache.ReadReq_miss_rate::total 0.003849
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005521
> system.cpu.dcache.WriteReq_miss_rate::total 0.005521
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001284
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001284
> system.cpu.dcache.demand_miss_rate::cpu.data 0.004481
> system.cpu.dcache.demand_miss_rate::total 0.004481
> system.cpu.dcache.overall_miss_rate::cpu.data 0.004481
> system.cpu.dcache.overall_miss_rate::total 0.004481
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63000
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000
> system.cpu.dcache.demand_avg_miss_latency::total 63000
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000
> system.cpu.dcache.overall_avg_miss_latency::total 63000
> system.cpu.dcache.blocked_cycles::no_mshrs 0
> system.cpu.dcache.blocked_cycles::no_targets 0
> system.cpu.dcache.blocked::no_mshrs 0
> system.cpu.dcache.blocked::no_targets 0
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
> system.cpu.dcache.avg_blocked_cycles::no_targets nan
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 258
> system.cpu.dcache.ReadReq_mshr_misses::total 258
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 225
> system.cpu.dcache.WriteReq_mshr_misses::total 225
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 1
> system.cpu.dcache.demand_mshr_misses::cpu.data 483
> system.cpu.dcache.demand_mshr_misses::total 483
> system.cpu.dcache.overall_mshr_misses::cpu.data 483
> system.cpu.dcache.overall_mshr_misses::total 483
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15996000
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 15996000
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13950000
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 13950000
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 62000
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29946000
> system.cpu.dcache.demand_mshr_miss_latency::total 29946000
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29946000
> system.cpu.dcache.overall_mshr_miss_latency::total 29946000
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003849
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003849
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005521
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005521
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001284
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001284
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004481
> system.cpu.dcache.demand_mshr_miss_rate::total 0.004481
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004481
> system.cpu.dcache.overall_mshr_miss_rate::total 0.004481
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 62000
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.icache.tags.replacements 44
> system.cpu.icache.tags.tagsinuse 603.393635
> system.cpu.icache.tags.total_refs 309176
> system.cpu.icache.tags.sampled_refs 955
> system.cpu.icache.tags.avg_refs 323.744503
> system.cpu.icache.tags.warmup_cycle 0
> system.cpu.icache.tags.occ_blocks::cpu.inst 603.393635
> system.cpu.icache.tags.occ_percent::cpu.inst 0.294626
> system.cpu.icache.tags.occ_percent::total 0.294626
> system.cpu.icache.tags.occ_task_id_blocks::1024 911
> system.cpu.icache.tags.age_task_id_blocks_1024::0 42
> system.cpu.icache.tags.age_task_id_blocks_1024::1 65
> system.cpu.icache.tags.age_task_id_blocks_1024::2 804
> system.cpu.icache.tags.occ_task_id_percent::1024 0.444824
> system.cpu.icache.tags.tag_accesses 621217
> system.cpu.icache.tags.data_accesses 621217
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.icache.ReadReq_hits::cpu.inst 309176
> system.cpu.icache.ReadReq_hits::total 309176
> system.cpu.icache.demand_hits::cpu.inst 309176
> system.cpu.icache.demand_hits::total 309176
> system.cpu.icache.overall_hits::cpu.inst 309176
> system.cpu.icache.overall_hits::total 309176
> system.cpu.icache.ReadReq_misses::cpu.inst 955
> system.cpu.icache.ReadReq_misses::total 955
> system.cpu.icache.demand_misses::cpu.inst 955
> system.cpu.icache.demand_misses::total 955
> system.cpu.icache.overall_misses::cpu.inst 955
> system.cpu.icache.overall_misses::total 955
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 60065500
> system.cpu.icache.ReadReq_miss_latency::total 60065500
> system.cpu.icache.demand_miss_latency::cpu.inst 60065500
> system.cpu.icache.demand_miss_latency::total 60065500
> system.cpu.icache.overall_miss_latency::cpu.inst 60065500
> system.cpu.icache.overall_miss_latency::total 60065500
> system.cpu.icache.ReadReq_accesses::cpu.inst 310131
> system.cpu.icache.ReadReq_accesses::total 310131
> system.cpu.icache.demand_accesses::cpu.inst 310131
> system.cpu.icache.demand_accesses::total 310131
> system.cpu.icache.overall_accesses::cpu.inst 310131
> system.cpu.icache.overall_accesses::total 310131
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003079
> system.cpu.icache.ReadReq_miss_rate::total 0.003079
> system.cpu.icache.demand_miss_rate::cpu.inst 0.003079
> system.cpu.icache.demand_miss_rate::total 0.003079
> system.cpu.icache.overall_miss_rate::cpu.inst 0.003079
> system.cpu.icache.overall_miss_rate::total 0.003079
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62895.811518
> system.cpu.icache.ReadReq_avg_miss_latency::total 62895.811518
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62895.811518
> system.cpu.icache.demand_avg_miss_latency::total 62895.811518
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62895.811518
> system.cpu.icache.overall_avg_miss_latency::total 62895.811518
> system.cpu.icache.blocked_cycles::no_mshrs 0
> system.cpu.icache.blocked_cycles::no_targets 0
> system.cpu.icache.blocked::no_mshrs 0
> system.cpu.icache.blocked::no_targets 0
> system.cpu.icache.avg_blocked_cycles::no_mshrs nan
> system.cpu.icache.avg_blocked_cycles::no_targets nan
> system.cpu.icache.writebacks::writebacks 44
> system.cpu.icache.writebacks::total 44
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 955
> system.cpu.icache.ReadReq_mshr_misses::total 955
> system.cpu.icache.demand_mshr_misses::cpu.inst 955
> system.cpu.icache.demand_mshr_misses::total 955
> system.cpu.icache.overall_mshr_misses::cpu.inst 955
> system.cpu.icache.overall_mshr_misses::total 955
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59110500
> system.cpu.icache.ReadReq_mshr_miss_latency::total 59110500
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59110500
> system.cpu.icache.demand_mshr_miss_latency::total 59110500
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59110500
> system.cpu.icache.overall_mshr_miss_latency::total 59110500
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.003079
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003079
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.003079
> system.cpu.icache.demand_mshr_miss_rate::total 0.003079
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.003079
> system.cpu.icache.overall_mshr_miss_rate::total 0.003079
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61895.811518
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61895.811518
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61895.811518
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61895.811518
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61895.811518
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61895.811518
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.l2cache.tags.replacements 0
> system.cpu.l2cache.tags.tagsinuse 1026.033062
> system.cpu.l2cache.tags.total_refs 46
> system.cpu.l2cache.tags.sampled_refs 1437
> system.cpu.l2cache.tags.avg_refs 0.032011
> system.cpu.l2cache.tags.warmup_cycle 0
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 628.042057
> system.cpu.l2cache.tags.occ_blocks::cpu.data 397.991005
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.019166
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.012146
> system.cpu.l2cache.tags.occ_percent::total 0.031312
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 1437
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 72
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1309
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.043854
> system.cpu.l2cache.tags.tag_accesses 13301
> system.cpu.l2cache.tags.data_accesses 13301
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.l2cache.WritebackClean_hits::writebacks 44
> system.cpu.l2cache.WritebackClean_hits::total 44
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2
> system.cpu.l2cache.ReadCleanReq_hits::total 2
> system.cpu.l2cache.demand_hits::cpu.inst 2
> system.cpu.l2cache.demand_hits::total 2
> system.cpu.l2cache.overall_hits::cpu.inst 2
> system.cpu.l2cache.overall_hits::total 2
> system.cpu.l2cache.ReadExReq_misses::cpu.data 225
> system.cpu.l2cache.ReadExReq_misses::total 225
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 953
> system.cpu.l2cache.ReadCleanReq_misses::total 953
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 259
> system.cpu.l2cache.ReadSharedReq_misses::total 259
> system.cpu.l2cache.demand_misses::cpu.inst 953
> system.cpu.l2cache.demand_misses::cpu.data 484
> system.cpu.l2cache.demand_misses::total 1437
> system.cpu.l2cache.overall_misses::cpu.inst 953
> system.cpu.l2cache.overall_misses::cpu.data 484
> system.cpu.l2cache.overall_misses::total 1437
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13612500
> system.cpu.l2cache.ReadExReq_miss_latency::total 13612500
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57657000
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 57657000
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15669500
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 15669500
> system.cpu.l2cache.demand_miss_latency::cpu.inst 57657000
> system.cpu.l2cache.demand_miss_latency::cpu.data 29282000
> system.cpu.l2cache.demand_miss_latency::total 86939000
> system.cpu.l2cache.overall_miss_latency::cpu.inst 57657000
> system.cpu.l2cache.overall_miss_latency::cpu.data 29282000
> system.cpu.l2cache.overall_miss_latency::total 86939000
> system.cpu.l2cache.WritebackClean_accesses::writebacks 44
> system.cpu.l2cache.WritebackClean_accesses::total 44
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 225
> system.cpu.l2cache.ReadExReq_accesses::total 225
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 955
> system.cpu.l2cache.ReadCleanReq_accesses::total 955
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 259
> system.cpu.l2cache.ReadSharedReq_accesses::total 259
> system.cpu.l2cache.demand_accesses::cpu.inst 955
> system.cpu.l2cache.demand_accesses::cpu.data 484
> system.cpu.l2cache.demand_accesses::total 1439
> system.cpu.l2cache.overall_accesses::cpu.inst 955
> system.cpu.l2cache.overall_accesses::cpu.data 484
> system.cpu.l2cache.overall_accesses::total 1439
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1
> system.cpu.l2cache.ReadExReq_miss_rate::total 1
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997906
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 1
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.demand_miss_rate::cpu.data 1
> system.cpu.l2cache.demand_miss_rate::total 0.998610
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.overall_miss_rate::cpu.data 1
> system.cpu.l2cache.overall_miss_rate::total 0.998610
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.524659
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.524659
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.524659
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500
> system.cpu.l2cache.demand_avg_miss_latency::total 60500.347947
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.524659
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500
> system.cpu.l2cache.overall_avg_miss_latency::total 60500.347947
> system.cpu.l2cache.blocked_cycles::no_mshrs 0
> system.cpu.l2cache.blocked_cycles::no_targets 0
> system.cpu.l2cache.blocked::no_mshrs 0
> system.cpu.l2cache.blocked::no_targets 0
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 225
> system.cpu.l2cache.ReadExReq_mshr_misses::total 225
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 953
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 953
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 259
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 259
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 953
> system.cpu.l2cache.demand_mshr_misses::cpu.data 484
> system.cpu.l2cache.demand_mshr_misses::total 1437
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 953
> system.cpu.l2cache.overall_mshr_misses::cpu.data 484
> system.cpu.l2cache.overall_mshr_misses::total 1437
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11362500
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11362500
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 48127000
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 48127000
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13079500
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13079500
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48127000
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24442000
> system.cpu.l2cache.demand_mshr_miss_latency::total 72569000
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48127000
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24442000
> system.cpu.l2cache.overall_mshr_miss_latency::total 72569000
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997906
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.998610
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.998610
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.524659
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.524659
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.524659
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.347947
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.524659
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.347947
> system.cpu.toL2Bus.snoop_filter.tot_requests 1483
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 44
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.toL2Bus.trans_dist::ReadResp 1214
> system.cpu.toL2Bus.trans_dist::WritebackClean 44
> system.cpu.toL2Bus.trans_dist::ReadExReq 225
> system.cpu.toL2Bus.trans_dist::ReadExResp 225
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 955
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 259
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1954
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 968
> system.cpu.toL2Bus.pkt_count::total 2922
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63936
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30976
> system.cpu.toL2Bus.pkt_size::total 94912
> system.cpu.toL2Bus.snoops 0
> system.cpu.toL2Bus.snoopTraffic 0
> system.cpu.toL2Bus.snoop_fanout::samples 1439
> system.cpu.toL2Bus.snoop_fanout::mean 0
> system.cpu.toL2Bus.snoop_fanout::stdev 0
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
> system.cpu.toL2Bus.snoop_fanout::0 1439 100.00% 100.00%
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
> system.cpu.toL2Bus.snoop_fanout::min_value 0
> system.cpu.toL2Bus.snoop_fanout::max_value 0
> system.cpu.toL2Bus.snoop_fanout::total 1439
> system.cpu.toL2Bus.reqLayer0.occupancy 785500
> system.cpu.toL2Bus.reqLayer0.utilization 0.2
> system.cpu.toL2Bus.respLayer0.occupancy 1432500
> system.cpu.toL2Bus.respLayer0.utilization 0.3
> system.cpu.toL2Bus.respLayer1.occupancy 726000
> system.cpu.toL2Bus.respLayer1.utilization 0.1
> system.membus.snoop_filter.tot_requests 1437
> system.membus.snoop_filter.hit_single_requests 0
> system.membus.snoop_filter.hit_multi_requests 0
> system.membus.snoop_filter.tot_snoops 0
> system.membus.snoop_filter.hit_single_snoops 0
> system.membus.snoop_filter.hit_multi_snoops 0
> system.membus.pwrStateResidencyTicks::UNDEFINED 508585500
> system.membus.trans_dist::ReadResp 1212
> system.membus.trans_dist::ReadExReq 225
> system.membus.trans_dist::ReadExResp 225
> system.membus.trans_dist::ReadSharedReq 1212
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2874
> system.membus.pkt_count::total 2874
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 91968
> system.membus.pkt_size::total 91968
> system.membus.snoops 0
> system.membus.snoopTraffic 0
> system.membus.snoop_fanout::samples 1437
> system.membus.snoop_fanout::mean 0
> system.membus.snoop_fanout::stdev 0
> system.membus.snoop_fanout::underflows 0 0.00% 0.00%
> system.membus.snoop_fanout::0 1437 100.00% 100.00%
> system.membus.snoop_fanout::1 0 0.00% 100.00%
> system.membus.snoop_fanout::overflows 0 0.00% 100.00%
> system.membus.snoop_fanout::min_value 0
> system.membus.snoop_fanout::max_value 0
> system.membus.snoop_fanout::total 1437
> system.membus.reqLayer0.occupancy 1437500
> system.membus.reqLayer0.utilization 0.3
> system.membus.respLayer1.occupancy 7185000
> system.membus.respLayer1.utilization 1.4
< sim_seconds 0.000353 # Number of seconds simulated
< sim_ticks 352925500 # Number of ticks simulated
< final_tick 352925500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
< sim_freq 1000000000000 # Frequency of simulated ticks
< host_inst_rate 23308 # Simulator instruction rate (inst/s)
< host_op_rate 23308 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 40827277 # Simulator tick rate (ticks/s)
< host_mem_usage 243536 # Number of bytes of host memory used
< host_seconds 8.64 # Real time elapsed on the host
< sim_insts 201478 # Number of instructions simulated
< sim_ops 201478 # Number of ops (including micro ops) simulated
< system.voltage_domain.voltage 1 # Voltage in Volts
< system.clk_domain.clock 1000 # Clock period in ticks
< system.physmem.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 55168 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 18368 # Number of bytes read from this memory
< system.physmem.bytes_read::total 73536 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 55168 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 55168 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 862 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 287 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 1149 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 156316276 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 52044978 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 208361255 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 156316276 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 156316276 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 156316276 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 52044978 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 208361255 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu_clk_domain.clock 500 # Clock period in ticks
< system.cpu.dtb.read_hits 0 # DTB read hits
< system.cpu.dtb.read_misses 0 # DTB read misses
< system.cpu.dtb.read_accesses 0 # DTB read accesses
< system.cpu.dtb.write_hits 0 # DTB write hits
< system.cpu.dtb.write_misses 0 # DTB write misses
< system.cpu.dtb.write_accesses 0 # DTB write accesses
< system.cpu.dtb.hits 0 # DTB hits
< system.cpu.dtb.misses 0 # DTB misses
< system.cpu.dtb.accesses 0 # DTB accesses
< system.cpu.itb.read_hits 0 # DTB read hits
< system.cpu.itb.read_misses 0 # DTB read misses
< system.cpu.itb.read_accesses 0 # DTB read accesses
< system.cpu.itb.write_hits 0 # DTB write hits
< system.cpu.itb.write_misses 0 # DTB write misses
< system.cpu.itb.write_accesses 0 # DTB write accesses
< system.cpu.itb.hits 0 # DTB hits
< system.cpu.itb.misses 0 # DTB misses
< system.cpu.itb.accesses 0 # DTB accesses
< system.cpu.workload.num_syscalls 130 # Number of system calls
< system.cpu.pwrStateResidencyTicks::ON 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 705851 # number of cpu cycles simulated
< system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
< system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
< system.cpu.committedInsts 201478 # Number of instructions committed
< system.cpu.committedOps 201478 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 201477 # Number of integer alu accesses
< system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
< system.cpu.num_func_calls 14627 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 30164 # number of instructions that are conditional controls
< system.cpu.num_int_insts 201477 # number of integer instructions
< system.cpu.num_fp_insts 0 # number of float instructions
< system.cpu.num_int_register_reads 266871 # number of times the integer registers were read
< system.cpu.num_int_register_writes 137624 # number of times the integer registers were written
< system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
< system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
< system.cpu.num_mem_refs 80078 # number of memory refs
< system.cpu.num_load_insts 46389 # Number of load instructions
< system.cpu.num_store_insts 33689 # Number of store instructions
< system.cpu.num_idle_cycles 0 # Number of idle cycles
< system.cpu.num_busy_cycles 705851 # Number of busy cycles
< system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0 # Percentage of idle cycles
< system.cpu.Branches 44791 # Number of branches fetched
< system.cpu.op_class::No_OpClass 132 0.07% 0.07% # Class of executed instruction
< system.cpu.op_class::IntAlu 120936 59.99% 60.05% # Class of executed instruction
< system.cpu.op_class::IntMult 297 0.15% 60.20% # Class of executed instruction
< system.cpu.op_class::IntDiv 166 0.08% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatAdd 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatCmp 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatCvt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatMult 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatMultAcc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatDiv 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatMisc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::FloatSqrt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdAdd 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdAddAcc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdAlu 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdCmp 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdCvt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdMisc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdMult 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdMultAcc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdShift 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdShiftAcc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdSqrt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatAdd 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatAlu 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatCmp 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatCvt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatDiv 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatMisc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatMult 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.28% # Class of executed instruction
< system.cpu.op_class::MemRead 46389 23.01% 83.29% # Class of executed instruction
< system.cpu.op_class::MemWrite 33689 16.71% 100.00% # Class of executed instruction
< system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
< system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
< system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
< system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
< system.cpu.op_class::total 201609 # Class of executed instruction
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 237.806291 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 79790 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 287 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 278.013937 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 237.806291 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.058058 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.058058 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 287 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.070068 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 160441 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 160441 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 46314 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 46314 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 33476 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 33476 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 79790 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 79790 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 79790 # number of overall hits
< system.cpu.dcache.overall_hits::total 79790 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 75 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 75 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 212 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 212 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 287 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 287 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 287 # number of overall misses
< system.cpu.dcache.overall_misses::total 287 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4725000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4725000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 13356000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 13356000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 18081000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 18081000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 18081000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 18081000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 46389 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 46389 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 80077 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 80077 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 80077 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 80077 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001617 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.001617 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006293 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.006293 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.003584 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.003584 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.003584 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.003584 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 75 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 75 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 212 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 212 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 287 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 287 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4650000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4650000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13144000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 13144000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17794000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 17794000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17794000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 17794000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001617 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001617 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006293 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006293 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.003584 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003584 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.003584 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 16 # number of replacements
< system.cpu.icache.tags.tagsinuse 467.242122 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 200748 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 862 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 232.886311 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 467.242122 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.228146 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.228146 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 846 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 632 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.413086 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 404082 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 404082 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 200748 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 200748 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 200748 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 200748 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 200748 # number of overall hits
< system.cpu.icache.overall_hits::total 200748 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 862 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 862 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 862 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 862 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 862 # number of overall misses
< system.cpu.icache.overall_misses::total 862 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 54307500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 54307500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 54307500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 54307500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 54307500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 54307500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 201610 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 201610 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 201610 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 201610 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 201610 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 201610 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004276 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.004276 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.004276 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.004276 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.004276 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.004276 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63001.740139 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 63001.740139 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 63001.740139 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 63001.740139 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 63001.740139 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 16 # number of writebacks
< system.cpu.icache.writebacks::total 16 # number of writebacks
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 862 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 862 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 862 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 862 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53445500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 53445500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53445500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 53445500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53445500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 53445500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004276 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.004276 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004276 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.004276 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62001.740139 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62001.740139 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62001.740139 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 62001.740139 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62001.740139 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 62001.740139 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 0 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 708.129693 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 16 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1149 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.013925 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 470.314864 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 237.814829 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.014353 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.007258 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.021610 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 1149 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 912 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.035065 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 10469 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 10469 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackClean_hits::writebacks 16 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 16 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 212 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 212 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 862 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 862 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 75 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 75 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 862 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 287 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 1149 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 862 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 287 # number of overall misses
< system.cpu.l2cache.overall_misses::total 1149 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12826000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 12826000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 52152000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 52152000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4537500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 4537500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 52152000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 17363500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 69515500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 52152000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 17363500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 69515500 # number of overall miss cycles
< system.cpu.l2cache.WritebackClean_accesses::writebacks 16 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 16 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 212 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 212 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 862 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 862 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 75 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 75 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 862 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 287 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 1149 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 862 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 287 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 1149 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.160093 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.160093 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.160093 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 60500.870322 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.160093 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 60500.870322 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 212 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 212 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 862 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 862 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 75 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 75 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 862 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 287 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 1149 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 862 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 287 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 1149 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10706000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10706000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43532000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43532000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3787500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3787500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43532000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14493500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 58025500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43532000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14493500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 58025500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.160093 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.160093 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.160093 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.870322 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 1165 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 16 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 937 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 16 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 212 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 212 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 862 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 75 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1740 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 574 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 2314 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 56192 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18368 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 74560 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 0 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 1149 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 1149 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 598500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 1293000 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer1.occupancy 430500 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
< system.membus.snoop_filter.tot_requests 1149 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
< system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.membus.pwrStateResidencyTicks::UNDEFINED 352925500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 937 # Transaction distribution
< system.membus.trans_dist::ReadExReq 212 # Transaction distribution
< system.membus.trans_dist::ReadExResp 212 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 937 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2298 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 2298 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73536 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 73536 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
< system.membus.snoop_fanout::samples 1149 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 1149 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 1149 # Request fanout histogram
< system.membus.reqLayer0.occupancy 1150000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
< system.membus.respLayer1.occupancy 5745000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 1.6 # Layer utilization (%)
---
> sim_seconds 0.000509
> sim_ticks 508585500
> final_tick 508585500
> sim_freq 1000000000000
> host_inst_rate 3721
> host_op_rate 3732
> host_tick_rate 7088392
> host_mem_usage 270008
> host_seconds 71.75
> sim_insts 266983
> sim_ops 267753
> system.voltage_domain.voltage 1
> system.clk_domain.clock 1000
> system.physmem.pwrStateResidencyTicks::UNDEFINED 508585500
> system.physmem.bytes_read::cpu.inst 60992
> system.physmem.bytes_read::cpu.data 30976
> system.physmem.bytes_read::total 91968
> system.physmem.bytes_inst_read::cpu.inst 60992
> system.physmem.bytes_inst_read::total 60992
> system.physmem.num_reads::cpu.inst 953
> system.physmem.num_reads::cpu.data 484
> system.physmem.num_reads::total 1437
> system.physmem.bw_read::cpu.inst 119924772
> system.physmem.bw_read::cpu.data 60906180
> system.physmem.bw_read::total 180830952
> system.physmem.bw_inst_read::cpu.inst 119924772
> system.physmem.bw_inst_read::total 119924772
> system.physmem.bw_total::cpu.inst 119924772
> system.physmem.bw_total::cpu.data 60906180
> system.physmem.bw_total::total 180830952
> system.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu_clk_domain.clock 500
> system.cpu.dtb.read_hits 0
> system.cpu.dtb.read_misses 0
> system.cpu.dtb.read_accesses 0
> system.cpu.dtb.write_hits 0
> system.cpu.dtb.write_misses 0
> system.cpu.dtb.write_accesses 0
> system.cpu.dtb.hits 0
> system.cpu.dtb.misses 0
> system.cpu.dtb.accesses 0
> system.cpu.itb.read_hits 0
> system.cpu.itb.read_misses 0
> system.cpu.itb.read_accesses 0
> system.cpu.itb.write_hits 0
> system.cpu.itb.write_misses 0
> system.cpu.itb.write_accesses 0
> system.cpu.itb.hits 0
> system.cpu.itb.misses 0
> system.cpu.itb.accesses 0
> system.cpu.workload.numSyscalls 182
> system.cpu.pwrStateResidencyTicks::ON 508585500
> system.cpu.numCycles 1017171
> system.cpu.numWorkItemsStarted 0
> system.cpu.numWorkItemsCompleted 0
> system.cpu.committedInsts 266983
> system.cpu.committedOps 267753
> system.cpu.num_int_alu_accesses 266336
> system.cpu.num_fp_alu_accesses 12
> system.cpu.num_vec_alu_accesses 0
> system.cpu.num_func_calls 15688
> system.cpu.num_conditional_control_insts 41227
> system.cpu.num_int_insts 266336
> system.cpu.num_fp_insts 12
> system.cpu.num_vec_insts 0
> system.cpu.num_int_register_reads 334534
> system.cpu.num_int_register_writes 178355
> system.cpu.num_fp_register_reads 12
> system.cpu.num_fp_register_writes 0
> system.cpu.num_vec_register_reads 0
> system.cpu.num_vec_register_writes 0
> system.cpu.num_mem_refs 109337
> system.cpu.num_load_insts 67806
> system.cpu.num_store_insts 41531
> system.cpu.num_idle_cycles 0
> system.cpu.num_busy_cycles 1017171
> system.cpu.not_idle_fraction 1
> system.cpu.idle_fraction 0
> system.cpu.Branches 56915
> system.cpu.op_class::No_OpClass 191 0.07% 0.07%
> system.cpu.op_class::IntAlu 157741 58.87% 58.94%
> system.cpu.op_class::IntMult 436 0.16% 59.11%
> system.cpu.op_class::IntDiv 230 0.09% 59.19%
> system.cpu.op_class::FloatAdd 0 0.00% 59.19%
> system.cpu.op_class::FloatCmp 0 0.00% 59.19%
> system.cpu.op_class::FloatCvt 0 0.00% 59.19%
> system.cpu.op_class::FloatMult 0 0.00% 59.19%
> system.cpu.op_class::FloatMultAcc 0 0.00% 59.19%
> system.cpu.op_class::FloatDiv 0 0.00% 59.19%
> system.cpu.op_class::FloatMisc 0 0.00% 59.19%
> system.cpu.op_class::FloatSqrt 0 0.00% 59.19%
> system.cpu.op_class::SimdAdd 0 0.00% 59.19%
> system.cpu.op_class::SimdAddAcc 0 0.00% 59.19%
> system.cpu.op_class::SimdAlu 0 0.00% 59.19%
> system.cpu.op_class::SimdCmp 0 0.00% 59.19%
> system.cpu.op_class::SimdCvt 0 0.00% 59.19%
> system.cpu.op_class::SimdMisc 0 0.00% 59.19%
> system.cpu.op_class::SimdMult 0 0.00% 59.19%
> system.cpu.op_class::SimdMultAcc 0 0.00% 59.19%
> system.cpu.op_class::SimdShift 0 0.00% 59.19%
> system.cpu.op_class::SimdShiftAcc 0 0.00% 59.19%
> system.cpu.op_class::SimdSqrt 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatAdd 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatAlu 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatCmp 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatCvt 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatDiv 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatMisc 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatMult 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.19%
> system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.19%
> system.cpu.op_class::MemRead 67806 25.31% 84.50%
> system.cpu.op_class::MemWrite 41519 15.50% 100.00%
> system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
> system.cpu.op_class::FloatMemWrite 12 0.00% 100.00%
> system.cpu.op_class::IprAccess 0 0.00% 100.00%
> system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
> system.cpu.op_class::total 267935
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.dcache.tags.replacements 0
> system.cpu.dcache.tags.tagsinuse 397.981012
> system.cpu.dcache.tags.total_refs 108853
> system.cpu.dcache.tags.sampled_refs 484
> system.cpu.dcache.tags.avg_refs 224.902893
> system.cpu.dcache.tags.warmup_cycle 0
> system.cpu.dcache.tags.occ_blocks::cpu.data 397.981012
> system.cpu.dcache.tags.occ_percent::cpu.data 0.097163
> system.cpu.dcache.tags.occ_percent::total 0.097163
> system.cpu.dcache.tags.occ_task_id_blocks::1024 484
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 14
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 7
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 463
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.118164
> system.cpu.dcache.tags.tag_accesses 219158
> system.cpu.dcache.tags.data_accesses 219158
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.dcache.ReadReq_hits::cpu.data 66769
> system.cpu.dcache.ReadReq_hits::total 66769
> system.cpu.dcache.WriteReq_hits::cpu.data 40527
> system.cpu.dcache.WriteReq_hits::total 40527
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 778
> system.cpu.dcache.LoadLockedReq_hits::total 778
> system.cpu.dcache.StoreCondReq_hits::cpu.data 779
> system.cpu.dcache.StoreCondReq_hits::total 779
> system.cpu.dcache.demand_hits::cpu.data 107296
> system.cpu.dcache.demand_hits::total 107296
> system.cpu.dcache.overall_hits::cpu.data 107296
> system.cpu.dcache.overall_hits::total 107296
> system.cpu.dcache.ReadReq_misses::cpu.data 258
> system.cpu.dcache.ReadReq_misses::total 258
> system.cpu.dcache.WriteReq_misses::cpu.data 225
> system.cpu.dcache.WriteReq_misses::total 225
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 1
> system.cpu.dcache.LoadLockedReq_misses::total 1
> system.cpu.dcache.demand_misses::cpu.data 483
> system.cpu.dcache.demand_misses::total 483
> system.cpu.dcache.overall_misses::cpu.data 483
> system.cpu.dcache.overall_misses::total 483
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 16254000
> system.cpu.dcache.ReadReq_miss_latency::total 16254000
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 14175000
> system.cpu.dcache.WriteReq_miss_latency::total 14175000
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63000
> system.cpu.dcache.LoadLockedReq_miss_latency::total 63000
> system.cpu.dcache.demand_miss_latency::cpu.data 30429000
> system.cpu.dcache.demand_miss_latency::total 30429000
> system.cpu.dcache.overall_miss_latency::cpu.data 30429000
> system.cpu.dcache.overall_miss_latency::total 30429000
> system.cpu.dcache.ReadReq_accesses::cpu.data 67027
> system.cpu.dcache.ReadReq_accesses::total 67027
> system.cpu.dcache.WriteReq_accesses::cpu.data 40752
> system.cpu.dcache.WriteReq_accesses::total 40752
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 779
> system.cpu.dcache.LoadLockedReq_accesses::total 779
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 779
> system.cpu.dcache.StoreCondReq_accesses::total 779
> system.cpu.dcache.demand_accesses::cpu.data 107779
> system.cpu.dcache.demand_accesses::total 107779
> system.cpu.dcache.overall_accesses::cpu.data 107779
> system.cpu.dcache.overall_accesses::total 107779
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003849
> system.cpu.dcache.ReadReq_miss_rate::total 0.003849
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005521
> system.cpu.dcache.WriteReq_miss_rate::total 0.005521
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001284
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001284
> system.cpu.dcache.demand_miss_rate::cpu.data 0.004481
> system.cpu.dcache.demand_miss_rate::total 0.004481
> system.cpu.dcache.overall_miss_rate::cpu.data 0.004481
> system.cpu.dcache.overall_miss_rate::total 0.004481
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63000
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000
> system.cpu.dcache.demand_avg_miss_latency::total 63000
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000
> system.cpu.dcache.overall_avg_miss_latency::total 63000
> system.cpu.dcache.blocked_cycles::no_mshrs 0
> system.cpu.dcache.blocked_cycles::no_targets 0
> system.cpu.dcache.blocked::no_mshrs 0
> system.cpu.dcache.blocked::no_targets 0
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
> system.cpu.dcache.avg_blocked_cycles::no_targets nan
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 258
> system.cpu.dcache.ReadReq_mshr_misses::total 258
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 225
> system.cpu.dcache.WriteReq_mshr_misses::total 225
> system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1
> system.cpu.dcache.LoadLockedReq_mshr_misses::total 1
> system.cpu.dcache.demand_mshr_misses::cpu.data 483
> system.cpu.dcache.demand_mshr_misses::total 483
> system.cpu.dcache.overall_mshr_misses::cpu.data 483
> system.cpu.dcache.overall_mshr_misses::total 483
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15996000
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 15996000
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13950000
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 13950000
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 62000
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29946000
> system.cpu.dcache.demand_mshr_miss_latency::total 29946000
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29946000
> system.cpu.dcache.overall_mshr_miss_latency::total 29946000
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003849
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003849
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005521
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005521
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001284
> system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001284
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004481
> system.cpu.dcache.demand_mshr_miss_rate::total 0.004481
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004481
> system.cpu.dcache.overall_mshr_miss_rate::total 0.004481
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 62000
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.icache.tags.replacements 44
> system.cpu.icache.tags.tagsinuse 603.393635
> system.cpu.icache.tags.total_refs 309176
> system.cpu.icache.tags.sampled_refs 955
> system.cpu.icache.tags.avg_refs 323.744503
> system.cpu.icache.tags.warmup_cycle 0
> system.cpu.icache.tags.occ_blocks::cpu.inst 603.393635
> system.cpu.icache.tags.occ_percent::cpu.inst 0.294626
> system.cpu.icache.tags.occ_percent::total 0.294626
> system.cpu.icache.tags.occ_task_id_blocks::1024 911
> system.cpu.icache.tags.age_task_id_blocks_1024::0 42
> system.cpu.icache.tags.age_task_id_blocks_1024::1 65
> system.cpu.icache.tags.age_task_id_blocks_1024::2 804
> system.cpu.icache.tags.occ_task_id_percent::1024 0.444824
> system.cpu.icache.tags.tag_accesses 621217
> system.cpu.icache.tags.data_accesses 621217
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.icache.ReadReq_hits::cpu.inst 309176
> system.cpu.icache.ReadReq_hits::total 309176
> system.cpu.icache.demand_hits::cpu.inst 309176
> system.cpu.icache.demand_hits::total 309176
> system.cpu.icache.overall_hits::cpu.inst 309176
> system.cpu.icache.overall_hits::total 309176
> system.cpu.icache.ReadReq_misses::cpu.inst 955
> system.cpu.icache.ReadReq_misses::total 955
> system.cpu.icache.demand_misses::cpu.inst 955
> system.cpu.icache.demand_misses::total 955
> system.cpu.icache.overall_misses::cpu.inst 955
> system.cpu.icache.overall_misses::total 955
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 60065500
> system.cpu.icache.ReadReq_miss_latency::total 60065500
> system.cpu.icache.demand_miss_latency::cpu.inst 60065500
> system.cpu.icache.demand_miss_latency::total 60065500
> system.cpu.icache.overall_miss_latency::cpu.inst 60065500
> system.cpu.icache.overall_miss_latency::total 60065500
> system.cpu.icache.ReadReq_accesses::cpu.inst 310131
> system.cpu.icache.ReadReq_accesses::total 310131
> system.cpu.icache.demand_accesses::cpu.inst 310131
> system.cpu.icache.demand_accesses::total 310131
> system.cpu.icache.overall_accesses::cpu.inst 310131
> system.cpu.icache.overall_accesses::total 310131
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003079
> system.cpu.icache.ReadReq_miss_rate::total 0.003079
> system.cpu.icache.demand_miss_rate::cpu.inst 0.003079
> system.cpu.icache.demand_miss_rate::total 0.003079
> system.cpu.icache.overall_miss_rate::cpu.inst 0.003079
> system.cpu.icache.overall_miss_rate::total 0.003079
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62895.811518
> system.cpu.icache.ReadReq_avg_miss_latency::total 62895.811518
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62895.811518
> system.cpu.icache.demand_avg_miss_latency::total 62895.811518
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62895.811518
> system.cpu.icache.overall_avg_miss_latency::total 62895.811518
> system.cpu.icache.blocked_cycles::no_mshrs 0
> system.cpu.icache.blocked_cycles::no_targets 0
> system.cpu.icache.blocked::no_mshrs 0
> system.cpu.icache.blocked::no_targets 0
> system.cpu.icache.avg_blocked_cycles::no_mshrs nan
> system.cpu.icache.avg_blocked_cycles::no_targets nan
> system.cpu.icache.writebacks::writebacks 44
> system.cpu.icache.writebacks::total 44
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 955
> system.cpu.icache.ReadReq_mshr_misses::total 955
> system.cpu.icache.demand_mshr_misses::cpu.inst 955
> system.cpu.icache.demand_mshr_misses::total 955
> system.cpu.icache.overall_mshr_misses::cpu.inst 955
> system.cpu.icache.overall_mshr_misses::total 955
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59110500
> system.cpu.icache.ReadReq_mshr_miss_latency::total 59110500
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59110500
> system.cpu.icache.demand_mshr_miss_latency::total 59110500
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59110500
> system.cpu.icache.overall_mshr_miss_latency::total 59110500
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.003079
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003079
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.003079
> system.cpu.icache.demand_mshr_miss_rate::total 0.003079
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.003079
> system.cpu.icache.overall_mshr_miss_rate::total 0.003079
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61895.811518
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61895.811518
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61895.811518
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61895.811518
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61895.811518
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61895.811518
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.l2cache.tags.replacements 0
> system.cpu.l2cache.tags.tagsinuse 1026.033062
> system.cpu.l2cache.tags.total_refs 46
> system.cpu.l2cache.tags.sampled_refs 1437
> system.cpu.l2cache.tags.avg_refs 0.032011
> system.cpu.l2cache.tags.warmup_cycle 0
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 628.042057
> system.cpu.l2cache.tags.occ_blocks::cpu.data 397.991005
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.019166
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.012146
> system.cpu.l2cache.tags.occ_percent::total 0.031312
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 1437
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 72
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1309
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.043854
> system.cpu.l2cache.tags.tag_accesses 13301
> system.cpu.l2cache.tags.data_accesses 13301
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.l2cache.WritebackClean_hits::writebacks 44
> system.cpu.l2cache.WritebackClean_hits::total 44
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2
> system.cpu.l2cache.ReadCleanReq_hits::total 2
> system.cpu.l2cache.demand_hits::cpu.inst 2
> system.cpu.l2cache.demand_hits::total 2
> system.cpu.l2cache.overall_hits::cpu.inst 2
> system.cpu.l2cache.overall_hits::total 2
> system.cpu.l2cache.ReadExReq_misses::cpu.data 225
> system.cpu.l2cache.ReadExReq_misses::total 225
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 953
> system.cpu.l2cache.ReadCleanReq_misses::total 953
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 259
> system.cpu.l2cache.ReadSharedReq_misses::total 259
> system.cpu.l2cache.demand_misses::cpu.inst 953
> system.cpu.l2cache.demand_misses::cpu.data 484
> system.cpu.l2cache.demand_misses::total 1437
> system.cpu.l2cache.overall_misses::cpu.inst 953
> system.cpu.l2cache.overall_misses::cpu.data 484
> system.cpu.l2cache.overall_misses::total 1437
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13612500
> system.cpu.l2cache.ReadExReq_miss_latency::total 13612500
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 57657000
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 57657000
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 15669500
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 15669500
> system.cpu.l2cache.demand_miss_latency::cpu.inst 57657000
> system.cpu.l2cache.demand_miss_latency::cpu.data 29282000
> system.cpu.l2cache.demand_miss_latency::total 86939000
> system.cpu.l2cache.overall_miss_latency::cpu.inst 57657000
> system.cpu.l2cache.overall_miss_latency::cpu.data 29282000
> system.cpu.l2cache.overall_miss_latency::total 86939000
> system.cpu.l2cache.WritebackClean_accesses::writebacks 44
> system.cpu.l2cache.WritebackClean_accesses::total 44
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 225
> system.cpu.l2cache.ReadExReq_accesses::total 225
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 955
> system.cpu.l2cache.ReadCleanReq_accesses::total 955
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 259
> system.cpu.l2cache.ReadSharedReq_accesses::total 259
> system.cpu.l2cache.demand_accesses::cpu.inst 955
> system.cpu.l2cache.demand_accesses::cpu.data 484
> system.cpu.l2cache.demand_accesses::total 1439
> system.cpu.l2cache.overall_accesses::cpu.inst 955
> system.cpu.l2cache.overall_accesses::cpu.data 484
> system.cpu.l2cache.overall_accesses::total 1439
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1
> system.cpu.l2cache.ReadExReq_miss_rate::total 1
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997906
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 1
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.demand_miss_rate::cpu.data 1
> system.cpu.l2cache.demand_miss_rate::total 0.998610
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.overall_miss_rate::cpu.data 1
> system.cpu.l2cache.overall_miss_rate::total 0.998610
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.524659
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.524659
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.524659
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500
> system.cpu.l2cache.demand_avg_miss_latency::total 60500.347947
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.524659
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500
> system.cpu.l2cache.overall_avg_miss_latency::total 60500.347947
> system.cpu.l2cache.blocked_cycles::no_mshrs 0
> system.cpu.l2cache.blocked_cycles::no_targets 0
> system.cpu.l2cache.blocked::no_mshrs 0
> system.cpu.l2cache.blocked::no_targets 0
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
> system.cpu.l2cache.avg_blocked_cycles::no_targets nan
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 225
> system.cpu.l2cache.ReadExReq_mshr_misses::total 225
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 953
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 953
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 259
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 259
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 953
> system.cpu.l2cache.demand_mshr_misses::cpu.data 484
> system.cpu.l2cache.demand_mshr_misses::total 1437
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 953
> system.cpu.l2cache.overall_mshr_misses::cpu.data 484
> system.cpu.l2cache.overall_mshr_misses::total 1437
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11362500
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11362500
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 48127000
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 48127000
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13079500
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13079500
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48127000
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 24442000
> system.cpu.l2cache.demand_mshr_miss_latency::total 72569000
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48127000
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 24442000
> system.cpu.l2cache.overall_mshr_miss_latency::total 72569000
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997906
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.998610
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997906
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.998610
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.524659
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.524659
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.524659
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.347947
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.524659
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.347947
> system.cpu.toL2Bus.snoop_filter.tot_requests 1483
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 44
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 508585500
> system.cpu.toL2Bus.trans_dist::ReadResp 1214
> system.cpu.toL2Bus.trans_dist::WritebackClean 44
> system.cpu.toL2Bus.trans_dist::ReadExReq 225
> system.cpu.toL2Bus.trans_dist::ReadExResp 225
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 955
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 259
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1954
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 968
> system.cpu.toL2Bus.pkt_count::total 2922
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63936
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 30976
> system.cpu.toL2Bus.pkt_size::total 94912
> system.cpu.toL2Bus.snoops 0
> system.cpu.toL2Bus.snoopTraffic 0
> system.cpu.toL2Bus.snoop_fanout::samples 1439
> system.cpu.toL2Bus.snoop_fanout::mean 0
> system.cpu.toL2Bus.snoop_fanout::stdev 0
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
> system.cpu.toL2Bus.snoop_fanout::0 1439 100.00% 100.00%
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
> system.cpu.toL2Bus.snoop_fanout::min_value 0
> system.cpu.toL2Bus.snoop_fanout::max_value 0
> system.cpu.toL2Bus.snoop_fanout::total 1439
> system.cpu.toL2Bus.reqLayer0.occupancy 785500
> system.cpu.toL2Bus.reqLayer0.utilization 0.2
> system.cpu.toL2Bus.respLayer0.occupancy 1432500
> system.cpu.toL2Bus.respLayer0.utilization 0.3
> system.cpu.toL2Bus.respLayer1.occupancy 726000
> system.cpu.toL2Bus.respLayer1.utilization 0.1
> system.membus.snoop_filter.tot_requests 1437
> system.membus.snoop_filter.hit_single_requests 0
> system.membus.snoop_filter.hit_multi_requests 0
> system.membus.snoop_filter.tot_snoops 0
> system.membus.snoop_filter.hit_single_snoops 0
> system.membus.snoop_filter.hit_multi_snoops 0
> system.membus.pwrStateResidencyTicks::UNDEFINED 508585500
> system.membus.trans_dist::ReadResp 1212
> system.membus.trans_dist::ReadExReq 225
> system.membus.trans_dist::ReadExResp 225
> system.membus.trans_dist::ReadSharedReq 1212
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2874
> system.membus.pkt_count::total 2874
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 91968
> system.membus.pkt_size::total 91968
> system.membus.snoops 0
> system.membus.snoopTraffic 0
> system.membus.snoop_fanout::samples 1437
> system.membus.snoop_fanout::mean 0
> system.membus.snoop_fanout::stdev 0
> system.membus.snoop_fanout::underflows 0 0.00% 0.00%
> system.membus.snoop_fanout::0 1437 100.00% 100.00%
> system.membus.snoop_fanout::1 0 0.00% 100.00%
> system.membus.snoop_fanout::overflows 0 0.00% 100.00%
> system.membus.snoop_fanout::min_value 0
> system.membus.snoop_fanout::max_value 0
> system.membus.snoop_fanout::total 1437
> system.membus.reqLayer0.occupancy 1437500
> system.membus.reqLayer0.utilization 0.3
> system.membus.respLayer1.occupancy 7185000
> system.membus.respLayer1.utilization 1.4