1{
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "membus": {
9 "point_of_coherency": true,
10 "system": "system",
11 "response_latency": 2,
12 "cxx_class": "CoherentXBar",
13 "forward_latency": 4,
14 "clk_domain": "system.clk_domain",
15 "width": 16,
16 "eventq_index": 0,
17 "default_p_state": "UNDEFINED",
18 "p_state_clk_gate_max": 1000000000000,
19 "master": {
20 "peer": [
21 "system.physmem.port"
22 ],
23 "role": "MASTER"
24 },
25 "type": "CoherentXBar",
26 "frontend_latency": 3,
27 "slave": {
28 "peer": [
29 "system.system_port",
30 "system.cpu.icache_port",
31 "system.cpu.dcache_port"
32 ],
33 "role": "SLAVE"
34 },
35 "p_state_clk_gate_min": 1000,
36 "snoop_filter": {
37 "name": "snoop_filter",
38 "system": "system",
39 "max_capacity": 8388608,
40 "eventq_index": 0,
41 "cxx_class": "SnoopFilter",
42 "path": "system.membus.snoop_filter",
43 "type": "SnoopFilter",
44 "lookup_latency": 1
45 },
46 "power_model": null,
47 "path": "system.membus",
48 "snoop_response_latency": 4,
49 "name": "membus",
50 "p_state_clk_gate_bins": 20,
51 "use_default_range": false
52 },
53 "symbolfile": "",
54 "readfile": "",
55 "thermal_model": null,
56 "cxx_class": "System",
57 "work_begin_cpu_id_exit": -1,
58 "load_offset": 0,
59 "work_begin_exit_count": 0,
60 "p_state_clk_gate_min": 1000,
61 "memories": [
62 "system.physmem"
63 ],
64 "work_begin_ckpt_count": 0,
65 "clk_domain": {
66 "name": "clk_domain",
67 "clock": [
68 1000
69 ],
70 "init_perf_level": 0,
71 "voltage_domain": "system.voltage_domain",
72 "eventq_index": 0,
73 "cxx_class": "SrcClockDomain",
74 "path": "system.clk_domain",
75 "type": "SrcClockDomain",
76 "domain_id": -1
77 },
78 "mem_ranges": [],
79 "eventq_index": 0,
80 "default_p_state": "UNDEFINED",
81 "p_state_clk_gate_max": 1000000000000,
82 "dvfs_handler": {
83 "enable": false,
84 "name": "dvfs_handler",
85 "sys_clk_domain": "system.clk_domain",
86 "transition_latency": 100000000,
87 "eventq_index": 0,
88 "cxx_class": "DVFSHandler",
89 "domains": [],
90 "path": "system.dvfs_handler",
91 "type": "DVFSHandler"
92 },
93 "work_end_exit_count": 0,
94 "type": "System",
95 "voltage_domain": {
96 "name": "voltage_domain",
97 "eventq_index": 0,
98 "voltage": [
99 "1.0"
100 ],
101 "cxx_class": "VoltageDomain",
102 "path": "system.voltage_domain",
103 "type": "VoltageDomain"
104 },
105 "cache_line_size": 64,
106 "boot_osflags": "a",
107 "system_port": {
108 "peer": "system.membus.slave[0]",
109 "role": "MASTER"
110 },
111 "physmem": {
112 "range": "0:134217727:0:0:0:0",
113 "latency": 30000,
114 "name": "physmem",
115 "p_state_clk_gate_min": 1000,
116 "eventq_index": 0,
117 "p_state_clk_gate_bins": 20,
118 "default_p_state": "UNDEFINED",
119 "kvm_map": true,
120 "clk_domain": "system.clk_domain",
121 "power_model": null,
122 "latency_var": 0,
123 "bandwidth": "73.000000",
124 "conf_table_reported": true,
125 "cxx_class": "SimpleMemory",
126 "p_state_clk_gate_max": 1000000000000,
127 "path": "system.physmem",
128 "null": false,
129 "type": "SimpleMemory",
130 "port": {
131 "peer": "system.membus.master[0]",
132 "role": "SLAVE"
133 },
134 "in_addr_map": true
135 },
136 "power_model": null,
137 "work_cpus_ckpt_count": 0,
138 "thermal_components": [],
139 "path": "system",
140 "cpu_clk_domain": {
141 "name": "cpu_clk_domain",
142 "clock": [
143 500
144 ],
145 "init_perf_level": 0,
146 "voltage_domain": "system.voltage_domain",
147 "eventq_index": 0,
148 "cxx_class": "SrcClockDomain",
149 "path": "system.cpu_clk_domain",
150 "type": "SrcClockDomain",
151 "domain_id": -1
152 },
153 "work_end_ckpt_count": 0,
154 "mem_mode": "atomic",
155 "name": "system",
156 "init_param": 0,
157 "p_state_clk_gate_bins": 20,
158 "load_addr_mask": 1099511627775,
159 "cpu": [
160 {
161 "do_statistics_insts": true,
162 "numThreads": 1,
163 "itb": {
164 "name": "itb",
165 "eventq_index": 0,
166 "cxx_class": "RiscvISA::TLB",
167 "path": "system.cpu.itb",
168 "type": "RiscvTLB",
169 "size": 64
170 },
171 "simulate_data_stalls": false,
172 "function_trace": false,
173 "do_checkpoint_insts": true,
174 "cxx_class": "AtomicSimpleCPU",
175 "max_loads_all_threads": 0,
176 "system": "system",
177 "clk_domain": "system.cpu_clk_domain",
178 "function_trace_start": 0,
179 "cpu_id": 0,
180 "width": 1,
181 "checker": null,
182 "eventq_index": 0,
183 "default_p_state": "UNDEFINED",
184 "p_state_clk_gate_max": 1000000000000,
185 "do_quiesce": true,
186 "type": "AtomicSimpleCPU",
187 "fastmem": false,
188 "profile": 0,
189 "icache_port": {
190 "peer": "system.membus.slave[1]",
191 "role": "MASTER"
192 },
193 "p_state_clk_gate_bins": 20,
194 "p_state_clk_gate_min": 1000,
195 "interrupts": [
196 {
197 "eventq_index": 0,
198 "path": "system.cpu.interrupts",
199 "type": "RiscvInterrupts",
200 "name": "interrupts",
201 "cxx_class": "RiscvISA::Interrupts"
202 }
203 ],
204 "dcache_port": {
205 "peer": "system.membus.slave[2]",
206 "role": "MASTER"
207 },
208 "socket_id": 0,
209 "power_model": null,
210 "max_insts_all_threads": 0,
211 "path": "system.cpu",
212 "max_loads_any_thread": 0,
213 "switched_out": false,
214 "workload": [
215 {
216 "uid": 100,
217 "pid": 100,
218 "kvmInSE": false,
219 "cxx_class": "LiveProcess",
220 "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest",
221 "drivers": [],
222 "system": "system",
223 "gid": 100,
224 "eventq_index": 0,
225 "env": [],
226 "input": "cin",
227 "ppid": 99,
228 "type": "LiveProcess",
229 "cwd": "",
230 "simpoint": 0,
231 "euid": 100,
232 "path": "system.cpu.workload",
233 "max_stack_size": 67108864,
234 "name": "workload",
235 "cmd": [
236 "insttest"
237 ],
238 "errout": "cerr",
239 "useArchPT": false,
240 "egid": 100,
241 "output": "cout"
242 }
243 ],
244 "name": "cpu",
245 "dtb": {
246 "name": "dtb",
247 "eventq_index": 0,
248 "cxx_class": "RiscvISA::TLB",
249 "path": "system.cpu.dtb",
250 "type": "RiscvTLB",
251 "size": 64
252 },
253 "simpoint_start_insts": [],
254 "max_insts_any_thread": 0,
255 "simulate_inst_stalls": false,
256 "progress_interval": 0,
257 "branchPred": null,
258 "isa": [
259 {
260 "eventq_index": 0,
261 "path": "system.cpu.isa",
262 "type": "RiscvISA",
263 "name": "isa",
264 "cxx_class": "RiscvISA::ISA"
265 }
266 ],
267 "tracer": {
268 "eventq_index": 0,
269 "path": "system.cpu.tracer",
270 "type": "ExeTracer",
271 "name": "tracer",
272 "cxx_class": "Trace::ExeTracer"
273 }
274 }
275 ],
276 "multi_thread": false,
277 "exit_on_work_items": false,
278 "work_item_id": -1,
279 "num_work_ids": 16
280 },
281 "time_sync_period": 100000000000,
282 "eventq_index": 0,
283 "time_sync_spin_threshold": 100000000,
284 "cxx_class": "Root",
285 "path": "root",
286 "time_sync_enable": false,
287 "type": "Root",
288 "full_system": false
289}
2 "name": null,
3 "sim_quantum": 0,
4 "system": {
5 "kernel": "",
6 "mmap_using_noreserve": false,
7 "kernel_addr_check": true,
8 "membus": {
9 "point_of_coherency": true,
10 "system": "system",
11 "response_latency": 2,
12 "cxx_class": "CoherentXBar",
13 "forward_latency": 4,
14 "clk_domain": "system.clk_domain",
15 "width": 16,
16 "eventq_index": 0,
17 "default_p_state": "UNDEFINED",
18 "p_state_clk_gate_max": 1000000000000,
19 "master": {
20 "peer": [
21 "system.physmem.port"
22 ],
23 "role": "MASTER"
24 },
25 "type": "CoherentXBar",
26 "frontend_latency": 3,
27 "slave": {
28 "peer": [
29 "system.system_port",
30 "system.cpu.icache_port",
31 "system.cpu.dcache_port"
32 ],
33 "role": "SLAVE"
34 },
35 "p_state_clk_gate_min": 1000,
36 "snoop_filter": {
37 "name": "snoop_filter",
38 "system": "system",
39 "max_capacity": 8388608,
40 "eventq_index": 0,
41 "cxx_class": "SnoopFilter",
42 "path": "system.membus.snoop_filter",
43 "type": "SnoopFilter",
44 "lookup_latency": 1
45 },
46 "power_model": null,
47 "path": "system.membus",
48 "snoop_response_latency": 4,
49 "name": "membus",
50 "p_state_clk_gate_bins": 20,
51 "use_default_range": false
52 },
53 "symbolfile": "",
54 "readfile": "",
55 "thermal_model": null,
56 "cxx_class": "System",
57 "work_begin_cpu_id_exit": -1,
58 "load_offset": 0,
59 "work_begin_exit_count": 0,
60 "p_state_clk_gate_min": 1000,
61 "memories": [
62 "system.physmem"
63 ],
64 "work_begin_ckpt_count": 0,
65 "clk_domain": {
66 "name": "clk_domain",
67 "clock": [
68 1000
69 ],
70 "init_perf_level": 0,
71 "voltage_domain": "system.voltage_domain",
72 "eventq_index": 0,
73 "cxx_class": "SrcClockDomain",
74 "path": "system.clk_domain",
75 "type": "SrcClockDomain",
76 "domain_id": -1
77 },
78 "mem_ranges": [],
79 "eventq_index": 0,
80 "default_p_state": "UNDEFINED",
81 "p_state_clk_gate_max": 1000000000000,
82 "dvfs_handler": {
83 "enable": false,
84 "name": "dvfs_handler",
85 "sys_clk_domain": "system.clk_domain",
86 "transition_latency": 100000000,
87 "eventq_index": 0,
88 "cxx_class": "DVFSHandler",
89 "domains": [],
90 "path": "system.dvfs_handler",
91 "type": "DVFSHandler"
92 },
93 "work_end_exit_count": 0,
94 "type": "System",
95 "voltage_domain": {
96 "name": "voltage_domain",
97 "eventq_index": 0,
98 "voltage": [
99 "1.0"
100 ],
101 "cxx_class": "VoltageDomain",
102 "path": "system.voltage_domain",
103 "type": "VoltageDomain"
104 },
105 "cache_line_size": 64,
106 "boot_osflags": "a",
107 "system_port": {
108 "peer": "system.membus.slave[0]",
109 "role": "MASTER"
110 },
111 "physmem": {
112 "range": "0:134217727:0:0:0:0",
113 "latency": 30000,
114 "name": "physmem",
115 "p_state_clk_gate_min": 1000,
116 "eventq_index": 0,
117 "p_state_clk_gate_bins": 20,
118 "default_p_state": "UNDEFINED",
119 "kvm_map": true,
120 "clk_domain": "system.clk_domain",
121 "power_model": null,
122 "latency_var": 0,
123 "bandwidth": "73.000000",
124 "conf_table_reported": true,
125 "cxx_class": "SimpleMemory",
126 "p_state_clk_gate_max": 1000000000000,
127 "path": "system.physmem",
128 "null": false,
129 "type": "SimpleMemory",
130 "port": {
131 "peer": "system.membus.master[0]",
132 "role": "SLAVE"
133 },
134 "in_addr_map": true
135 },
136 "power_model": null,
137 "work_cpus_ckpt_count": 0,
138 "thermal_components": [],
139 "path": "system",
140 "cpu_clk_domain": {
141 "name": "cpu_clk_domain",
142 "clock": [
143 500
144 ],
145 "init_perf_level": 0,
146 "voltage_domain": "system.voltage_domain",
147 "eventq_index": 0,
148 "cxx_class": "SrcClockDomain",
149 "path": "system.cpu_clk_domain",
150 "type": "SrcClockDomain",
151 "domain_id": -1
152 },
153 "work_end_ckpt_count": 0,
154 "mem_mode": "atomic",
155 "name": "system",
156 "init_param": 0,
157 "p_state_clk_gate_bins": 20,
158 "load_addr_mask": 1099511627775,
159 "cpu": [
160 {
161 "do_statistics_insts": true,
162 "numThreads": 1,
163 "itb": {
164 "name": "itb",
165 "eventq_index": 0,
166 "cxx_class": "RiscvISA::TLB",
167 "path": "system.cpu.itb",
168 "type": "RiscvTLB",
169 "size": 64
170 },
171 "simulate_data_stalls": false,
172 "function_trace": false,
173 "do_checkpoint_insts": true,
174 "cxx_class": "AtomicSimpleCPU",
175 "max_loads_all_threads": 0,
176 "system": "system",
177 "clk_domain": "system.cpu_clk_domain",
178 "function_trace_start": 0,
179 "cpu_id": 0,
180 "width": 1,
181 "checker": null,
182 "eventq_index": 0,
183 "default_p_state": "UNDEFINED",
184 "p_state_clk_gate_max": 1000000000000,
185 "do_quiesce": true,
186 "type": "AtomicSimpleCPU",
187 "fastmem": false,
188 "profile": 0,
189 "icache_port": {
190 "peer": "system.membus.slave[1]",
191 "role": "MASTER"
192 },
193 "p_state_clk_gate_bins": 20,
194 "p_state_clk_gate_min": 1000,
195 "interrupts": [
196 {
197 "eventq_index": 0,
198 "path": "system.cpu.interrupts",
199 "type": "RiscvInterrupts",
200 "name": "interrupts",
201 "cxx_class": "RiscvISA::Interrupts"
202 }
203 ],
204 "dcache_port": {
205 "peer": "system.membus.slave[2]",
206 "role": "MASTER"
207 },
208 "socket_id": 0,
209 "power_model": null,
210 "max_insts_all_threads": 0,
211 "path": "system.cpu",
212 "max_loads_any_thread": 0,
213 "switched_out": false,
214 "workload": [
215 {
216 "uid": 100,
217 "pid": 100,
218 "kvmInSE": false,
219 "cxx_class": "LiveProcess",
220 "executable": "/z/powerjg/gem5-upstream/tests/test-progs/insttest/bin/riscv/linux-rv64i/insttest",
221 "drivers": [],
222 "system": "system",
223 "gid": 100,
224 "eventq_index": 0,
225 "env": [],
226 "input": "cin",
227 "ppid": 99,
228 "type": "LiveProcess",
229 "cwd": "",
230 "simpoint": 0,
231 "euid": 100,
232 "path": "system.cpu.workload",
233 "max_stack_size": 67108864,
234 "name": "workload",
235 "cmd": [
236 "insttest"
237 ],
238 "errout": "cerr",
239 "useArchPT": false,
240 "egid": 100,
241 "output": "cout"
242 }
243 ],
244 "name": "cpu",
245 "dtb": {
246 "name": "dtb",
247 "eventq_index": 0,
248 "cxx_class": "RiscvISA::TLB",
249 "path": "system.cpu.dtb",
250 "type": "RiscvTLB",
251 "size": 64
252 },
253 "simpoint_start_insts": [],
254 "max_insts_any_thread": 0,
255 "simulate_inst_stalls": false,
256 "progress_interval": 0,
257 "branchPred": null,
258 "isa": [
259 {
260 "eventq_index": 0,
261 "path": "system.cpu.isa",
262 "type": "RiscvISA",
263 "name": "isa",
264 "cxx_class": "RiscvISA::ISA"
265 }
266 ],
267 "tracer": {
268 "eventq_index": 0,
269 "path": "system.cpu.tracer",
270 "type": "ExeTracer",
271 "name": "tracer",
272 "cxx_class": "Trace::ExeTracer"
273 }
274 }
275 ],
276 "multi_thread": false,
277 "exit_on_work_items": false,
278 "work_item_id": -1,
279 "num_work_ids": 16
280 },
281 "time_sync_period": 100000000000,
282 "eventq_index": 0,
283 "time_sync_spin_threshold": 100000000,
284 "cxx_class": "Root",
285 "path": "root",
286 "time_sync_enable": false,
287 "type": "Root",
288 "full_system": false
289}