3sim_seconds 0.000257 # Number of seconds simulated 4sim_ticks 257396500 # Number of ticks simulated 5final_tick 257396500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 23064 # Simulator instruction rate (inst/s) 8host_op_rate 23064 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 29446323 # Simulator tick rate (ticks/s) 10host_mem_usage 244684 # Number of bytes of host memory used 11host_seconds 8.74 # Real time elapsed on the host 12sim_insts 201609 # Number of instructions simulated 13sim_ops 201609 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 70720 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 18880 # Number of bytes read from this memory 19system.physmem.bytes_read::total 89600 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 70720 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 70720 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 1105 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 295 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 1400 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 274751211 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 73349871 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 348101081 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 274751211 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 274751211 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 274751211 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 73349871 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 348101081 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 1400 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 1400 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 89600 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 89600 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 195 # Per bank write bursts 46system.physmem.perBankRdBursts::1 221 # Per bank write bursts 47system.physmem.perBankRdBursts::2 35 # Per bank write bursts 48system.physmem.perBankRdBursts::3 87 # Per bank write bursts 49system.physmem.perBankRdBursts::4 141 # Per bank write bursts 50system.physmem.perBankRdBursts::5 86 # Per bank write bursts 51system.physmem.perBankRdBursts::6 5 # Per bank write bursts 52system.physmem.perBankRdBursts::7 106 # Per bank write bursts 53system.physmem.perBankRdBursts::8 78 # Per bank write bursts 54system.physmem.perBankRdBursts::9 96 # Per bank write bursts 55system.physmem.perBankRdBursts::10 80 # Per bank write bursts 56system.physmem.perBankRdBursts::11 128 # Per bank write bursts 57system.physmem.perBankRdBursts::12 40 # Per bank write bursts 58system.physmem.perBankRdBursts::13 27 # Per bank write bursts 59system.physmem.perBankRdBursts::14 51 # Per bank write bursts 60system.physmem.perBankRdBursts::15 24 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 257156500 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 1400 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 1337 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 60 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 274 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 323.270073 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 216.910663 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 283.246990 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 71 25.91% 25.91% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 59 21.53% 47.45% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 52 18.98% 66.42% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 26 9.49% 75.91% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 14 5.11% 81.02% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 23 8.39% 89.42% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 8 2.92% 92.34% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 1.09% 93.43% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 18 6.57% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 274 # Bytes accessed per row activation 204system.physmem.totQLat 19864500 # Total ticks spent queuing 205system.physmem.totMemAccLat 46114500 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 7000000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 14188.93 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 32938.93 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 348.10 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 348.10 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 2.72 # Data bus utilization in percentage 216system.physmem.busUtilRead 2.72 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 1124 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 80.29 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 183683.21 # Average gap between requests 225system.physmem.pageHitRate 80.29 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 1299480 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 690690 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 6254640 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 20283120.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 14953950 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 477120 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 94483770 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 6205440 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 144648210 # Total energy per rank (pJ) 237system.physmem_0.averagePower 561.964316 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 223185500 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states 240system.physmem_0.memoryStateTime::REF 8580000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 16154500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 25250500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 207201500 # Time in different power states 245system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 349140 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 3741360 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 14751360.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 9433500 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 3408960 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 53834790 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 13144800 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 18682440 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 118017510 # Total energy per rank (pJ) 256system.physmem_1.averagePower 458.502938 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 227632750 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 8194250 # Time in different power states 259system.physmem_1.memoryStateTime::REF 6246000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 75541750 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 34227000 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 15120250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 118067250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 58095 # Number of BP lookups 266system.cpu.branchPred.condPredicted 37339 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 4808 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 47628 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 25748 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 54.060637 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 9498 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 5462 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 4036 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 2282 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.write_accesses 0 # DTB write accesses 285system.cpu.dtb.hits 0 # DTB hits 286system.cpu.dtb.misses 0 # DTB misses 287system.cpu.dtb.accesses 0 # DTB accesses 288system.cpu.itb.read_hits 0 # DTB read hits 289system.cpu.itb.read_misses 0 # DTB read misses 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 130 # Number of system calls 298system.cpu.pwrStateResidencyTicks::ON 257396500 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 514793 # number of cpu cycles simulated 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.committedInsts 201609 # Number of instructions committed 303system.cpu.committedOps 201609 # Number of ops (including micro ops) committed 304system.cpu.discardedOps 12686 # Number of ops (including micro ops) which were discarded before commit 305system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 306system.cpu.cpi 2.553423 # CPI: cycles per instruction 307system.cpu.ipc 0.391631 # IPC: instructions per cycle 308system.cpu.op_class_0::No_OpClass 132 0.07% 0.07% # Class of committed instruction 309system.cpu.op_class_0::IntAlu 120936 59.99% 60.05% # Class of committed instruction 310system.cpu.op_class_0::IntMult 297 0.15% 60.20% # Class of committed instruction 311system.cpu.op_class_0::IntDiv 166 0.08% 60.28% # Class of committed instruction 312system.cpu.op_class_0::FloatAdd 0 0.00% 60.28% # Class of committed instruction 313system.cpu.op_class_0::FloatCmp 0 0.00% 60.28% # Class of committed instruction 314system.cpu.op_class_0::FloatCvt 0 0.00% 60.28% # Class of committed instruction 315system.cpu.op_class_0::FloatMult 0 0.00% 60.28% # Class of committed instruction 316system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.28% # Class of committed instruction 317system.cpu.op_class_0::FloatDiv 0 0.00% 60.28% # Class of committed instruction 318system.cpu.op_class_0::FloatMisc 0 0.00% 60.28% # Class of committed instruction 319system.cpu.op_class_0::FloatSqrt 0 0.00% 60.28% # Class of committed instruction 320system.cpu.op_class_0::SimdAdd 0 0.00% 60.28% # Class of committed instruction 321system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.28% # Class of committed instruction 322system.cpu.op_class_0::SimdAlu 0 0.00% 60.28% # Class of committed instruction 323system.cpu.op_class_0::SimdCmp 0 0.00% 60.28% # Class of committed instruction 324system.cpu.op_class_0::SimdCvt 0 0.00% 60.28% # Class of committed instruction 325system.cpu.op_class_0::SimdMisc 0 0.00% 60.28% # Class of committed instruction 326system.cpu.op_class_0::SimdMult 0 0.00% 60.28% # Class of committed instruction 327system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.28% # Class of committed instruction 328system.cpu.op_class_0::SimdShift 0 0.00% 60.28% # Class of committed instruction 329system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.28% # Class of committed instruction 330system.cpu.op_class_0::SimdSqrt 0 0.00% 60.28% # Class of committed instruction 331system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.28% # Class of committed instruction 332system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.28% # Class of committed instruction 333system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.28% # Class of committed instruction 334system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.28% # Class of committed instruction 335system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.28% # Class of committed instruction 336system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.28% # Class of committed instruction 337system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.28% # Class of committed instruction 338system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.28% # Class of committed instruction 339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.28% # Class of committed instruction 340system.cpu.op_class_0::MemRead 46389 23.01% 83.29% # Class of committed instruction 341system.cpu.op_class_0::MemWrite 33689 16.71% 100.00% # Class of committed instruction 342system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 343system.cpu.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 201609 # Class of committed instruction 347system.cpu.tickCycles 299839 # Number of cycles that the object actually ticked 348system.cpu.idleCycles 214954 # Total number of cycles that the object has spent stopped 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states 350system.cpu.dcache.tags.replacements 0 # number of replacements 351system.cpu.dcache.tags.tagsinuse 237.251323 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 81600 # Total number of references to valid blocks. 353system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks. 354system.cpu.dcache.tags.avg_refs 275.675676 # Average number of references to valid blocks. 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 356system.cpu.dcache.tags.occ_blocks::cpu.data 237.251323 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.057923 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.057923 # Average percentage of cache occupancy 359system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 362system.cpu.dcache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 363system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id 364system.cpu.dcache.tags.tag_accesses 164496 # Number of tag accesses 365system.cpu.dcache.tags.data_accesses 164496 # Number of data accesses 366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states 367system.cpu.dcache.ReadReq_hits::cpu.data 48321 # number of ReadReq hits 368system.cpu.dcache.ReadReq_hits::total 48321 # number of ReadReq hits 369system.cpu.dcache.WriteReq_hits::cpu.data 33279 # number of WriteReq hits 370system.cpu.dcache.WriteReq_hits::total 33279 # number of WriteReq hits 371system.cpu.dcache.demand_hits::cpu.data 81600 # number of demand (read+write) hits 372system.cpu.dcache.demand_hits::total 81600 # number of demand (read+write) hits 373system.cpu.dcache.overall_hits::cpu.data 81600 # number of overall hits 374system.cpu.dcache.overall_hits::total 81600 # number of overall hits 375system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 376system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses 377system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses 378system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses 379system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses 380system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses 381system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses 382system.cpu.dcache.overall_misses::total 500 # number of overall misses 383system.cpu.dcache.ReadReq_miss_latency::cpu.data 8843000 # number of ReadReq miss cycles 384system.cpu.dcache.ReadReq_miss_latency::total 8843000 # number of ReadReq miss cycles 385system.cpu.dcache.WriteReq_miss_latency::cpu.data 32769500 # number of WriteReq miss cycles 386system.cpu.dcache.WriteReq_miss_latency::total 32769500 # number of WriteReq miss cycles 387system.cpu.dcache.demand_miss_latency::cpu.data 41612500 # number of demand (read+write) miss cycles 388system.cpu.dcache.demand_miss_latency::total 41612500 # number of demand (read+write) miss cycles 389system.cpu.dcache.overall_miss_latency::cpu.data 41612500 # number of overall miss cycles 390system.cpu.dcache.overall_miss_latency::total 41612500 # number of overall miss cycles 391system.cpu.dcache.ReadReq_accesses::cpu.data 48412 # number of ReadReq accesses(hits+misses) 392system.cpu.dcache.ReadReq_accesses::total 48412 # number of ReadReq accesses(hits+misses) 393system.cpu.dcache.WriteReq_accesses::cpu.data 33688 # number of WriteReq accesses(hits+misses) 394system.cpu.dcache.WriteReq_accesses::total 33688 # number of WriteReq accesses(hits+misses) 395system.cpu.dcache.demand_accesses::cpu.data 82100 # number of demand (read+write) accesses 396system.cpu.dcache.demand_accesses::total 82100 # number of demand (read+write) accesses 397system.cpu.dcache.overall_accesses::cpu.data 82100 # number of overall (read+write) accesses 398system.cpu.dcache.overall_accesses::total 82100 # number of overall (read+write) accesses 399system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001880 # miss rate for ReadReq accesses 400system.cpu.dcache.ReadReq_miss_rate::total 0.001880 # miss rate for ReadReq accesses 401system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012141 # miss rate for WriteReq accesses 402system.cpu.dcache.WriteReq_miss_rate::total 0.012141 # miss rate for WriteReq accesses 403system.cpu.dcache.demand_miss_rate::cpu.data 0.006090 # miss rate for demand accesses 404system.cpu.dcache.demand_miss_rate::total 0.006090 # miss rate for demand accesses 405system.cpu.dcache.overall_miss_rate::cpu.data 0.006090 # miss rate for overall accesses 406system.cpu.dcache.overall_miss_rate::total 0.006090 # miss rate for overall accesses 407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 97175.824176 # average ReadReq miss latency 408system.cpu.dcache.ReadReq_avg_miss_latency::total 97175.824176 # average ReadReq miss latency 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80121.026895 # average WriteReq miss latency 410system.cpu.dcache.WriteReq_avg_miss_latency::total 80121.026895 # average WriteReq miss latency 411system.cpu.dcache.demand_avg_miss_latency::cpu.data 83225 # average overall miss latency 412system.cpu.dcache.demand_avg_miss_latency::total 83225 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::cpu.data 83225 # average overall miss latency 414system.cpu.dcache.overall_avg_miss_latency::total 83225 # average overall miss latency 415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 422system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 423system.cpu.dcache.WriteReq_mshr_hits::cpu.data 198 # number of WriteReq MSHR hits 424system.cpu.dcache.WriteReq_mshr_hits::total 198 # number of WriteReq MSHR hits 425system.cpu.dcache.demand_mshr_hits::cpu.data 204 # number of demand (read+write) MSHR hits 426system.cpu.dcache.demand_mshr_hits::total 204 # number of demand (read+write) MSHR hits 427system.cpu.dcache.overall_mshr_hits::cpu.data 204 # number of overall MSHR hits 428system.cpu.dcache.overall_mshr_hits::total 204 # number of overall MSHR hits 429system.cpu.dcache.ReadReq_mshr_misses::cpu.data 85 # number of ReadReq MSHR misses 430system.cpu.dcache.ReadReq_mshr_misses::total 85 # number of ReadReq MSHR misses 431system.cpu.dcache.WriteReq_mshr_misses::cpu.data 211 # number of WriteReq MSHR misses 432system.cpu.dcache.WriteReq_mshr_misses::total 211 # number of WriteReq MSHR misses 433system.cpu.dcache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses 434system.cpu.dcache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 435system.cpu.dcache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses 436system.cpu.dcache.overall_mshr_misses::total 296 # number of overall MSHR misses 437system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8161000 # number of ReadReq MSHR miss cycles 438system.cpu.dcache.ReadReq_mshr_miss_latency::total 8161000 # number of ReadReq MSHR miss cycles 439system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16932000 # number of WriteReq MSHR miss cycles 440system.cpu.dcache.WriteReq_mshr_miss_latency::total 16932000 # number of WriteReq MSHR miss cycles 441system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25093000 # number of demand (read+write) MSHR miss cycles 442system.cpu.dcache.demand_mshr_miss_latency::total 25093000 # number of demand (read+write) MSHR miss cycles 443system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25093000 # number of overall MSHR miss cycles 444system.cpu.dcache.overall_mshr_miss_latency::total 25093000 # number of overall MSHR miss cycles 445system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001756 # mshr miss rate for ReadReq accesses 446system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001756 # mshr miss rate for ReadReq accesses 447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006263 # mshr miss rate for WriteReq accesses 448system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006263 # mshr miss rate for WriteReq accesses 449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for demand accesses 450system.cpu.dcache.demand_mshr_miss_rate::total 0.003605 # mshr miss rate for demand accesses 451system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003605 # mshr miss rate for overall accesses 452system.cpu.dcache.overall_mshr_miss_rate::total 0.003605 # mshr miss rate for overall accesses 453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96011.764706 # average ReadReq mshr miss latency 454system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96011.764706 # average ReadReq mshr miss latency 455system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80246.445498 # average WriteReq mshr miss latency 456system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80246.445498 # average WriteReq mshr miss latency 457system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency 458system.cpu.dcache.demand_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency 459system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84773.648649 # average overall mshr miss latency 460system.cpu.dcache.overall_avg_mshr_miss_latency::total 84773.648649 # average overall mshr miss latency 461system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states 462system.cpu.icache.tags.replacements 44 # number of replacements 463system.cpu.icache.tags.tagsinuse 581.971054 # Cycle average of tags in use 464system.cpu.icache.tags.total_refs 86953 # Total number of references to valid blocks. 465system.cpu.icache.tags.sampled_refs 1105 # Sample count of references to valid blocks. 466system.cpu.icache.tags.avg_refs 78.690498 # Average number of references to valid blocks. 467system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 468system.cpu.icache.tags.occ_blocks::cpu.inst 581.971054 # Average occupied blocks per requestor 469system.cpu.icache.tags.occ_percent::cpu.inst 0.284166 # Average percentage of cache occupancy 470system.cpu.icache.tags.occ_percent::total 0.284166 # Average percentage of cache occupancy 471system.cpu.icache.tags.occ_task_id_blocks::1024 1061 # Occupied blocks per task id 472system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 473system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id 474system.cpu.icache.tags.age_task_id_blocks_1024::2 746 # Occupied blocks per task id 475system.cpu.icache.tags.occ_task_id_percent::1024 0.518066 # Percentage of cache occupancy per task id 476system.cpu.icache.tags.tag_accesses 177221 # Number of tag accesses 477system.cpu.icache.tags.data_accesses 177221 # Number of data accesses 478system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states 479system.cpu.icache.ReadReq_hits::cpu.inst 86953 # number of ReadReq hits 480system.cpu.icache.ReadReq_hits::total 86953 # number of ReadReq hits 481system.cpu.icache.demand_hits::cpu.inst 86953 # number of demand (read+write) hits 482system.cpu.icache.demand_hits::total 86953 # number of demand (read+write) hits 483system.cpu.icache.overall_hits::cpu.inst 86953 # number of overall hits 484system.cpu.icache.overall_hits::total 86953 # number of overall hits 485system.cpu.icache.ReadReq_misses::cpu.inst 1105 # number of ReadReq misses 486system.cpu.icache.ReadReq_misses::total 1105 # number of ReadReq misses 487system.cpu.icache.demand_misses::cpu.inst 1105 # number of demand (read+write) misses 488system.cpu.icache.demand_misses::total 1105 # number of demand (read+write) misses 489system.cpu.icache.overall_misses::cpu.inst 1105 # number of overall misses 490system.cpu.icache.overall_misses::total 1105 # number of overall misses 491system.cpu.icache.ReadReq_miss_latency::cpu.inst 95598500 # number of ReadReq miss cycles 492system.cpu.icache.ReadReq_miss_latency::total 95598500 # number of ReadReq miss cycles 493system.cpu.icache.demand_miss_latency::cpu.inst 95598500 # number of demand (read+write) miss cycles 494system.cpu.icache.demand_miss_latency::total 95598500 # number of demand (read+write) miss cycles 495system.cpu.icache.overall_miss_latency::cpu.inst 95598500 # number of overall miss cycles 496system.cpu.icache.overall_miss_latency::total 95598500 # number of overall miss cycles 497system.cpu.icache.ReadReq_accesses::cpu.inst 88058 # number of ReadReq accesses(hits+misses) 498system.cpu.icache.ReadReq_accesses::total 88058 # number of ReadReq accesses(hits+misses) 499system.cpu.icache.demand_accesses::cpu.inst 88058 # number of demand (read+write) accesses 500system.cpu.icache.demand_accesses::total 88058 # number of demand (read+write) accesses 501system.cpu.icache.overall_accesses::cpu.inst 88058 # number of overall (read+write) accesses 502system.cpu.icache.overall_accesses::total 88058 # number of overall (read+write) accesses 503system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.012549 # miss rate for ReadReq accesses 504system.cpu.icache.ReadReq_miss_rate::total 0.012549 # miss rate for ReadReq accesses 505system.cpu.icache.demand_miss_rate::cpu.inst 0.012549 # miss rate for demand accesses 506system.cpu.icache.demand_miss_rate::total 0.012549 # miss rate for demand accesses 507system.cpu.icache.overall_miss_rate::cpu.inst 0.012549 # miss rate for overall accesses 508system.cpu.icache.overall_miss_rate::total 0.012549 # miss rate for overall accesses 509system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 86514.479638 # average ReadReq miss latency 510system.cpu.icache.ReadReq_avg_miss_latency::total 86514.479638 # average ReadReq miss latency 511system.cpu.icache.demand_avg_miss_latency::cpu.inst 86514.479638 # average overall miss latency 512system.cpu.icache.demand_avg_miss_latency::total 86514.479638 # average overall miss latency 513system.cpu.icache.overall_avg_miss_latency::cpu.inst 86514.479638 # average overall miss latency 514system.cpu.icache.overall_avg_miss_latency::total 86514.479638 # average overall miss latency 515system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 516system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 517system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 518system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 519system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 520system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 521system.cpu.icache.writebacks::writebacks 44 # number of writebacks 522system.cpu.icache.writebacks::total 44 # number of writebacks 523system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1105 # number of ReadReq MSHR misses 524system.cpu.icache.ReadReq_mshr_misses::total 1105 # number of ReadReq MSHR misses 525system.cpu.icache.demand_mshr_misses::cpu.inst 1105 # number of demand (read+write) MSHR misses 526system.cpu.icache.demand_mshr_misses::total 1105 # number of demand (read+write) MSHR misses 527system.cpu.icache.overall_mshr_misses::cpu.inst 1105 # number of overall MSHR misses 528system.cpu.icache.overall_mshr_misses::total 1105 # number of overall MSHR misses 529system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 94493500 # number of ReadReq MSHR miss cycles 530system.cpu.icache.ReadReq_mshr_miss_latency::total 94493500 # number of ReadReq MSHR miss cycles 531system.cpu.icache.demand_mshr_miss_latency::cpu.inst 94493500 # number of demand (read+write) MSHR miss cycles 532system.cpu.icache.demand_mshr_miss_latency::total 94493500 # number of demand (read+write) MSHR miss cycles 533system.cpu.icache.overall_mshr_miss_latency::cpu.inst 94493500 # number of overall MSHR miss cycles 534system.cpu.icache.overall_mshr_miss_latency::total 94493500 # number of overall MSHR miss cycles 535system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for ReadReq accesses 536system.cpu.icache.ReadReq_mshr_miss_rate::total 0.012549 # mshr miss rate for ReadReq accesses 537system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for demand accesses 538system.cpu.icache.demand_mshr_miss_rate::total 0.012549 # mshr miss rate for demand accesses 539system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.012549 # mshr miss rate for overall accesses 540system.cpu.icache.overall_mshr_miss_rate::total 0.012549 # mshr miss rate for overall accesses 541system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85514.479638 # average ReadReq mshr miss latency 542system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85514.479638 # average ReadReq mshr miss latency 543system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85514.479638 # average overall mshr miss latency 544system.cpu.icache.demand_avg_mshr_miss_latency::total 85514.479638 # average overall mshr miss latency 545system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85514.479638 # average overall mshr miss latency 546system.cpu.icache.overall_avg_mshr_miss_latency::total 85514.479638 # average overall mshr miss latency 547system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states 548system.cpu.l2cache.tags.replacements 0 # number of replacements 549system.cpu.l2cache.tags.tagsinuse 828.582477 # Cycle average of tags in use 550system.cpu.l2cache.tags.total_refs 45 # Total number of references to valid blocks. 551system.cpu.l2cache.tags.sampled_refs 1400 # Sample count of references to valid blocks. 552system.cpu.l2cache.tags.avg_refs 0.032143 # Average number of references to valid blocks. 553system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 554system.cpu.l2cache.tags.occ_blocks::cpu.inst 591.965303 # Average occupied blocks per requestor 555system.cpu.l2cache.tags.occ_blocks::cpu.data 236.617175 # Average occupied blocks per requestor 556system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018065 # Average percentage of cache occupancy 557system.cpu.l2cache.tags.occ_percent::cpu.data 0.007221 # Average percentage of cache occupancy 558system.cpu.l2cache.tags.occ_percent::total 0.025286 # Average percentage of cache occupancy 559system.cpu.l2cache.tags.occ_task_id_blocks::1024 1400 # Occupied blocks per task id 560system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 561system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id 562system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1053 # Occupied blocks per task id 563system.cpu.l2cache.tags.occ_task_id_percent::1024 0.042725 # Percentage of cache occupancy per task id 564system.cpu.l2cache.tags.tag_accesses 12960 # Number of tag accesses 565system.cpu.l2cache.tags.data_accesses 12960 # Number of data accesses 566system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states 567system.cpu.l2cache.WritebackClean_hits::writebacks 44 # number of WritebackClean hits 568system.cpu.l2cache.WritebackClean_hits::total 44 # number of WritebackClean hits 569system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 570system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 571system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 572system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 573system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 574system.cpu.l2cache.overall_hits::total 1 # number of overall hits 575system.cpu.l2cache.ReadExReq_misses::cpu.data 211 # number of ReadExReq misses 576system.cpu.l2cache.ReadExReq_misses::total 211 # number of ReadExReq misses 577system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1105 # number of ReadCleanReq misses 578system.cpu.l2cache.ReadCleanReq_misses::total 1105 # number of ReadCleanReq misses 579system.cpu.l2cache.ReadSharedReq_misses::cpu.data 84 # number of ReadSharedReq misses 580system.cpu.l2cache.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses 581system.cpu.l2cache.demand_misses::cpu.inst 1105 # number of demand (read+write) misses 582system.cpu.l2cache.demand_misses::cpu.data 295 # number of demand (read+write) misses 583system.cpu.l2cache.demand_misses::total 1400 # number of demand (read+write) misses 584system.cpu.l2cache.overall_misses::cpu.inst 1105 # number of overall misses 585system.cpu.l2cache.overall_misses::cpu.data 295 # number of overall misses 586system.cpu.l2cache.overall_misses::total 1400 # number of overall misses 587system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16615500 # number of ReadExReq miss cycles 588system.cpu.l2cache.ReadExReq_miss_latency::total 16615500 # number of ReadExReq miss cycles 589system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 92835500 # number of ReadCleanReq miss cycles 590system.cpu.l2cache.ReadCleanReq_miss_latency::total 92835500 # number of ReadCleanReq miss cycles 591system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8021000 # number of ReadSharedReq miss cycles 592system.cpu.l2cache.ReadSharedReq_miss_latency::total 8021000 # number of ReadSharedReq miss cycles 593system.cpu.l2cache.demand_miss_latency::cpu.inst 92835500 # number of demand (read+write) miss cycles 594system.cpu.l2cache.demand_miss_latency::cpu.data 24636500 # number of demand (read+write) miss cycles 595system.cpu.l2cache.demand_miss_latency::total 117472000 # number of demand (read+write) miss cycles 596system.cpu.l2cache.overall_miss_latency::cpu.inst 92835500 # number of overall miss cycles 597system.cpu.l2cache.overall_miss_latency::cpu.data 24636500 # number of overall miss cycles 598system.cpu.l2cache.overall_miss_latency::total 117472000 # number of overall miss cycles 599system.cpu.l2cache.WritebackClean_accesses::writebacks 44 # number of WritebackClean accesses(hits+misses) 600system.cpu.l2cache.WritebackClean_accesses::total 44 # number of WritebackClean accesses(hits+misses) 601system.cpu.l2cache.ReadExReq_accesses::cpu.data 211 # number of ReadExReq accesses(hits+misses) 602system.cpu.l2cache.ReadExReq_accesses::total 211 # number of ReadExReq accesses(hits+misses) 603system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1105 # number of ReadCleanReq accesses(hits+misses) 604system.cpu.l2cache.ReadCleanReq_accesses::total 1105 # number of ReadCleanReq accesses(hits+misses) 605system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 85 # number of ReadSharedReq accesses(hits+misses) 606system.cpu.l2cache.ReadSharedReq_accesses::total 85 # number of ReadSharedReq accesses(hits+misses) 607system.cpu.l2cache.demand_accesses::cpu.inst 1105 # number of demand (read+write) accesses 608system.cpu.l2cache.demand_accesses::cpu.data 296 # number of demand (read+write) accesses 609system.cpu.l2cache.demand_accesses::total 1401 # number of demand (read+write) accesses 610system.cpu.l2cache.overall_accesses::cpu.inst 1105 # number of overall (read+write) accesses 611system.cpu.l2cache.overall_accesses::cpu.data 296 # number of overall (read+write) accesses 612system.cpu.l2cache.overall_accesses::total 1401 # number of overall (read+write) accesses 613system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 614system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 615system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses 616system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses 617system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.988235 # miss rate for ReadSharedReq accesses 618system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.988235 # miss rate for ReadSharedReq accesses 619system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses 620system.cpu.l2cache.demand_miss_rate::cpu.data 0.996622 # miss rate for demand accesses 621system.cpu.l2cache.demand_miss_rate::total 0.999286 # miss rate for demand accesses 622system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses 623system.cpu.l2cache.overall_miss_rate::cpu.data 0.996622 # miss rate for overall accesses 624system.cpu.l2cache.overall_miss_rate::total 0.999286 # miss rate for overall accesses 625system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78746.445498 # average ReadExReq miss latency 626system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78746.445498 # average ReadExReq miss latency 627system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84014.027149 # average ReadCleanReq miss latency 628system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84014.027149 # average ReadCleanReq miss latency 629system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95488.095238 # average ReadSharedReq miss latency 630system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 95488.095238 # average ReadSharedReq miss latency 631system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84014.027149 # average overall miss latency 632system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83513.559322 # average overall miss latency 633system.cpu.l2cache.demand_avg_miss_latency::total 83908.571429 # average overall miss latency 634system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84014.027149 # average overall miss latency 635system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83513.559322 # average overall miss latency 636system.cpu.l2cache.overall_avg_miss_latency::total 83908.571429 # average overall miss latency 637system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 640system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 641system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 642system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 211 # number of ReadExReq MSHR misses 644system.cpu.l2cache.ReadExReq_mshr_misses::total 211 # number of ReadExReq MSHR misses 645system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1105 # number of ReadCleanReq MSHR misses 646system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1105 # number of ReadCleanReq MSHR misses 647system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 84 # number of ReadSharedReq MSHR misses 648system.cpu.l2cache.ReadSharedReq_mshr_misses::total 84 # number of ReadSharedReq MSHR misses 649system.cpu.l2cache.demand_mshr_misses::cpu.inst 1105 # number of demand (read+write) MSHR misses 650system.cpu.l2cache.demand_mshr_misses::cpu.data 295 # number of demand (read+write) MSHR misses 651system.cpu.l2cache.demand_mshr_misses::total 1400 # number of demand (read+write) MSHR misses 652system.cpu.l2cache.overall_mshr_misses::cpu.inst 1105 # number of overall MSHR misses 653system.cpu.l2cache.overall_mshr_misses::cpu.data 295 # number of overall MSHR misses 654system.cpu.l2cache.overall_mshr_misses::total 1400 # number of overall MSHR misses 655system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14505500 # number of ReadExReq MSHR miss cycles 656system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14505500 # number of ReadExReq MSHR miss cycles 657system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 81785500 # number of ReadCleanReq MSHR miss cycles 658system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 81785500 # number of ReadCleanReq MSHR miss cycles 659system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7181000 # number of ReadSharedReq MSHR miss cycles 660system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7181000 # number of ReadSharedReq MSHR miss cycles 661system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 81785500 # number of demand (read+write) MSHR miss cycles 662system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21686500 # number of demand (read+write) MSHR miss cycles 663system.cpu.l2cache.demand_mshr_miss_latency::total 103472000 # number of demand (read+write) MSHR miss cycles 664system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 81785500 # number of overall MSHR miss cycles 665system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21686500 # number of overall MSHR miss cycles 666system.cpu.l2cache.overall_mshr_miss_latency::total 103472000 # number of overall MSHR miss cycles 667system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 668system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 669system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 670system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses 671system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.988235 # mshr miss rate for ReadSharedReq accesses 672system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.988235 # mshr miss rate for ReadSharedReq accesses 673system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses 674system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996622 # mshr miss rate for demand accesses 675system.cpu.l2cache.demand_mshr_miss_rate::total 0.999286 # mshr miss rate for demand accesses 676system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses 677system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996622 # mshr miss rate for overall accesses 678system.cpu.l2cache.overall_mshr_miss_rate::total 0.999286 # mshr miss rate for overall accesses 679system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68746.445498 # average ReadExReq mshr miss latency 680system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68746.445498 # average ReadExReq mshr miss latency 681system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74014.027149 # average ReadCleanReq mshr miss latency 682system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74014.027149 # average ReadCleanReq mshr miss latency 683system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 85488.095238 # average ReadSharedReq mshr miss latency 684system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85488.095238 # average ReadSharedReq mshr miss latency 685system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74014.027149 # average overall mshr miss latency 686system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73513.559322 # average overall mshr miss latency 687system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73908.571429 # average overall mshr miss latency 688system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74014.027149 # average overall mshr miss latency 689system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73513.559322 # average overall mshr miss latency 690system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73908.571429 # average overall mshr miss latency 691system.cpu.toL2Bus.snoop_filter.tot_requests 1445 # Total number of requests made to the snoop filter. 692system.cpu.toL2Bus.snoop_filter.hit_single_requests 45 # Number of requests hitting in the snoop filter with a single holder of the requested data. 693system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 694system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 695system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 696system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 697system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states 698system.cpu.toL2Bus.trans_dist::ReadResp 1190 # Transaction distribution 699system.cpu.toL2Bus.trans_dist::WritebackClean 44 # Transaction distribution 700system.cpu.toL2Bus.trans_dist::ReadExReq 211 # Transaction distribution 701system.cpu.toL2Bus.trans_dist::ReadExResp 211 # Transaction distribution 702system.cpu.toL2Bus.trans_dist::ReadCleanReq 1105 # Transaction distribution 703system.cpu.toL2Bus.trans_dist::ReadSharedReq 85 # Transaction distribution 704system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2254 # Packet count per connected master and slave (bytes) 705system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes) 706system.cpu.toL2Bus.pkt_count::total 2846 # Packet count per connected master and slave (bytes) 707system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 73536 # Cumulative packet size per connected master and slave (bytes) 708system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) 709system.cpu.toL2Bus.pkt_size::total 92480 # Cumulative packet size per connected master and slave (bytes) 710system.cpu.toL2Bus.snoops 0 # Total snoops (count) 711system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 712system.cpu.toL2Bus.snoop_fanout::samples 1401 # Request fanout histogram 713system.cpu.toL2Bus.snoop_fanout::mean 0.000714 # Request fanout histogram 714system.cpu.toL2Bus.snoop_fanout::stdev 0.026717 # Request fanout histogram 715system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 716system.cpu.toL2Bus.snoop_fanout::0 1400 99.93% 99.93% # Request fanout histogram 717system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram 718system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 719system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 720system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 721system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 722system.cpu.toL2Bus.snoop_fanout::total 1401 # Request fanout histogram 723system.cpu.toL2Bus.reqLayer0.occupancy 766500 # Layer occupancy (ticks) 724system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) 725system.cpu.toL2Bus.respLayer0.occupancy 1657500 # Layer occupancy (ticks) 726system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) 727system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks) 728system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 729system.membus.snoop_filter.tot_requests 1400 # Total number of requests made to the snoop filter. 730system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 731system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 732system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 733system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 734system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 735system.membus.pwrStateResidencyTicks::UNDEFINED 257396500 # Cumulative time (in ticks) in various power states 736system.membus.trans_dist::ReadResp 1189 # Transaction distribution 737system.membus.trans_dist::ReadExReq 211 # Transaction distribution 738system.membus.trans_dist::ReadExResp 211 # Transaction distribution 739system.membus.trans_dist::ReadSharedReq 1189 # Transaction distribution 740system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2800 # Packet count per connected master and slave (bytes) 741system.membus.pkt_count::total 2800 # Packet count per connected master and slave (bytes) 742system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 89600 # Cumulative packet size per connected master and slave (bytes) 743system.membus.pkt_size::total 89600 # Cumulative packet size per connected master and slave (bytes) 744system.membus.snoops 0 # Total snoops (count) 745system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 746system.membus.snoop_fanout::samples 1400 # Request fanout histogram 747system.membus.snoop_fanout::mean 0 # Request fanout histogram 748system.membus.snoop_fanout::stdev 0 # Request fanout histogram 749system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 750system.membus.snoop_fanout::0 1400 100.00% 100.00% # Request fanout histogram 751system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 752system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 753system.membus.snoop_fanout::min_value 0 # Request fanout histogram 754system.membus.snoop_fanout::max_value 0 # Request fanout histogram 755system.membus.snoop_fanout::total 1400 # Request fanout histogram 756system.membus.reqLayer0.occupancy 1611500 # Layer occupancy (ticks) 757system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) 758system.membus.respLayer1.occupancy 7433000 # Layer occupancy (ticks) 759system.membus.respLayer1.utilization 2.9 # Layer utilization (%)
| 3sim_seconds 0.000313 4sim_ticks 313251500 5final_tick 313251500 6sim_freq 1000000000000 7host_inst_rate 2591 8host_op_rate 2598 9host_tick_rate 3037898 10host_mem_usage 272308 11host_seconds 103.11 12sim_insts 267165 13sim_ops 267935 14system.voltage_domain.voltage 1 15system.clk_domain.clock 1000 16system.physmem.pwrStateResidencyTicks::UNDEFINED 313251500 17system.physmem.bytes_read::cpu.inst 79360 18system.physmem.bytes_read::cpu.data 31360 19system.physmem.bytes_read::total 110720 20system.physmem.bytes_inst_read::cpu.inst 79360 21system.physmem.bytes_inst_read::total 79360 22system.physmem.num_reads::cpu.inst 1240 23system.physmem.num_reads::cpu.data 490 24system.physmem.num_reads::total 1730 25system.physmem.bw_read::cpu.inst 253342761 26system.physmem.bw_read::cpu.data 100111252 27system.physmem.bw_read::total 353454014 28system.physmem.bw_inst_read::cpu.inst 253342761 29system.physmem.bw_inst_read::total 253342761 30system.physmem.bw_total::cpu.inst 253342761 31system.physmem.bw_total::cpu.data 100111252 32system.physmem.bw_total::total 353454014 33system.physmem.readReqs 1730 34system.physmem.writeReqs 0 35system.physmem.readBursts 1730 36system.physmem.writeBursts 0 37system.physmem.bytesReadDRAM 110720 38system.physmem.bytesReadWrQ 0 39system.physmem.bytesWritten 0 40system.physmem.bytesReadSys 110720 41system.physmem.bytesWrittenSys 0 42system.physmem.servicedByWrQ 0 43system.physmem.mergedWrBursts 0 44system.physmem.neitherReadNorWriteReqs 0 45system.physmem.perBankRdBursts::0 226 46system.physmem.perBankRdBursts::1 132 47system.physmem.perBankRdBursts::2 158 48system.physmem.perBankRdBursts::3 128 49system.physmem.perBankRdBursts::4 122 50system.physmem.perBankRdBursts::5 110 51system.physmem.perBankRdBursts::6 45 52system.physmem.perBankRdBursts::7 84 53system.physmem.perBankRdBursts::8 30 54system.physmem.perBankRdBursts::9 49 55system.physmem.perBankRdBursts::10 66 56system.physmem.perBankRdBursts::11 62 57system.physmem.perBankRdBursts::12 141 58system.physmem.perBankRdBursts::13 134 59system.physmem.perBankRdBursts::14 150 60system.physmem.perBankRdBursts::15 93 61system.physmem.perBankWrBursts::0 0 62system.physmem.perBankWrBursts::1 0 63system.physmem.perBankWrBursts::2 0 64system.physmem.perBankWrBursts::3 0 65system.physmem.perBankWrBursts::4 0 66system.physmem.perBankWrBursts::5 0 67system.physmem.perBankWrBursts::6 0 68system.physmem.perBankWrBursts::7 0 69system.physmem.perBankWrBursts::8 0 70system.physmem.perBankWrBursts::9 0 71system.physmem.perBankWrBursts::10 0 72system.physmem.perBankWrBursts::11 0 73system.physmem.perBankWrBursts::12 0 74system.physmem.perBankWrBursts::13 0 75system.physmem.perBankWrBursts::14 0 76system.physmem.perBankWrBursts::15 0 77system.physmem.numRdRetry 0 78system.physmem.numWrRetry 0 79system.physmem.totGap 313129500 80system.physmem.readPktSize::0 0 81system.physmem.readPktSize::1 0 82system.physmem.readPktSize::2 0 83system.physmem.readPktSize::3 0 84system.physmem.readPktSize::4 0 85system.physmem.readPktSize::5 0 86system.physmem.readPktSize::6 1730 87system.physmem.writePktSize::0 0 88system.physmem.writePktSize::1 0 89system.physmem.writePktSize::2 0 90system.physmem.writePktSize::3 0 91system.physmem.writePktSize::4 0 92system.physmem.writePktSize::5 0 93system.physmem.writePktSize::6 0 94system.physmem.rdQLenPdf::0 1515 95system.physmem.rdQLenPdf::1 197 96system.physmem.rdQLenPdf::2 18 97system.physmem.rdQLenPdf::3 0 98system.physmem.rdQLenPdf::4 0 99system.physmem.rdQLenPdf::5 0 100system.physmem.rdQLenPdf::6 0 101system.physmem.rdQLenPdf::7 0 102system.physmem.rdQLenPdf::8 0 103system.physmem.rdQLenPdf::9 0 104system.physmem.rdQLenPdf::10 0 105system.physmem.rdQLenPdf::11 0 106system.physmem.rdQLenPdf::12 0 107system.physmem.rdQLenPdf::13 0 108system.physmem.rdQLenPdf::14 0 109system.physmem.rdQLenPdf::15 0 110system.physmem.rdQLenPdf::16 0 111system.physmem.rdQLenPdf::17 0 112system.physmem.rdQLenPdf::18 0 113system.physmem.rdQLenPdf::19 0 114system.physmem.rdQLenPdf::20 0 115system.physmem.rdQLenPdf::21 0 116system.physmem.rdQLenPdf::22 0 117system.physmem.rdQLenPdf::23 0 118system.physmem.rdQLenPdf::24 0 119system.physmem.rdQLenPdf::25 0 120system.physmem.rdQLenPdf::26 0 121system.physmem.rdQLenPdf::27 0 122system.physmem.rdQLenPdf::28 0 123system.physmem.rdQLenPdf::29 0 124system.physmem.rdQLenPdf::30 0 125system.physmem.rdQLenPdf::31 0 126system.physmem.wrQLenPdf::0 0 127system.physmem.wrQLenPdf::1 0 128system.physmem.wrQLenPdf::2 0 129system.physmem.wrQLenPdf::3 0 130system.physmem.wrQLenPdf::4 0 131system.physmem.wrQLenPdf::5 0 132system.physmem.wrQLenPdf::6 0 133system.physmem.wrQLenPdf::7 0 134system.physmem.wrQLenPdf::8 0 135system.physmem.wrQLenPdf::9 0 136system.physmem.wrQLenPdf::10 0 137system.physmem.wrQLenPdf::11 0 138system.physmem.wrQLenPdf::12 0 139system.physmem.wrQLenPdf::13 0 140system.physmem.wrQLenPdf::14 0 141system.physmem.wrQLenPdf::15 0 142system.physmem.wrQLenPdf::16 0 143system.physmem.wrQLenPdf::17 0 144system.physmem.wrQLenPdf::18 0 145system.physmem.wrQLenPdf::19 0 146system.physmem.wrQLenPdf::20 0 147system.physmem.wrQLenPdf::21 0 148system.physmem.wrQLenPdf::22 0 149system.physmem.wrQLenPdf::23 0 150system.physmem.wrQLenPdf::24 0 151system.physmem.wrQLenPdf::25 0 152system.physmem.wrQLenPdf::26 0 153system.physmem.wrQLenPdf::27 0 154system.physmem.wrQLenPdf::28 0 155system.physmem.wrQLenPdf::29 0 156system.physmem.wrQLenPdf::30 0 157system.physmem.wrQLenPdf::31 0 158system.physmem.wrQLenPdf::32 0 159system.physmem.wrQLenPdf::33 0 160system.physmem.wrQLenPdf::34 0 161system.physmem.wrQLenPdf::35 0 162system.physmem.wrQLenPdf::36 0 163system.physmem.wrQLenPdf::37 0 164system.physmem.wrQLenPdf::38 0 165system.physmem.wrQLenPdf::39 0 166system.physmem.wrQLenPdf::40 0 167system.physmem.wrQLenPdf::41 0 168system.physmem.wrQLenPdf::42 0 169system.physmem.wrQLenPdf::43 0 170system.physmem.wrQLenPdf::44 0 171system.physmem.wrQLenPdf::45 0 172system.physmem.wrQLenPdf::46 0 173system.physmem.wrQLenPdf::47 0 174system.physmem.wrQLenPdf::48 0 175system.physmem.wrQLenPdf::49 0 176system.physmem.wrQLenPdf::50 0 177system.physmem.wrQLenPdf::51 0 178system.physmem.wrQLenPdf::52 0 179system.physmem.wrQLenPdf::53 0 180system.physmem.wrQLenPdf::54 0 181system.physmem.wrQLenPdf::55 0 182system.physmem.wrQLenPdf::56 0 183system.physmem.wrQLenPdf::57 0 184system.physmem.wrQLenPdf::58 0 185system.physmem.wrQLenPdf::59 0 186system.physmem.wrQLenPdf::60 0 187system.physmem.wrQLenPdf::61 0 188system.physmem.wrQLenPdf::62 0 189system.physmem.wrQLenPdf::63 0 190system.physmem.bytesPerActivate::samples 384 191system.physmem.bytesPerActivate::mean 284.166667 192system.physmem.bytesPerActivate::gmean 191.143330 193system.physmem.bytesPerActivate::stdev 258.838001 194system.physmem.bytesPerActivate::0-127 121 31.51% 31.51% 195system.physmem.bytesPerActivate::128-255 78 20.31% 51.82% 196system.physmem.bytesPerActivate::256-383 78 20.31% 72.14% 197system.physmem.bytesPerActivate::384-511 41 10.68% 82.81% 198system.physmem.bytesPerActivate::512-639 16 4.17% 86.98% 199system.physmem.bytesPerActivate::640-767 17 4.43% 91.41% 200system.physmem.bytesPerActivate::768-895 7 1.82% 93.23% 201system.physmem.bytesPerActivate::896-1023 13 3.39% 96.61% 202system.physmem.bytesPerActivate::1024-1151 13 3.39% 100.00% 203system.physmem.bytesPerActivate::total 384 204system.physmem.totQLat 26594000 205system.physmem.totMemAccLat 59031500 206system.physmem.totBusLat 8650000 207system.physmem.avgQLat 15372.25 208system.physmem.avgBusLat 5000.00 209system.physmem.avgMemAccLat 34122.25 210system.physmem.avgRdBW 353.45 211system.physmem.avgWrBW 0.00 212system.physmem.avgRdBWSys 353.45 213system.physmem.avgWrBWSys 0.00 214system.physmem.peakBW 12800.00 215system.physmem.busUtil 2.76 216system.physmem.busUtilRead 2.76 217system.physmem.busUtilWrite 0.00 218system.physmem.avgRdQLen 1.08 219system.physmem.avgWrQLen 0.00 220system.physmem.readRowHits 1341 221system.physmem.writeRowHits 0 222system.physmem.readRowHitRate 77.51 223system.physmem.writeRowHitRate nan 224system.physmem.avgGap 180999.71 225system.physmem.pageHitRate 77.51 226system.physmem_0.actEnergy 1727880 227system.physmem_0.preEnergy 910800 228system.physmem_0.readEnergy 7175700 229system.physmem_0.writeEnergy 0 230system.physmem_0.refreshEnergy 24585600.000000 231system.physmem_0.actBackEnergy 18117450 232system.physmem_0.preBackEnergy 554880 233system.physmem_0.actPowerDownEnergy 118740120 234system.physmem_0.prePowerDownEnergy 4485600 235system.physmem_0.selfRefreshEnergy 0 236system.physmem_0.totalEnergy 176298030 237system.physmem_0.averagePower 562.798477 238system.physmem_0.totalIdleTime 271894500 239system.physmem_0.memoryStateTime::IDLE 246000 240system.physmem_0.memoryStateTime::REF 10400000 241system.physmem_0.memoryStateTime::SREF 0 242system.physmem_0.memoryStateTime::PRE_PDN 11677750 243system.physmem_0.memoryStateTime::ACT 30512750 244system.physmem_0.memoryStateTime::ACT_PDN 260415000 245system.physmem_1.actEnergy 1049580 246system.physmem_1.preEnergy 546480 247system.physmem_1.readEnergy 5176500 248system.physmem_1.writeEnergy 0 249system.physmem_1.refreshEnergy 19053840.000000 250system.physmem_1.actBackEnergy 13439460 251system.physmem_1.preBackEnergy 996000 252system.physmem_1.actPowerDownEnergy 66734460 253system.physmem_1.prePowerDownEnergy 15381120 254system.physmem_1.selfRefreshEnergy 24957060 255system.physmem_1.totalEnergy 147334500 256system.physmem_1.averagePower 470.337827 257system.physmem_1.totalIdleTime 281112750 258system.physmem_1.memoryStateTime::IDLE 1783500 259system.physmem_1.memoryStateTime::REF 8084000 260system.physmem_1.memoryStateTime::SREF 94783750 261system.physmem_1.memoryStateTime::PRE_PDN 40053750 262system.physmem_1.memoryStateTime::ACT 22186000 263system.physmem_1.memoryStateTime::ACT_PDN 146360500 264system.pwrStateResidencyTicks::UNDEFINED 313251500 265system.cpu.branchPred.lookups 74064 266system.cpu.branchPred.condPredicted 50422 267system.cpu.branchPred.condIncorrect 6373 268system.cpu.branchPred.BTBLookups 52846 269system.cpu.branchPred.BTBHits 24168 270system.cpu.branchPred.BTBCorrect 0 271system.cpu.branchPred.BTBHitPct 45.732884 272system.cpu.branchPred.usedRAS 0 273system.cpu.branchPred.RASInCorrect 0 274system.cpu.branchPred.indirectLookups 16397 275system.cpu.branchPred.indirectHits 9369 276system.cpu.branchPred.indirectMisses 7028 277system.cpu.branchPredindirectMispredicted 3663 278system.cpu_clk_domain.clock 500 279system.cpu.dtb.read_hits 0 280system.cpu.dtb.read_misses 0 281system.cpu.dtb.read_accesses 0 282system.cpu.dtb.write_hits 0 283system.cpu.dtb.write_misses 0 284system.cpu.dtb.write_accesses 0 285system.cpu.dtb.hits 0 286system.cpu.dtb.misses 0 287system.cpu.dtb.accesses 0 288system.cpu.itb.read_hits 0 289system.cpu.itb.read_misses 0 290system.cpu.itb.read_accesses 0 291system.cpu.itb.write_hits 0 292system.cpu.itb.write_misses 0 293system.cpu.itb.write_accesses 0 294system.cpu.itb.hits 0 295system.cpu.itb.misses 0 296system.cpu.itb.accesses 0 297system.cpu.workload.numSyscalls 182 298system.cpu.pwrStateResidencyTicks::ON 313251500 299system.cpu.numCycles 626503 300system.cpu.numWorkItemsStarted 0 301system.cpu.numWorkItemsCompleted 0 302system.cpu.committedInsts 267165 303system.cpu.committedOps 267935 304system.cpu.discardedOps 16687 305system.cpu.numFetchSuspends 0 306system.cpu.cpi 2.345004 307system.cpu.ipc 0.426439 308system.cpu.op_class_0::No_OpClass 191 0.07% 0.07% 309system.cpu.op_class_0::IntAlu 157741 58.87% 58.94% 310system.cpu.op_class_0::IntMult 436 0.16% 59.11% 311system.cpu.op_class_0::IntDiv 230 0.09% 59.19% 312system.cpu.op_class_0::FloatAdd 0 0.00% 59.19% 313system.cpu.op_class_0::FloatCmp 0 0.00% 59.19% 314system.cpu.op_class_0::FloatCvt 0 0.00% 59.19% 315system.cpu.op_class_0::FloatMult 0 0.00% 59.19% 316system.cpu.op_class_0::FloatMultAcc 0 0.00% 59.19% 317system.cpu.op_class_0::FloatDiv 0 0.00% 59.19% 318system.cpu.op_class_0::FloatMisc 0 0.00% 59.19% 319system.cpu.op_class_0::FloatSqrt 0 0.00% 59.19% 320system.cpu.op_class_0::SimdAdd 0 0.00% 59.19% 321system.cpu.op_class_0::SimdAddAcc 0 0.00% 59.19% 322system.cpu.op_class_0::SimdAlu 0 0.00% 59.19% 323system.cpu.op_class_0::SimdCmp 0 0.00% 59.19% 324system.cpu.op_class_0::SimdCvt 0 0.00% 59.19% 325system.cpu.op_class_0::SimdMisc 0 0.00% 59.19% 326system.cpu.op_class_0::SimdMult 0 0.00% 59.19% 327system.cpu.op_class_0::SimdMultAcc 0 0.00% 59.19% 328system.cpu.op_class_0::SimdShift 0 0.00% 59.19% 329system.cpu.op_class_0::SimdShiftAcc 0 0.00% 59.19% 330system.cpu.op_class_0::SimdSqrt 0 0.00% 59.19% 331system.cpu.op_class_0::SimdFloatAdd 0 0.00% 59.19% 332system.cpu.op_class_0::SimdFloatAlu 0 0.00% 59.19% 333system.cpu.op_class_0::SimdFloatCmp 0 0.00% 59.19% 334system.cpu.op_class_0::SimdFloatCvt 0 0.00% 59.19% 335system.cpu.op_class_0::SimdFloatDiv 0 0.00% 59.19% 336system.cpu.op_class_0::SimdFloatMisc 0 0.00% 59.19% 337system.cpu.op_class_0::SimdFloatMult 0 0.00% 59.19% 338system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 59.19% 339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 59.19% 340system.cpu.op_class_0::MemRead 67806 25.31% 84.50% 341system.cpu.op_class_0::MemWrite 41519 15.50% 100.00% 342system.cpu.op_class_0::FloatMemRead 0 0.00% 100.00% 343system.cpu.op_class_0::FloatMemWrite 12 0.00% 100.00% 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% 346system.cpu.op_class_0::total 267935 347system.cpu.tickCycles 372506 348system.cpu.idleCycles 253997 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 313251500 350system.cpu.dcache.tags.replacements 0 351system.cpu.dcache.tags.tagsinuse 375.293791 352system.cpu.dcache.tags.total_refs 111829 353system.cpu.dcache.tags.sampled_refs 492 354system.cpu.dcache.tags.avg_refs 227.294715 355system.cpu.dcache.tags.warmup_cycle 0 356system.cpu.dcache.tags.occ_blocks::cpu.data 375.293791 357system.cpu.dcache.tags.occ_percent::cpu.data 0.091624 358system.cpu.dcache.tags.occ_percent::total 0.091624 359system.cpu.dcache.tags.occ_task_id_blocks::1024 492 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 362system.cpu.dcache.tags.age_task_id_blocks_1024::2 459 363system.cpu.dcache.tags.occ_task_id_percent::1024 0.120117 364system.cpu.dcache.tags.tag_accesses 225460 365system.cpu.dcache.tags.data_accesses 225460 366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 313251500 367system.cpu.dcache.ReadReq_hits::cpu.data 69905 368system.cpu.dcache.ReadReq_hits::total 69905 369system.cpu.dcache.WriteReq_hits::cpu.data 40366 370system.cpu.dcache.WriteReq_hits::total 40366 371system.cpu.dcache.LoadLockedReq_hits::cpu.data 779 372system.cpu.dcache.LoadLockedReq_hits::total 779 373system.cpu.dcache.StoreCondReq_hits::cpu.data 779 374system.cpu.dcache.StoreCondReq_hits::total 779 375system.cpu.dcache.demand_hits::cpu.data 110271 376system.cpu.dcache.demand_hits::total 110271 377system.cpu.dcache.overall_hits::cpu.data 110271 378system.cpu.dcache.overall_hits::total 110271 379system.cpu.dcache.ReadReq_misses::cpu.data 269 380system.cpu.dcache.ReadReq_misses::total 269 381system.cpu.dcache.WriteReq_misses::cpu.data 386 382system.cpu.dcache.WriteReq_misses::total 386 383system.cpu.dcache.demand_misses::cpu.data 655 384system.cpu.dcache.demand_misses::total 655 385system.cpu.dcache.overall_misses::cpu.data 655 386system.cpu.dcache.overall_misses::total 655 387system.cpu.dcache.ReadReq_miss_latency::cpu.data 24582500 388system.cpu.dcache.ReadReq_miss_latency::total 24582500 389system.cpu.dcache.WriteReq_miss_latency::cpu.data 32000500 390system.cpu.dcache.WriteReq_miss_latency::total 32000500 391system.cpu.dcache.demand_miss_latency::cpu.data 56583000 392system.cpu.dcache.demand_miss_latency::total 56583000 393system.cpu.dcache.overall_miss_latency::cpu.data 56583000 394system.cpu.dcache.overall_miss_latency::total 56583000 395system.cpu.dcache.ReadReq_accesses::cpu.data 70174 396system.cpu.dcache.ReadReq_accesses::total 70174 397system.cpu.dcache.WriteReq_accesses::cpu.data 40752 398system.cpu.dcache.WriteReq_accesses::total 40752 399system.cpu.dcache.LoadLockedReq_accesses::cpu.data 779 400system.cpu.dcache.LoadLockedReq_accesses::total 779 401system.cpu.dcache.StoreCondReq_accesses::cpu.data 779 402system.cpu.dcache.StoreCondReq_accesses::total 779 403system.cpu.dcache.demand_accesses::cpu.data 110926 404system.cpu.dcache.demand_accesses::total 110926 405system.cpu.dcache.overall_accesses::cpu.data 110926 406system.cpu.dcache.overall_accesses::total 110926 407system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003833 408system.cpu.dcache.ReadReq_miss_rate::total 0.003833 409system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009472 410system.cpu.dcache.WriteReq_miss_rate::total 0.009472 411system.cpu.dcache.demand_miss_rate::cpu.data 0.005905 412system.cpu.dcache.demand_miss_rate::total 0.005905 413system.cpu.dcache.overall_miss_rate::cpu.data 0.005905 414system.cpu.dcache.overall_miss_rate::total 0.005905 415system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 91384.758364 416system.cpu.dcache.ReadReq_avg_miss_latency::total 91384.758364 417system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 82902.849741 418system.cpu.dcache.WriteReq_avg_miss_latency::total 82902.849741 419system.cpu.dcache.demand_avg_miss_latency::cpu.data 86386.259542 420system.cpu.dcache.demand_avg_miss_latency::total 86386.259542 421system.cpu.dcache.overall_avg_miss_latency::cpu.data 86386.259542 422system.cpu.dcache.overall_avg_miss_latency::total 86386.259542 423system.cpu.dcache.blocked_cycles::no_mshrs 0 424system.cpu.dcache.blocked_cycles::no_targets 0 425system.cpu.dcache.blocked::no_mshrs 0 426system.cpu.dcache.blocked::no_targets 0 427system.cpu.dcache.avg_blocked_cycles::no_mshrs nan 428system.cpu.dcache.avg_blocked_cycles::no_targets nan 429system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 430system.cpu.dcache.ReadReq_mshr_hits::total 1 431system.cpu.dcache.WriteReq_mshr_hits::cpu.data 162 432system.cpu.dcache.WriteReq_mshr_hits::total 162 433system.cpu.dcache.demand_mshr_hits::cpu.data 163 434system.cpu.dcache.demand_mshr_hits::total 163 435system.cpu.dcache.overall_mshr_hits::cpu.data 163 436system.cpu.dcache.overall_mshr_hits::total 163 437system.cpu.dcache.ReadReq_mshr_misses::cpu.data 268 438system.cpu.dcache.ReadReq_mshr_misses::total 268 439system.cpu.dcache.WriteReq_mshr_misses::cpu.data 224 440system.cpu.dcache.WriteReq_mshr_misses::total 224 441system.cpu.dcache.demand_mshr_misses::cpu.data 492 442system.cpu.dcache.demand_mshr_misses::total 492 443system.cpu.dcache.overall_mshr_misses::cpu.data 492 444system.cpu.dcache.overall_mshr_misses::total 492 445system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24235500 446system.cpu.dcache.ReadReq_mshr_miss_latency::total 24235500 447system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 19240000 448system.cpu.dcache.WriteReq_mshr_miss_latency::total 19240000 449system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43475500 450system.cpu.dcache.demand_mshr_miss_latency::total 43475500 451system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43475500 452system.cpu.dcache.overall_mshr_miss_latency::total 43475500 453system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003819 454system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003819 455system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005497 456system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005497 457system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004435 458system.cpu.dcache.demand_mshr_miss_rate::total 0.004435 459system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004435 460system.cpu.dcache.overall_mshr_miss_rate::total 0.004435 461system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90430.970149 462system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90430.970149 463system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85892.857143 464system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85892.857143 465system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88364.837398 466system.cpu.dcache.demand_avg_mshr_miss_latency::total 88364.837398 467system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88364.837398 468system.cpu.dcache.overall_avg_mshr_miss_latency::total 88364.837398 469system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 313251500 470system.cpu.icache.tags.replacements 98 471system.cpu.icache.tags.tagsinuse 729.007799 472system.cpu.icache.tags.total_refs 102368 473system.cpu.icache.tags.sampled_refs 1248 474system.cpu.icache.tags.avg_refs 82.025641 475system.cpu.icache.tags.warmup_cycle 0 476system.cpu.icache.tags.occ_blocks::cpu.inst 729.007799 477system.cpu.icache.tags.occ_percent::cpu.inst 0.355961 478system.cpu.icache.tags.occ_percent::total 0.355961 479system.cpu.icache.tags.occ_task_id_blocks::1024 1150 480system.cpu.icache.tags.age_task_id_blocks_1024::0 50 481system.cpu.icache.tags.age_task_id_blocks_1024::1 200 482system.cpu.icache.tags.age_task_id_blocks_1024::2 900 483system.cpu.icache.tags.occ_task_id_percent::1024 0.561523 484system.cpu.icache.tags.tag_accesses 208482 485system.cpu.icache.tags.data_accesses 208482 486system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 313251500 487system.cpu.icache.ReadReq_hits::cpu.inst 102368 488system.cpu.icache.ReadReq_hits::total 102368 489system.cpu.icache.demand_hits::cpu.inst 102368 490system.cpu.icache.demand_hits::total 102368 491system.cpu.icache.overall_hits::cpu.inst 102368 492system.cpu.icache.overall_hits::total 102368 493system.cpu.icache.ReadReq_misses::cpu.inst 1249 494system.cpu.icache.ReadReq_misses::total 1249 495system.cpu.icache.demand_misses::cpu.inst 1249 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