1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.000386 # Number of seconds simulated
4sim_ticks 385535500 # Number of ticks simulated
5final_tick 385535500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 27855 # Simulator instruction rate (inst/s)
8host_op_rate 27855 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 47485128 # Simulator tick rate (ticks/s)
10host_mem_usage 243704 # Number of bytes of host memory used
11host_seconds 8.12 # Real time elapsed on the host
12sim_insts 226159 # Number of instructions simulated
13sim_ops 226159 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 53632 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 18944 # Number of bytes read from this memory
19system.physmem.bytes_read::total 72576 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 53632 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 53632 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 838 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 296 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 1134 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 139110406 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 49136850 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 188247256 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 139110406 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 139110406 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 139110406 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 49136850 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 188247256 # Total bandwidth to/from this memory (bytes/s)
33system.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
34system.cpu_clk_domain.clock 500 # Clock period in ticks
35system.cpu.dtb.read_hits 0 # DTB read hits
36system.cpu.dtb.read_misses 0 # DTB read misses
37system.cpu.dtb.read_accesses 0 # DTB read accesses
38system.cpu.dtb.write_hits 0 # DTB write hits
39system.cpu.dtb.write_misses 0 # DTB write misses
40system.cpu.dtb.write_accesses 0 # DTB write accesses
41system.cpu.dtb.hits 0 # DTB hits
42system.cpu.dtb.misses 0 # DTB misses
43system.cpu.dtb.accesses 0 # DTB accesses
44system.cpu.itb.read_hits 0 # DTB read hits
45system.cpu.itb.read_misses 0 # DTB read misses
46system.cpu.itb.read_accesses 0 # DTB read accesses
47system.cpu.itb.write_hits 0 # DTB write hits
48system.cpu.itb.write_misses 0 # DTB write misses
49system.cpu.itb.write_accesses 0 # DTB write accesses
50system.cpu.itb.hits 0 # DTB hits
51system.cpu.itb.misses 0 # DTB misses
52system.cpu.itb.accesses 0 # DTB accesses
53system.cpu.workload.numSyscalls 115 # Number of system calls
54system.cpu.pwrStateResidencyTicks::ON 385535500 # Cumulative time (in ticks) in various power states
55system.cpu.numCycles 771071 # number of cpu cycles simulated
56system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
57system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
58system.cpu.committedInsts 226159 # Number of instructions committed
59system.cpu.committedOps 226159 # Number of ops (including micro ops) committed
60system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses
61system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses
62system.cpu.num_func_calls 16616 # number of times a function call or return occured
63system.cpu.num_conditional_control_insts 33789 # number of instructions that are conditional controls
64system.cpu.num_int_insts 225992 # number of integer instructions
65system.cpu.num_fp_insts 862 # number of float instructions
66system.cpu.num_int_register_reads 298589 # number of times the integer registers were read
67system.cpu.num_int_register_writes 154866 # number of times the integer registers were written
68system.cpu.num_fp_register_reads 733 # number of times the floating registers were read
69system.cpu.num_fp_register_writes 588 # number of times the floating registers were written
70system.cpu.num_mem_refs 88941 # number of memory refs
71system.cpu.num_load_insts 51711 # Number of load instructions
72system.cpu.num_store_insts 37230 # Number of store instructions
73system.cpu.num_idle_cycles 0 # Number of idle cycles
74system.cpu.num_busy_cycles 771071 # Number of busy cycles
75system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
76system.cpu.idle_fraction 0 # Percentage of idle cycles
77system.cpu.Branches 50405 # Number of branches fetched
78system.cpu.op_class::No_OpClass 117 0.05% 0.05% # Class of executed instruction
79system.cpu.op_class::IntAlu 136540 60.34% 60.39% # Class of executed instruction
80system.cpu.op_class::IntMult 325 0.14% 60.54% # Class of executed instruction
81system.cpu.op_class::IntDiv 40 0.02% 60.56% # Class of executed instruction
82system.cpu.op_class::FloatAdd 104 0.05% 60.60% # Class of executed instruction
83system.cpu.op_class::FloatCmp 119 0.05% 60.65% # Class of executed instruction
84system.cpu.op_class::FloatCvt 43 0.02% 60.67% # Class of executed instruction
85system.cpu.op_class::FloatMult 30 0.01% 60.69% # Class of executed instruction
86system.cpu.op_class::FloatMultAcc 0 0.00% 60.69% # Class of executed instruction
87system.cpu.op_class::FloatDiv 11 0.00% 60.69% # Class of executed instruction
88system.cpu.op_class::FloatMisc 0 0.00% 60.69% # Class of executed instruction
89system.cpu.op_class::FloatSqrt 5 0.00% 60.69% # Class of executed instruction
90system.cpu.op_class::SimdAdd 0 0.00% 60.69% # Class of executed instruction
91system.cpu.op_class::SimdAddAcc 0 0.00% 60.69% # Class of executed instruction
92system.cpu.op_class::SimdAlu 0 0.00% 60.69% # Class of executed instruction
93system.cpu.op_class::SimdCmp 0 0.00% 60.69% # Class of executed instruction
94system.cpu.op_class::SimdCvt 0 0.00% 60.69% # Class of executed instruction
95system.cpu.op_class::SimdMisc 0 0.00% 60.69% # Class of executed instruction
96system.cpu.op_class::SimdMult 0 0.00% 60.69% # Class of executed instruction
97system.cpu.op_class::SimdMultAcc 0 0.00% 60.69% # Class of executed instruction
98system.cpu.op_class::SimdShift 0 0.00% 60.69% # Class of executed instruction
99system.cpu.op_class::SimdShiftAcc 0 0.00% 60.69% # Class of executed instruction
100system.cpu.op_class::SimdSqrt 0 0.00% 60.69% # Class of executed instruction
101system.cpu.op_class::SimdFloatAdd 0 0.00% 60.69% # Class of executed instruction
102system.cpu.op_class::SimdFloatAlu 0 0.00% 60.69% # Class of executed instruction
103system.cpu.op_class::SimdFloatCmp 0 0.00% 60.69% # Class of executed instruction
104system.cpu.op_class::SimdFloatCvt 0 0.00% 60.69% # Class of executed instruction
105system.cpu.op_class::SimdFloatDiv 0 0.00% 60.69% # Class of executed instruction
106system.cpu.op_class::SimdFloatMisc 0 0.00% 60.69% # Class of executed instruction
107system.cpu.op_class::SimdFloatMult 0 0.00% 60.69% # Class of executed instruction
108system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.69% # Class of executed instruction
109system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.69% # Class of executed instruction
110system.cpu.op_class::MemRead 51297 22.67% 83.36% # Class of executed instruction
111system.cpu.op_class::MemWrite 37094 16.39% 99.76% # Class of executed instruction
112system.cpu.op_class::FloatMemRead 414 0.18% 99.94% # Class of executed instruction
113system.cpu.op_class::FloatMemWrite 136 0.06% 100.00% # Class of executed instruction
114system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
115system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
116system.cpu.op_class::total 226275 # Class of executed instruction
117system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
118system.cpu.dcache.tags.replacements 0 # number of replacements
119system.cpu.dcache.tags.tagsinuse 246.215915 # Cycle average of tags in use
120system.cpu.dcache.tags.total_refs 88644 # Total number of references to valid blocks.
121system.cpu.dcache.tags.sampled_refs 296 # Sample count of references to valid blocks.
122system.cpu.dcache.tags.avg_refs 299.472973 # Average number of references to valid blocks.
123system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
124system.cpu.dcache.tags.occ_blocks::cpu.data 246.215915 # Average occupied blocks per requestor
125system.cpu.dcache.tags.occ_percent::cpu.data 0.060111 # Average percentage of cache occupancy
126system.cpu.dcache.tags.occ_percent::total 0.060111 # Average percentage of cache occupancy
127system.cpu.dcache.tags.occ_task_id_blocks::1024 296 # Occupied blocks per task id
128system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
129system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
130system.cpu.dcache.tags.age_task_id_blocks_1024::2 278 # Occupied blocks per task id
131system.cpu.dcache.tags.occ_task_id_percent::1024 0.072266 # Percentage of cache occupancy per task id
132system.cpu.dcache.tags.tag_accesses 178176 # Number of tag accesses
133system.cpu.dcache.tags.data_accesses 178176 # Number of data accesses
134system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
135system.cpu.dcache.ReadReq_hits::cpu.data 51622 # number of ReadReq hits
136system.cpu.dcache.ReadReq_hits::total 51622 # number of ReadReq hits
137system.cpu.dcache.WriteReq_hits::cpu.data 37022 # number of WriteReq hits
138system.cpu.dcache.WriteReq_hits::total 37022 # number of WriteReq hits
139system.cpu.dcache.demand_hits::cpu.data 88644 # number of demand (read+write) hits
140system.cpu.dcache.demand_hits::total 88644 # number of demand (read+write) hits
141system.cpu.dcache.overall_hits::cpu.data 88644 # number of overall hits
142system.cpu.dcache.overall_hits::total 88644 # number of overall hits
143system.cpu.dcache.ReadReq_misses::cpu.data 89 # number of ReadReq misses
144system.cpu.dcache.ReadReq_misses::total 89 # number of ReadReq misses
145system.cpu.dcache.WriteReq_misses::cpu.data 207 # number of WriteReq misses
146system.cpu.dcache.WriteReq_misses::total 207 # number of WriteReq misses
147system.cpu.dcache.demand_misses::cpu.data 296 # number of demand (read+write) misses
148system.cpu.dcache.demand_misses::total 296 # number of demand (read+write) misses
149system.cpu.dcache.overall_misses::cpu.data 296 # number of overall misses
150system.cpu.dcache.overall_misses::total 296 # number of overall misses
151system.cpu.dcache.ReadReq_miss_latency::cpu.data 5607000 # number of ReadReq miss cycles
152system.cpu.dcache.ReadReq_miss_latency::total 5607000 # number of ReadReq miss cycles
153system.cpu.dcache.WriteReq_miss_latency::cpu.data 13041000 # number of WriteReq miss cycles
154system.cpu.dcache.WriteReq_miss_latency::total 13041000 # number of WriteReq miss cycles
155system.cpu.dcache.demand_miss_latency::cpu.data 18648000 # number of demand (read+write) miss cycles
156system.cpu.dcache.demand_miss_latency::total 18648000 # number of demand (read+write) miss cycles
157system.cpu.dcache.overall_miss_latency::cpu.data 18648000 # number of overall miss cycles
158system.cpu.dcache.overall_miss_latency::total 18648000 # number of overall miss cycles
159system.cpu.dcache.ReadReq_accesses::cpu.data 51711 # number of ReadReq accesses(hits+misses)
160system.cpu.dcache.ReadReq_accesses::total 51711 # number of ReadReq accesses(hits+misses)
161system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses)
162system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses)
163system.cpu.dcache.demand_accesses::cpu.data 88940 # number of demand (read+write) accesses
164system.cpu.dcache.demand_accesses::total 88940 # number of demand (read+write) accesses
165system.cpu.dcache.overall_accesses::cpu.data 88940 # number of overall (read+write) accesses
166system.cpu.dcache.overall_accesses::total 88940 # number of overall (read+write) accesses
167system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001721 # miss rate for ReadReq accesses
168system.cpu.dcache.ReadReq_miss_rate::total 0.001721 # miss rate for ReadReq accesses
169system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005560 # miss rate for WriteReq accesses
170system.cpu.dcache.WriteReq_miss_rate::total 0.005560 # miss rate for WriteReq accesses
171system.cpu.dcache.demand_miss_rate::cpu.data 0.003328 # miss rate for demand accesses
172system.cpu.dcache.demand_miss_rate::total 0.003328 # miss rate for demand accesses
173system.cpu.dcache.overall_miss_rate::cpu.data 0.003328 # miss rate for overall accesses
174system.cpu.dcache.overall_miss_rate::total 0.003328 # miss rate for overall accesses
175system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
176system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
177system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
178system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
179system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
180system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
181system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
182system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
183system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
184system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
185system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
186system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
187system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
188system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
189system.cpu.dcache.ReadReq_mshr_misses::cpu.data 89 # number of ReadReq MSHR misses
190system.cpu.dcache.ReadReq_mshr_misses::total 89 # number of ReadReq MSHR misses
191system.cpu.dcache.WriteReq_mshr_misses::cpu.data 207 # number of WriteReq MSHR misses
192system.cpu.dcache.WriteReq_mshr_misses::total 207 # number of WriteReq MSHR misses
193system.cpu.dcache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses
194system.cpu.dcache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses
195system.cpu.dcache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses
196system.cpu.dcache.overall_mshr_misses::total 296 # number of overall MSHR misses
197system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5518000 # number of ReadReq MSHR miss cycles
198system.cpu.dcache.ReadReq_mshr_miss_latency::total 5518000 # number of ReadReq MSHR miss cycles
199system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12834000 # number of WriteReq MSHR miss cycles
200system.cpu.dcache.WriteReq_mshr_miss_latency::total 12834000 # number of WriteReq MSHR miss cycles
201system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18352000 # number of demand (read+write) MSHR miss cycles
202system.cpu.dcache.demand_mshr_miss_latency::total 18352000 # number of demand (read+write) MSHR miss cycles
203system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18352000 # number of overall MSHR miss cycles
204system.cpu.dcache.overall_mshr_miss_latency::total 18352000 # number of overall MSHR miss cycles
205system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001721 # mshr miss rate for ReadReq accesses
206system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001721 # mshr miss rate for ReadReq accesses
207system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005560 # mshr miss rate for WriteReq accesses
208system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005560 # mshr miss rate for WriteReq accesses
209system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003328 # mshr miss rate for demand accesses
210system.cpu.dcache.demand_mshr_miss_rate::total 0.003328 # mshr miss rate for demand accesses
211system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003328 # mshr miss rate for overall accesses
212system.cpu.dcache.overall_mshr_miss_rate::total 0.003328 # mshr miss rate for overall accesses
213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
214system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
216system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
217system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
218system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
219system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
220system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
221system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
222system.cpu.icache.tags.replacements 31 # number of replacements
223system.cpu.icache.tags.tagsinuse 467.546782 # Cycle average of tags in use
224system.cpu.icache.tags.total_refs 225437 # Total number of references to valid blocks.
225system.cpu.icache.tags.sampled_refs 839 # Sample count of references to valid blocks.
226system.cpu.icache.tags.avg_refs 268.697259 # Average number of references to valid blocks.
227system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
228system.cpu.icache.tags.occ_blocks::cpu.inst 467.546782 # Average occupied blocks per requestor
229system.cpu.icache.tags.occ_percent::cpu.inst 0.228294 # Average percentage of cache occupancy
230system.cpu.icache.tags.occ_percent::total 0.228294 # Average percentage of cache occupancy
231system.cpu.icache.tags.occ_task_id_blocks::1024 808 # Occupied blocks per task id
232system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
233system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id
234system.cpu.icache.tags.age_task_id_blocks_1024::2 642 # Occupied blocks per task id
235system.cpu.icache.tags.occ_task_id_percent::1024 0.394531 # Percentage of cache occupancy per task id
236system.cpu.icache.tags.tag_accesses 453391 # Number of tag accesses
237system.cpu.icache.tags.data_accesses 453391 # Number of data accesses
238system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
239system.cpu.icache.ReadReq_hits::cpu.inst 225437 # number of ReadReq hits
240system.cpu.icache.ReadReq_hits::total 225437 # number of ReadReq hits
241system.cpu.icache.demand_hits::cpu.inst 225437 # number of demand (read+write) hits
242system.cpu.icache.demand_hits::total 225437 # number of demand (read+write) hits
243system.cpu.icache.overall_hits::cpu.inst 225437 # number of overall hits
244system.cpu.icache.overall_hits::total 225437 # number of overall hits
245system.cpu.icache.ReadReq_misses::cpu.inst 839 # number of ReadReq misses
246system.cpu.icache.ReadReq_misses::total 839 # number of ReadReq misses
247system.cpu.icache.demand_misses::cpu.inst 839 # number of demand (read+write) misses
248system.cpu.icache.demand_misses::total 839 # number of demand (read+write) misses
249system.cpu.icache.overall_misses::cpu.inst 839 # number of overall misses
250system.cpu.icache.overall_misses::total 839 # number of overall misses
251system.cpu.icache.ReadReq_miss_latency::cpu.inst 52807500 # number of ReadReq miss cycles
252system.cpu.icache.ReadReq_miss_latency::total 52807500 # number of ReadReq miss cycles
253system.cpu.icache.demand_miss_latency::cpu.inst 52807500 # number of demand (read+write) miss cycles
254system.cpu.icache.demand_miss_latency::total 52807500 # number of demand (read+write) miss cycles
255system.cpu.icache.overall_miss_latency::cpu.inst 52807500 # number of overall miss cycles
256system.cpu.icache.overall_miss_latency::total 52807500 # number of overall miss cycles
257system.cpu.icache.ReadReq_accesses::cpu.inst 226276 # number of ReadReq accesses(hits+misses)
258system.cpu.icache.ReadReq_accesses::total 226276 # number of ReadReq accesses(hits+misses)
259system.cpu.icache.demand_accesses::cpu.inst 226276 # number of demand (read+write) accesses
260system.cpu.icache.demand_accesses::total 226276 # number of demand (read+write) accesses
261system.cpu.icache.overall_accesses::cpu.inst 226276 # number of overall (read+write) accesses
262system.cpu.icache.overall_accesses::total 226276 # number of overall (read+write) accesses
263system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003708 # miss rate for ReadReq accesses
264system.cpu.icache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses
265system.cpu.icache.demand_miss_rate::cpu.inst 0.003708 # miss rate for demand accesses
266system.cpu.icache.demand_miss_rate::total 0.003708 # miss rate for demand accesses
267system.cpu.icache.overall_miss_rate::cpu.inst 0.003708 # miss rate for overall accesses
268system.cpu.icache.overall_miss_rate::total 0.003708 # miss rate for overall accesses
269system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62941.001192 # average ReadReq miss latency
270system.cpu.icache.ReadReq_avg_miss_latency::total 62941.001192 # average ReadReq miss latency
271system.cpu.icache.demand_avg_miss_latency::cpu.inst 62941.001192 # average overall miss latency
272system.cpu.icache.demand_avg_miss_latency::total 62941.001192 # average overall miss latency
273system.cpu.icache.overall_avg_miss_latency::cpu.inst 62941.001192 # average overall miss latency
274system.cpu.icache.overall_avg_miss_latency::total 62941.001192 # average overall miss latency
275system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
276system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
277system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
278system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
279system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
280system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
281system.cpu.icache.writebacks::writebacks 31 # number of writebacks
282system.cpu.icache.writebacks::total 31 # number of writebacks
283system.cpu.icache.ReadReq_mshr_misses::cpu.inst 839 # number of ReadReq MSHR misses
284system.cpu.icache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses
285system.cpu.icache.demand_mshr_misses::cpu.inst 839 # number of demand (read+write) MSHR misses
286system.cpu.icache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses
287system.cpu.icache.overall_mshr_misses::cpu.inst 839 # number of overall MSHR misses
288system.cpu.icache.overall_mshr_misses::total 839 # number of overall MSHR misses
289system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51968500 # number of ReadReq MSHR miss cycles
290system.cpu.icache.ReadReq_mshr_miss_latency::total 51968500 # number of ReadReq MSHR miss cycles
291system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51968500 # number of demand (read+write) MSHR miss cycles
292system.cpu.icache.demand_mshr_miss_latency::total 51968500 # number of demand (read+write) MSHR miss cycles
293system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51968500 # number of overall MSHR miss cycles
294system.cpu.icache.overall_mshr_miss_latency::total 51968500 # number of overall MSHR miss cycles
295system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.003708 # mshr miss rate for ReadReq accesses
296system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses
297system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.003708 # mshr miss rate for demand accesses
298system.cpu.icache.demand_mshr_miss_rate::total 0.003708 # mshr miss rate for demand accesses
299system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.003708 # mshr miss rate for overall accesses
300system.cpu.icache.overall_mshr_miss_rate::total 0.003708 # mshr miss rate for overall accesses
301system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61941.001192 # average ReadReq mshr miss latency
302system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61941.001192 # average ReadReq mshr miss latency
303system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61941.001192 # average overall mshr miss latency
304system.cpu.icache.demand_avg_mshr_miss_latency::total 61941.001192 # average overall mshr miss latency
305system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61941.001192 # average overall mshr miss latency
306system.cpu.icache.overall_avg_mshr_miss_latency::total 61941.001192 # average overall mshr miss latency
307system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
308system.cpu.l2cache.tags.replacements 0 # number of replacements
309system.cpu.l2cache.tags.tagsinuse 727.343781 # Cycle average of tags in use
310system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
311system.cpu.l2cache.tags.sampled_refs 1134 # Sample count of references to valid blocks.
312system.cpu.l2cache.tags.avg_refs 0.028219 # Average number of references to valid blocks.
313system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
314system.cpu.l2cache.tags.occ_blocks::cpu.inst 481.119804 # Average occupied blocks per requestor
315system.cpu.l2cache.tags.occ_blocks::cpu.data 246.223977 # Average occupied blocks per requestor
316system.cpu.l2cache.tags.occ_percent::cpu.inst 0.014683 # Average percentage of cache occupancy
317system.cpu.l2cache.tags.occ_percent::cpu.data 0.007514 # Average percentage of cache occupancy
318system.cpu.l2cache.tags.occ_percent::total 0.022197 # Average percentage of cache occupancy
319system.cpu.l2cache.tags.occ_task_id_blocks::1024 1134 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
321system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
322system.cpu.l2cache.tags.age_task_id_blocks_1024::2 950 # Occupied blocks per task id
323system.cpu.l2cache.tags.occ_task_id_percent::1024 0.034607 # Percentage of cache occupancy per task id
324system.cpu.l2cache.tags.tag_accesses 10462 # Number of tag accesses
325system.cpu.l2cache.tags.data_accesses 10462 # Number of data accesses
326system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
327system.cpu.l2cache.WritebackClean_hits::writebacks 31 # number of WritebackClean hits
328system.cpu.l2cache.WritebackClean_hits::total 31 # number of WritebackClean hits
329system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits
330system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits
331system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
332system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
333system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
334system.cpu.l2cache.overall_hits::total 1 # number of overall hits
335system.cpu.l2cache.ReadExReq_misses::cpu.data 207 # number of ReadExReq misses
336system.cpu.l2cache.ReadExReq_misses::total 207 # number of ReadExReq misses
337system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 838 # number of ReadCleanReq misses
338system.cpu.l2cache.ReadCleanReq_misses::total 838 # number of ReadCleanReq misses
339system.cpu.l2cache.ReadSharedReq_misses::cpu.data 89 # number of ReadSharedReq misses
340system.cpu.l2cache.ReadSharedReq_misses::total 89 # number of ReadSharedReq misses
341system.cpu.l2cache.demand_misses::cpu.inst 838 # number of demand (read+write) misses
342system.cpu.l2cache.demand_misses::cpu.data 296 # number of demand (read+write) misses
343system.cpu.l2cache.demand_misses::total 1134 # number of demand (read+write) misses
344system.cpu.l2cache.overall_misses::cpu.inst 838 # number of overall misses
345system.cpu.l2cache.overall_misses::cpu.data 296 # number of overall misses
346system.cpu.l2cache.overall_misses::total 1134 # number of overall misses
347system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12523500 # number of ReadExReq miss cycles
348system.cpu.l2cache.ReadExReq_miss_latency::total 12523500 # number of ReadExReq miss cycles
349system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 50699500 # number of ReadCleanReq miss cycles
350system.cpu.l2cache.ReadCleanReq_miss_latency::total 50699500 # number of ReadCleanReq miss cycles
351system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5384500 # number of ReadSharedReq miss cycles
352system.cpu.l2cache.ReadSharedReq_miss_latency::total 5384500 # number of ReadSharedReq miss cycles
353system.cpu.l2cache.demand_miss_latency::cpu.inst 50699500 # number of demand (read+write) miss cycles
354system.cpu.l2cache.demand_miss_latency::cpu.data 17908000 # number of demand (read+write) miss cycles
355system.cpu.l2cache.demand_miss_latency::total 68607500 # number of demand (read+write) miss cycles
356system.cpu.l2cache.overall_miss_latency::cpu.inst 50699500 # number of overall miss cycles
357system.cpu.l2cache.overall_miss_latency::cpu.data 17908000 # number of overall miss cycles
358system.cpu.l2cache.overall_miss_latency::total 68607500 # number of overall miss cycles
359system.cpu.l2cache.WritebackClean_accesses::writebacks 31 # number of WritebackClean accesses(hits+misses)
360system.cpu.l2cache.WritebackClean_accesses::total 31 # number of WritebackClean accesses(hits+misses)
361system.cpu.l2cache.ReadExReq_accesses::cpu.data 207 # number of ReadExReq accesses(hits+misses)
362system.cpu.l2cache.ReadExReq_accesses::total 207 # number of ReadExReq accesses(hits+misses)
363system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 839 # number of ReadCleanReq accesses(hits+misses)
364system.cpu.l2cache.ReadCleanReq_accesses::total 839 # number of ReadCleanReq accesses(hits+misses)
365system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 89 # number of ReadSharedReq accesses(hits+misses)
366system.cpu.l2cache.ReadSharedReq_accesses::total 89 # number of ReadSharedReq accesses(hits+misses)
367system.cpu.l2cache.demand_accesses::cpu.inst 839 # number of demand (read+write) accesses
368system.cpu.l2cache.demand_accesses::cpu.data 296 # number of demand (read+write) accesses
369system.cpu.l2cache.demand_accesses::total 1135 # number of demand (read+write) accesses
370system.cpu.l2cache.overall_accesses::cpu.inst 839 # number of overall (read+write) accesses
371system.cpu.l2cache.overall_accesses::cpu.data 296 # number of overall (read+write) accesses
372system.cpu.l2cache.overall_accesses::total 1135 # number of overall (read+write) accesses
373system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
374system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
375system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998808 # miss rate for ReadCleanReq accesses
376system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998808 # miss rate for ReadCleanReq accesses
377system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
378system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
379system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998808 # miss rate for demand accesses
380system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
381system.cpu.l2cache.demand_miss_rate::total 0.999119 # miss rate for demand accesses
382system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998808 # miss rate for overall accesses
383system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
384system.cpu.l2cache.overall_miss_rate::total 0.999119 # miss rate for overall accesses
385system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
386system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
387system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.596659 # average ReadCleanReq miss latency
388system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.596659 # average ReadCleanReq miss latency
389system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
390system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
391system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.596659 # average overall miss latency
392system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
393system.cpu.l2cache.demand_avg_miss_latency::total 60500.440917 # average overall miss latency
394system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.596659 # average overall miss latency
395system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
396system.cpu.l2cache.overall_avg_miss_latency::total 60500.440917 # average overall miss latency
397system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
398system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
399system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
400system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
401system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
402system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
403system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207 # number of ReadExReq MSHR misses
404system.cpu.l2cache.ReadExReq_mshr_misses::total 207 # number of ReadExReq MSHR misses
405system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 838 # number of ReadCleanReq MSHR misses
406system.cpu.l2cache.ReadCleanReq_mshr_misses::total 838 # number of ReadCleanReq MSHR misses
407system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 89 # number of ReadSharedReq MSHR misses
408system.cpu.l2cache.ReadSharedReq_mshr_misses::total 89 # number of ReadSharedReq MSHR misses
409system.cpu.l2cache.demand_mshr_misses::cpu.inst 838 # number of demand (read+write) MSHR misses
410system.cpu.l2cache.demand_mshr_misses::cpu.data 296 # number of demand (read+write) MSHR misses
411system.cpu.l2cache.demand_mshr_misses::total 1134 # number of demand (read+write) MSHR misses
412system.cpu.l2cache.overall_mshr_misses::cpu.inst 838 # number of overall MSHR misses
413system.cpu.l2cache.overall_mshr_misses::cpu.data 296 # number of overall MSHR misses
414system.cpu.l2cache.overall_mshr_misses::total 1134 # number of overall MSHR misses
415system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10453500 # number of ReadExReq MSHR miss cycles
416system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10453500 # number of ReadExReq MSHR miss cycles
417system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 42319500 # number of ReadCleanReq MSHR miss cycles
418system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 42319500 # number of ReadCleanReq MSHR miss cycles
419system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4494500 # number of ReadSharedReq MSHR miss cycles
420system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4494500 # number of ReadSharedReq MSHR miss cycles
421system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42319500 # number of demand (read+write) MSHR miss cycles
422system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14948000 # number of demand (read+write) MSHR miss cycles
423system.cpu.l2cache.demand_mshr_miss_latency::total 57267500 # number of demand (read+write) MSHR miss cycles
424system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42319500 # number of overall MSHR miss cycles
425system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14948000 # number of overall MSHR miss cycles
426system.cpu.l2cache.overall_mshr_miss_latency::total 57267500 # number of overall MSHR miss cycles
427system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
428system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
429system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for ReadCleanReq accesses
430system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998808 # mshr miss rate for ReadCleanReq accesses
431system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
432system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
433system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for demand accesses
434system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
435system.cpu.l2cache.demand_mshr_miss_rate::total 0.999119 # mshr miss rate for demand accesses
436system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998808 # mshr miss rate for overall accesses
437system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
438system.cpu.l2cache.overall_mshr_miss_rate::total 0.999119 # mshr miss rate for overall accesses
439system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
440system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
441system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.596659 # average ReadCleanReq mshr miss latency
442system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.596659 # average ReadCleanReq mshr miss latency
443system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
444system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
445system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.596659 # average overall mshr miss latency
446system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
447system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.440917 # average overall mshr miss latency
448system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.596659 # average overall mshr miss latency
449system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
450system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.440917 # average overall mshr miss latency
451system.cpu.toL2Bus.snoop_filter.tot_requests 1166 # Total number of requests made to the snoop filter.
452system.cpu.toL2Bus.snoop_filter.hit_single_requests 31 # Number of requests hitting in the snoop filter with a single holder of the requested data.
453system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
454system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
455system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
456system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
457system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
458system.cpu.toL2Bus.trans_dist::ReadResp 928 # Transaction distribution
459system.cpu.toL2Bus.trans_dist::WritebackClean 31 # Transaction distribution
460system.cpu.toL2Bus.trans_dist::ReadExReq 207 # Transaction distribution
461system.cpu.toL2Bus.trans_dist::ReadExResp 207 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::ReadCleanReq 839 # Transaction distribution
463system.cpu.toL2Bus.trans_dist::ReadSharedReq 89 # Transaction distribution
464system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1709 # Packet count per connected master and slave (bytes)
465system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 592 # Packet count per connected master and slave (bytes)
466system.cpu.toL2Bus.pkt_count::total 2301 # Packet count per connected master and slave (bytes)
467system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 55680 # Cumulative packet size per connected master and slave (bytes)
468system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes)
469system.cpu.toL2Bus.pkt_size::total 74624 # Cumulative packet size per connected master and slave (bytes)
470system.cpu.toL2Bus.snoops 0 # Total snoops (count)
471system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
472system.cpu.toL2Bus.snoop_fanout::samples 1135 # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
475system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::0 1135 100.00% 100.00% # Request fanout histogram
477system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
478system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
479system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
482system.cpu.toL2Bus.snoop_fanout::total 1135 # Request fanout histogram
483system.cpu.toL2Bus.reqLayer0.occupancy 614000 # Layer occupancy (ticks)
484system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
485system.cpu.toL2Bus.respLayer0.occupancy 1258500 # Layer occupancy (ticks)
486system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
487system.cpu.toL2Bus.respLayer1.occupancy 444000 # Layer occupancy (ticks)
488system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
489system.membus.snoop_filter.tot_requests 1134 # Total number of requests made to the snoop filter.
490system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
491system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
492system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
493system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
494system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
495system.membus.pwrStateResidencyTicks::UNDEFINED 385535500 # Cumulative time (in ticks) in various power states
496system.membus.trans_dist::ReadResp 927 # Transaction distribution
497system.membus.trans_dist::ReadExReq 207 # Transaction distribution
498system.membus.trans_dist::ReadExResp 207 # Transaction distribution
499system.membus.trans_dist::ReadSharedReq 927 # Transaction distribution
500system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2268 # Packet count per connected master and slave (bytes)
501system.membus.pkt_count::total 2268 # Packet count per connected master and slave (bytes)
502system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72576 # Cumulative packet size per connected master and slave (bytes)
503system.membus.pkt_size::total 72576 # Cumulative packet size per connected master and slave (bytes)
504system.membus.snoops 0 # Total snoops (count)
505system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
506system.membus.snoop_fanout::samples 1134 # Request fanout histogram
507system.membus.snoop_fanout::mean 0 # Request fanout histogram
508system.membus.snoop_fanout::stdev 0 # Request fanout histogram
509system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
510system.membus.snoop_fanout::0 1134 100.00% 100.00% # Request fanout histogram
511system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
512system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
513system.membus.snoop_fanout::min_value 0 # Request fanout histogram
514system.membus.snoop_fanout::max_value 0 # Request fanout histogram
515system.membus.snoop_fanout::total 1134 # Request fanout histogram
516system.membus.reqLayer0.occupancy 1134500 # Layer occupancy (ticks)
517system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
518system.membus.respLayer1.occupancy 5670000 # Layer occupancy (ticks)
519system.membus.respLayer1.utilization 1.5 # Layer utilization (%)
| 3sim_seconds 0.000755
4sim_ticks 755664500
5final_tick 755664500
6sim_freq 1000000000000
7host_inst_rate 3560
8host_op_rate 3571
9host_tick_rate 6467277
10host_mem_usage 270048
11host_seconds 116.84
12sim_insts 416024
13sim_ops 417277
14system.voltage_domain.voltage 1
15system.clk_domain.clock 1000
16system.physmem.pwrStateResidencyTicks::UNDEFINED 755664500
17system.physmem.bytes_read::cpu.inst 67712
18system.physmem.bytes_read::cpu.data 33920
19system.physmem.bytes_read::total 101632
20system.physmem.bytes_inst_read::cpu.inst 67712
21system.physmem.bytes_inst_read::total 67712
22system.physmem.num_reads::cpu.inst 1058
23system.physmem.num_reads::cpu.data 530
24system.physmem.num_reads::total 1588
25system.physmem.bw_read::cpu.inst 89605903
26system.physmem.bw_read::cpu.data 44887645
27system.physmem.bw_read::total 134493548
28system.physmem.bw_inst_read::cpu.inst 89605903
29system.physmem.bw_inst_read::total 89605903
30system.physmem.bw_total::cpu.inst 89605903
31system.physmem.bw_total::cpu.data 44887645
32system.physmem.bw_total::total 134493548
33system.pwrStateResidencyTicks::UNDEFINED 755664500
34system.cpu_clk_domain.clock 500
35system.cpu.dtb.read_hits 0
36system.cpu.dtb.read_misses 0
37system.cpu.dtb.read_accesses 0
38system.cpu.dtb.write_hits 0
39system.cpu.dtb.write_misses 0
40system.cpu.dtb.write_accesses 0
41system.cpu.dtb.hits 0
42system.cpu.dtb.misses 0
43system.cpu.dtb.accesses 0
44system.cpu.itb.read_hits 0
45system.cpu.itb.read_misses 0
46system.cpu.itb.read_accesses 0
47system.cpu.itb.write_hits 0
48system.cpu.itb.write_misses 0
49system.cpu.itb.write_accesses 0
50system.cpu.itb.hits 0
51system.cpu.itb.misses 0
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422system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.945179
423system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500
424system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500
425system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.945179
426system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500
427system.cpu.l2cache.demand_avg_miss_latency::total 60500.629722
428system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.945179
429system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500
430system.cpu.l2cache.overall_avg_miss_latency::total 60500.629722
431system.cpu.l2cache.blocked_cycles::no_mshrs 0
432system.cpu.l2cache.blocked_cycles::no_targets 0
433system.cpu.l2cache.blocked::no_mshrs 0
434system.cpu.l2cache.blocked::no_targets 0
435system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
436system.cpu.l2cache.avg_blocked_cycles::no_targets nan
437system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 227
438system.cpu.l2cache.ReadExReq_mshr_misses::total 227
439system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1058
440system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1058
441system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 303
442system.cpu.l2cache.ReadSharedReq_mshr_misses::total 303
443system.cpu.l2cache.demand_mshr_misses::cpu.inst 1058
444system.cpu.l2cache.demand_mshr_misses::cpu.data 530
445system.cpu.l2cache.demand_mshr_misses::total 1588
446system.cpu.l2cache.overall_mshr_misses::cpu.inst 1058
447system.cpu.l2cache.overall_mshr_misses::cpu.data 530
448system.cpu.l2cache.overall_mshr_misses::total 1588
449system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11463500
450system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11463500
451system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 53430000
452system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 53430000
453system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15301500
454system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15301500
455system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 53430000
456system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26765000
457system.cpu.l2cache.demand_mshr_miss_latency::total 80195000
458system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 53430000
459system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26765000
460system.cpu.l2cache.overall_mshr_miss_latency::total 80195000
461system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
462system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
463system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.999055
464system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.999055
465system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1
466system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1
467system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.999055
468system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1
469system.cpu.l2cache.demand_mshr_miss_rate::total 0.999370
470system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.999055
471system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
472system.cpu.l2cache.overall_mshr_miss_rate::total 0.999370
473system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500
474system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500
475system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.945179
476system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.945179
477system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500
478system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500
479system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.945179
480system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500
481system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.629722
482system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.945179
483system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500
484system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.629722
485system.cpu.toL2Bus.snoop_filter.tot_requests 1646
486system.cpu.toL2Bus.snoop_filter.hit_single_requests 57
487system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
488system.cpu.toL2Bus.snoop_filter.tot_snoops 0
489system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
490system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
491system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 755664500
492system.cpu.toL2Bus.trans_dist::ReadResp 1362
493system.cpu.toL2Bus.trans_dist::WritebackDirty 2
494system.cpu.toL2Bus.trans_dist::WritebackClean 55
495system.cpu.toL2Bus.trans_dist::ReadExReq 227
496system.cpu.toL2Bus.trans_dist::ReadExResp 227
497system.cpu.toL2Bus.trans_dist::ReadCleanReq 1059
498system.cpu.toL2Bus.trans_dist::ReadSharedReq 303
499system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2173
500system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1062
501system.cpu.toL2Bus.pkt_count::total 3235
502system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71296
503system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 34048
504system.cpu.toL2Bus.pkt_size::total 105344
505system.cpu.toL2Bus.snoops 0
506system.cpu.toL2Bus.snoopTraffic 0
507system.cpu.toL2Bus.snoop_fanout::samples 1589
508system.cpu.toL2Bus.snoop_fanout::mean 0
509system.cpu.toL2Bus.snoop_fanout::stdev -0
510system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
511system.cpu.toL2Bus.snoop_fanout::0 1589 100.00% 100.00%
512system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
513system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
514system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
515system.cpu.toL2Bus.snoop_fanout::min_value 0
516system.cpu.toL2Bus.snoop_fanout::max_value 0
517system.cpu.toL2Bus.snoop_fanout::total 1589
518system.cpu.toL2Bus.reqLayer0.occupancy 880000
519system.cpu.toL2Bus.reqLayer0.utilization 0.1
520system.cpu.toL2Bus.respLayer0.occupancy 1588500
521system.cpu.toL2Bus.respLayer0.utilization 0.2
522system.cpu.toL2Bus.respLayer1.occupancy 795000
523system.cpu.toL2Bus.respLayer1.utilization 0.1
524system.membus.snoop_filter.tot_requests 1588
525system.membus.snoop_filter.hit_single_requests 0
526system.membus.snoop_filter.hit_multi_requests 0
527system.membus.snoop_filter.tot_snoops 0
528system.membus.snoop_filter.hit_single_snoops 0
529system.membus.snoop_filter.hit_multi_snoops 0
530system.membus.pwrStateResidencyTicks::UNDEFINED 755664500
531system.membus.trans_dist::ReadResp 1361
532system.membus.trans_dist::ReadExReq 227
533system.membus.trans_dist::ReadExResp 227
534system.membus.trans_dist::ReadSharedReq 1361
535system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3176
536system.membus.pkt_count::total 3176
537system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 101632
538system.membus.pkt_size::total 101632
539system.membus.snoops 0
540system.membus.snoopTraffic 0
541system.membus.snoop_fanout::samples 1588
542system.membus.snoop_fanout::mean 0
543system.membus.snoop_fanout::stdev -0
544system.membus.snoop_fanout::underflows 0 0.00% 0.00%
545system.membus.snoop_fanout::0 1588 100.00% 100.00%
546system.membus.snoop_fanout::1 0 0.00% 100.00%
547system.membus.snoop_fanout::overflows 0 0.00% 100.00%
548system.membus.snoop_fanout::min_value 0
549system.membus.snoop_fanout::max_value 0
550system.membus.snoop_fanout::total 1588
551system.membus.reqLayer0.occupancy 1589000
552system.membus.reqLayer0.utilization 0.2
553system.membus.respLayer1.occupancy 7940000
554system.membus.respLayer1.utilization 1.0
|
520
521---------- End Simulation Statistics ----------
| 555
556---------- End Simulation Statistics ----------
|