1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000113 # Number of seconds simulated 4sim_ticks 113137000 # Number of ticks simulated 5final_tick 113137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 28615 # Simulator instruction rate (inst/s) 8host_op_rate 28615 # Simulator op (including micro ops) rate (op/s) --- 42 unchanged lines hidden (view full) --- 51system.cpu.itb.read_misses 0 # DTB read misses 52system.cpu.itb.read_accesses 0 # DTB read accesses 53system.cpu.itb.write_hits 0 # DTB write hits 54system.cpu.itb.write_misses 0 # DTB write misses 55system.cpu.itb.write_accesses 0 # DTB write accesses 56system.cpu.itb.hits 0 # DTB hits 57system.cpu.itb.misses 0 # DTB misses 58system.cpu.itb.accesses 0 # DTB accesses |
59system.cpu.workload.numSyscalls 115 # Number of system calls |
60system.cpu.pwrStateResidencyTicks::ON 113137000 # Cumulative time (in ticks) in various power states 61system.cpu.numCycles 226275 # number of cpu cycles simulated 62system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 63system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 64system.cpu.committedInsts 226159 # Number of instructions committed 65system.cpu.committedOps 226159 # Number of ops (including micro ops) committed 66system.cpu.num_int_alu_accesses 225992 # Number of integer alu accesses 67system.cpu.num_fp_alu_accesses 862 # Number of float alu accesses --- 86 unchanged lines hidden --- |