Cross Reference: /gem5/tests/quick/se/02.insttest/ref/riscv/linux-rv64f/o3-timing/stats.txt

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stats.txt (11955:1170d039b31e)	stats.txt (12137:d877205ec1bc)
1 2---------- Begin Simulation Statistics ----------	1 2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000113 # Number of seconds simulated 4sim_ticks 113383000 # Number of ticks simulated 5final_tick 113383000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 167766 # Simulator instruction rate (inst/s) 8host_op_rate 167765 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 84106882 # Simulator tick rate (ticks/s) 10host_mem_usage 263760 # Number of bytes of host memory used 11host_seconds 1.35 # Real time elapsed on the host 12sim_insts 226159 # Number of instructions simulated 13sim_ops 226159 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 65920 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory 19system.physmem.bytes_read::total 85184 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 65920 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 65920 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 1030 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 1331 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 581392272 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 169902014 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 751294286 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 581392272 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 581392272 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 581392272 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 169902014 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 751294286 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 1331 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 1331 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 85184 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 85184 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 174 # Per bank write bursts 46system.physmem.perBankRdBursts::1 18 # Per bank write bursts 47system.physmem.perBankRdBursts::2 15 # Per bank write bursts 48system.physmem.perBankRdBursts::3 82 # Per bank write bursts 49system.physmem.perBankRdBursts::4 194 # Per bank write bursts 50system.physmem.perBankRdBursts::5 254 # Per bank write bursts 51system.physmem.perBankRdBursts::6 22 # Per bank write bursts 52system.physmem.perBankRdBursts::7 4 # Per bank write bursts 53system.physmem.perBankRdBursts::8 25 # Per bank write bursts 54system.physmem.perBankRdBursts::9 103 # Per bank write bursts 55system.physmem.perBankRdBursts::10 150 # Per bank write bursts 56system.physmem.perBankRdBursts::11 145 # Per bank write bursts 57system.physmem.perBankRdBursts::12 50 # Per bank write bursts 58system.physmem.perBankRdBursts::13 52 # Per bank write bursts 59system.physmem.perBankRdBursts::14 14 # Per bank write bursts 60system.physmem.perBankRdBursts::15 29 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 113277000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 1331 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 810 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 212 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 390.641509 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 252.461189 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 341.274727 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 49 23.11% 23.11% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 43 20.28% 43.40% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 38 17.92% 61.32% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 18 8.49% 69.81% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 13 6.13% 75.94% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 8 3.77% 79.72% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 6 2.83% 82.55% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 5 2.36% 84.91% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 32 15.09% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 212 # Bytes accessed per row activation 204system.physmem.totQLat 17606250 # Total ticks spent queuing 205system.physmem.totMemAccLat 42562500 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 6655000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 13227.84 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 31977.84 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 751.29 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 751.29 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 5.87 # Data bus utilization in percentage 216system.physmem.busUtilRead 5.87 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.58 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 1107 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 83.17 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 85106.69 # Average gap between requests 225system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 771120 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 390885 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 5447820 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 9821100 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 199200 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 40147950 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 1260960 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 66643995 # Total energy per rank (pJ) 237system.physmem_0.averagePower 587.773777 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 90897000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 89500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 3640000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 3282750 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 18328750 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 88042000 # Time in different power states 245system.physmem_1.actEnergy 828240 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 413655 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 4055520 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 7853460 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 220320 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 41175660 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 2031360 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 65183175 # Total energy per rank (pJ) 256system.physmem_1.averagePower 574.889920 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 95520250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 174500 # Time in different power states 259system.physmem_1.memoryStateTime::REF 3640000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 5288750 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 13978500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 90301250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 78097 # Number of BP lookups 266system.cpu.branchPred.condPredicted 47857 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 4973 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 59652 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 36130 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 60.567961 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 14779 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 6634 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 8145 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 2576 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.write_accesses 0 # DTB write accesses 285system.cpu.dtb.hits 0 # DTB hits 286system.cpu.dtb.misses 0 # DTB misses 287system.cpu.dtb.accesses 0 # DTB accesses 288system.cpu.itb.read_hits 0 # DTB read hits 289system.cpu.itb.read_misses 0 # DTB read misses 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.numSyscalls 115 # Number of system calls 298system.cpu.pwrStateResidencyTicks::ON 113383000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 226767 # number of cpu cycles simulated 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.fetch.icacheStallCycles 73708 # Number of cycles fetch is stalled on an Icache miss 303system.cpu.fetch.Insts 336580 # Number of instructions fetch has processed 304system.cpu.fetch.Branches 78097 # Number of branches that fetch encountered 305system.cpu.fetch.predictedBranches 42764 # Number of branches that fetch has predicted taken 306system.cpu.fetch.Cycles 87814 # Number of cycles fetch has run and was not squashing or blocked 307system.cpu.fetch.SquashCycles 10240 # Number of cycles fetch has spent squashing 308system.cpu.fetch.MiscStallCycles 400 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 309system.cpu.fetch.IcacheWaitRetryStallCycles 177 # Number of stall cycles due to full MSHR 310system.cpu.fetch.CacheLines 60514 # Number of cache lines fetched 311system.cpu.fetch.IcacheSquashes 2320 # Number of outstanding Icache misses that were squashed 312system.cpu.fetch.rateDist::samples 167219 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::mean 2.012810 # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::stdev 2.818543 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::0 90347 54.03% 54.03% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::1 11793 7.05% 61.08% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::2 13895 8.31% 69.39% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::3 11689 6.99% 76.38% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::4 5745 3.44% 79.82% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::5 6911 4.13% 83.95% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::6 2836 1.70% 85.65% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::7 4645 2.78% 88.42% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::8 19358 11.58% 100.00% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::total 167219 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.branchRate 0.344393 # Number of branch fetches per cycle 330system.cpu.fetch.rate 1.484255 # Number of inst fetches per cycle 331system.cpu.decode.IdleCycles 72610 # Number of cycles decode is idle 332system.cpu.decode.BlockedCycles 18818 # Number of cycles decode is blocked 333system.cpu.decode.RunCycles 70228 # Number of cycles decode is running 334system.cpu.decode.UnblockCycles 1268 # Number of cycles decode is unblocking 335system.cpu.decode.SquashCycles 4295 # Number of cycles decode is squashing 336system.cpu.decode.BranchResolved 35338 # Number of times decode resolved a branch 337system.cpu.decode.BranchMispred 921 # Number of times decode detected a branch misprediction 338system.cpu.decode.DecodedInsts 310147 # Number of instructions handled by decode 339system.cpu.decode.SquashedInsts 2548 # Number of squashed instructions handled by decode 340system.cpu.rename.SquashCycles 4295 # Number of cycles rename is squashing 341system.cpu.rename.IdleCycles 75141 # Number of cycles rename is idle 342system.cpu.rename.BlockCycles 8221 # Number of cycles rename is blocking 343system.cpu.rename.serializeStallCycles 3161 # count of cycles rename stalled for serializing inst 344system.cpu.rename.RunCycles 68810 # Number of cycles rename is running 345system.cpu.rename.UnblockCycles 7591 # Number of cycles rename is unblocking 346system.cpu.rename.RenamedInsts 298778 # Number of instructions processed by rename 347system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full 348system.cpu.rename.IQFullEvents 69 # Number of times rename has blocked due to IQ full 349system.cpu.rename.LQFullEvents 743 # Number of times rename has blocked due to LQ full 350system.cpu.rename.SQFullEvents 6500 # Number of times rename has blocked due to SQ full 351system.cpu.rename.RenamedOperands 207984 # Number of destination operands rename has renamed 352system.cpu.rename.RenameLookups 389381 # Number of register rename lookups that rename has made 353system.cpu.rename.int_rename_lookups 387034 # Number of integer rename lookups 354system.cpu.rename.fp_rename_lookups 2347 # Number of floating rename lookups 355system.cpu.rename.CommittedMaps 155141 # Number of HB maps that are committed 356system.cpu.rename.UndoneMaps 52843 # Number of HB maps that are undone due to squashing 357system.cpu.rename.serializingInsts 133 # count of serializing insts renamed 358system.cpu.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed 359system.cpu.rename.skidInsts 3092 # count of insts added to the skid buffer 360system.cpu.memDep0.insertedLoads 62122 # Number of loads inserted to the mem dependence unit. 361system.cpu.memDep0.insertedStores 43306 # Number of stores inserted to the mem dependence unit. 362system.cpu.memDep0.conflictingLoads 1169 # Number of conflicting loads. 363system.cpu.memDep0.conflictingStores 342 # Number of conflicting stores. 364system.cpu.iq.iqInstsAdded 273422 # Number of instructions added to the IQ (excludes non-spec) 365system.cpu.iq.iqNonSpecInstsAdded 166 # Number of non-speculative instructions added to the IQ 366system.cpu.iq.iqInstsIssued 261550 # Number of instructions issued 367system.cpu.iq.iqSquashedInstsIssued 571 # Number of squashed instructions issued 368system.cpu.iq.iqSquashedInstsExamined 47419 # Number of squashed instructions iterated over during squash; mainly for profiling 369system.cpu.iq.iqSquashedOperandsExamined 26031 # Number of squashed operands that are examined and possibly removed from graph 370system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed 371system.cpu.iq.issued_per_cycle::samples 167219 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::mean 1.564117 # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::stdev 1.884378 # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::0 67857 40.58% 40.58% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::1 36223 21.66% 62.24% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::2 23953 14.32% 76.57% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::3 10828 6.48% 83.04% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::4 10307 6.16% 89.21% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::5 8097 4.84% 94.05% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::6 7553 4.52% 98.56% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::7 1302 0.78% 99.34% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::8 1099 0.66% 100.00% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::total 167219 # Number of insts issued each cycle 388system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 389system.cpu.iq.fu_full::IntAlu 716 10.62% 10.62% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntMult 0 0.00% 10.62% # attempts to use FU when none available 391system.cpu.iq.fu_full::IntDiv 0 0.00% 10.62% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.62% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.62% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.62% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatMult 0 0.00% 10.62% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available 397system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.62% # attempts to use FU when none available 398system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.62% # attempts to use FU when none available 399system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.62% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.62% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.62% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.62% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.62% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.62% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.62% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdMult 0 0.00% 10.62% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.62% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdShift 0 0.00% 10.62% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.62% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.62% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.62% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.62% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.62% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.62% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.62% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.62% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.62% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.62% # attempts to use FU when none available 420system.cpu.iq.fu_full::MemRead 2981 44.22% 54.84% # attempts to use FU when none available 421system.cpu.iq.fu_full::MemWrite 2955 43.84% 98.68% # attempts to use FU when none available 422system.cpu.iq.fu_full::FloatMemRead 88 1.31% 99.99% # attempts to use FU when none available 423system.cpu.iq.fu_full::FloatMemWrite 1 0.01% 100.00% # attempts to use FU when none available 424system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 425system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 426system.cpu.iq.FU_type_0::No_OpClass 117 0.04% 0.04% # Type of FU issued 427system.cpu.iq.FU_type_0::IntAlu 159688 61.05% 61.10% # Type of FU issued 428system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.22% # Type of FU issued 429system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.24% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatAdd 170 0.06% 61.31% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.35% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.37% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.39% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.39% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.39% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.39% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.39% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.39% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.39% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.39% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.39% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.39% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.39% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.39% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.39% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.39% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.39% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.39% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.39% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.39% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.39% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.39% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.39% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.39% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued 458system.cpu.iq.FU_type_0::MemRead 59226 22.64% 84.04% # Type of FU issued 459system.cpu.iq.FU_type_0::MemWrite 40848 15.62% 99.65% # Type of FU issued 460system.cpu.iq.FU_type_0::FloatMemRead 727 0.28% 99.93% # Type of FU issued 461system.cpu.iq.FU_type_0::FloatMemWrite 179 0.07% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 464system.cpu.iq.FU_type_0::total 261550 # Type of FU issued 465system.cpu.iq.rate 1.153387 # Inst issue rate 466system.cpu.iq.fu_busy_cnt 6741 # FU busy when requested 467system.cpu.iq.fu_busy_rate 0.025773 # FU busy rate (busy events/executed inst) 468system.cpu.iq.int_inst_queue_reads 694940 # Number of integer instruction queue reads 469system.cpu.iq.int_inst_queue_writes 318115 # Number of integer instruction queue writes 470system.cpu.iq.int_inst_queue_wakeup_accesses 249943 # Number of integer instruction queue wakeup accesses 471system.cpu.iq.fp_inst_queue_reads 2691 # Number of floating instruction queue reads 472system.cpu.iq.fp_inst_queue_writes 2944 # Number of floating instruction queue writes 473system.cpu.iq.fp_inst_queue_wakeup_accesses 1007 # Number of floating instruction queue wakeup accesses 474system.cpu.iq.int_alu_accesses 266784 # Number of integer alu accesses 475system.cpu.iq.fp_alu_accesses 1390 # Number of floating point alu accesses 476system.cpu.iew.lsq.thread0.forwLoads 5624 # Number of loads that had data forwarded from stores 477system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 478system.cpu.iew.lsq.thread0.squashedLoads 10411 # Number of loads squashed 479system.cpu.iew.lsq.thread0.ignoredResponses 34 # Number of memory responses ignored because the instruction is squashed 480system.cpu.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations 481system.cpu.iew.lsq.thread0.squashedStores 6077 # Number of stores squashed 482system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 483system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 484system.cpu.iew.lsq.thread0.rescheduledLoads 9 # Number of loads that were rescheduled 485system.cpu.iew.lsq.thread0.cacheBlocked 117 # Number of times an access to memory failed due to the cache being blocked 486system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 487system.cpu.iew.iewSquashCycles 4295 # Number of cycles IEW is squashing 488system.cpu.iew.iewBlockCycles 4907 # Number of cycles IEW is blocking 489system.cpu.iew.iewUnblockCycles 918 # Number of cycles IEW is unblocking 490system.cpu.iew.iewDispatchedInsts 273579 # Number of instructions dispatched to IQ 491system.cpu.iew.iewDispSquashedInsts 3363 # Number of squashed instructions skipped by dispatch 492system.cpu.iew.iewDispLoadInsts 62122 # Number of dispatched load instructions 493system.cpu.iew.iewDispStoreInsts 43306 # Number of dispatched store instructions 494system.cpu.iew.iewDispNonSpecInsts 157 # Number of dispatched non-speculative instructions 495system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 496system.cpu.iew.iewLSQFullEvents 908 # Number of times the LSQ has become full, causing a stall 497system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations 498system.cpu.iew.predictedTakenIncorrect 1293 # Number of branches that were predicted taken incorrectly 499system.cpu.iew.predictedNotTakenIncorrect 3450 # Number of branches that were predicted not taken incorrectly 500system.cpu.iew.branchMispredicts 4743 # Number of branch mispredicts detected at execute 501system.cpu.iew.iewExecutedInsts 254044 # Number of executed instructions 502system.cpu.iew.iewExecLoadInsts 58349 # Number of load instructions executed 503system.cpu.iew.iewExecSquashedInsts 7506 # Number of squashed instructions skipped in execute 504system.cpu.iew.exec_swp 0 # number of swp insts executed 505system.cpu.iew.exec_nop 0 # number of nop insts executed 506system.cpu.iew.exec_refs 98069 # number of memory reference insts executed 507system.cpu.iew.exec_branches 57083 # Number of branches executed 508system.cpu.iew.exec_stores 39720 # Number of stores executed 509system.cpu.iew.exec_rate 1.120286 # Inst execution rate 510system.cpu.iew.wb_sent 252158 # cumulative count of insts sent to commit 511system.cpu.iew.wb_count 250950 # cumulative count of insts written-back 512system.cpu.iew.wb_producers 95653 # num instructions producing a value 513system.cpu.iew.wb_consumers 131997 # num instructions consuming a value 514system.cpu.iew.wb_rate 1.106643 # insts written-back per cycle 515system.cpu.iew.wb_fanout 0.724660 # average fanout of values written-back 516system.cpu.commit.commitSquashedInsts 47451 # The number of squashed insts skipped by commit 517system.cpu.commit.commitNonSpecStalls 117 # The number of times commit has been forced to stall to communicate backwards 518system.cpu.commit.branchMispredicts 4148 # The number of times a branch was mispredicted 519system.cpu.commit.committed_per_cycle::samples 158171 # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::mean 1.429839 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::stdev 2.156696 # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::0 83501 52.79% 52.79% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::1 25809 16.32% 69.11% # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::2 14383 9.09% 78.20% # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::3 10997 6.95% 85.15% # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::4 5860 3.70% 88.86% # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::5 5977 3.78% 92.64% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::6 3309 2.09% 94.73% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::7 1266 0.80% 95.53% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::8 7069 4.47% 100.00% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::total 158171 # Number of insts commited each cycle 536system.cpu.commit.committedInsts 226159 # Number of instructions committed 537system.cpu.commit.committedOps 226159 # Number of ops (including micro ops) committed 538system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 539system.cpu.commit.refs 88940 # Number of memory references committed 540system.cpu.commit.loads 51711 # Number of loads committed 541system.cpu.commit.membars 0 # Number of memory barriers committed 542system.cpu.commit.branches 50405 # Number of branches committed 543system.cpu.commit.fp_insts 862 # Number of committed floating point instructions. 544system.cpu.commit.int_insts 225991 # Number of committed integer instructions. 545system.cpu.commit.function_calls 16616 # Number of function calls committed. 546system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction 547system.cpu.commit.op_class_0::IntAlu 136540 60.37% 60.37% # Class of committed instruction 548system.cpu.commit.op_class_0::IntMult 325 0.14% 60.52% # Class of committed instruction 549system.cpu.commit.op_class_0::IntDiv 40 0.02% 60.54% # Class of committed instruction 550system.cpu.commit.op_class_0::FloatAdd 104 0.05% 60.58% # Class of committed instruction 551system.cpu.commit.op_class_0::FloatCmp 119 0.05% 60.63% # Class of committed instruction 552system.cpu.commit.op_class_0::FloatCvt 43 0.02% 60.65% # Class of committed instruction 553system.cpu.commit.op_class_0::FloatMult 30 0.01% 60.67% # Class of committed instruction 554system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 60.67% # Class of committed instruction 555system.cpu.commit.op_class_0::FloatDiv 11 0.00% 60.67% # Class of committed instruction 556system.cpu.commit.op_class_0::FloatMisc 0 0.00% 60.67% # Class of committed instruction 557system.cpu.commit.op_class_0::FloatSqrt 5 0.00% 60.67% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdAdd 0 0.00% 60.67% # Class of committed instruction 559system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 60.67% # Class of committed instruction 560system.cpu.commit.op_class_0::SimdAlu 0 0.00% 60.67% # Class of committed instruction 561system.cpu.commit.op_class_0::SimdCmp 0 0.00% 60.67% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdCvt 0 0.00% 60.67% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdMisc 0 0.00% 60.67% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdMult 0 0.00% 60.67% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 60.67% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdShift 0 0.00% 60.67% # Class of committed instruction 567system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 60.67% # Class of committed instruction 568system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 60.67% # Class of committed instruction 569system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 60.67% # Class of committed instruction 570system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 60.67% # Class of committed instruction 571system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 60.67% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 60.67% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 60.67% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 60.67% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 60.67% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 60.67% # Class of committed instruction 577system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 60.67% # Class of committed instruction 578system.cpu.commit.op_class_0::MemRead 51297 22.68% 83.36% # Class of committed instruction 579system.cpu.commit.op_class_0::MemWrite 37093 16.40% 99.76% # Class of committed instruction 580system.cpu.commit.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction 581system.cpu.commit.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction 582system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 583system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 584system.cpu.commit.op_class_0::total 226159 # Class of committed instruction 585system.cpu.commit.bw_lim_events 7069 # number cycles where commit BW limit reached 586system.cpu.rob.rob_reads 423217 # The number of ROB reads 587system.cpu.rob.rob_writes 556357 # The number of ROB writes 588system.cpu.timesIdled 459 # Number of times that the entire CPU went into an idle state and unscheduled itself 589system.cpu.idleCycles 59548 # Total number of cycles that the CPU has spent unscheduled due to idling 590system.cpu.committedInsts 226159 # Number of Instructions Simulated 591system.cpu.committedOps 226159 # Number of Ops (including micro ops) Simulated 592system.cpu.cpi 1.002688 # CPI: Cycles Per Instruction 593system.cpu.cpi_total 1.002688 # CPI: Total CPI of All Threads 594system.cpu.ipc 0.997319 # IPC: Instructions Per Cycle 595system.cpu.ipc_total 0.997319 # IPC: Total IPC of All Threads 596system.cpu.int_regfile_reads 329254 # number of integer regfile reads 597system.cpu.int_regfile_writes 174794 # number of integer regfile writes 598system.cpu.fp_regfile_reads 878 # number of floating regfile reads 599system.cpu.fp_regfile_writes 754 # number of floating regfile writes 600system.cpu.misc_regfile_reads 446 # number of misc regfile reads 601system.cpu.misc_regfile_writes 313 # number of misc regfile writes 602system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states 603system.cpu.dcache.tags.replacements 0 # number of replacements 604system.cpu.dcache.tags.tagsinuse 244.658569 # Cycle average of tags in use 605system.cpu.dcache.tags.total_refs 87565 # Total number of references to valid blocks. 606system.cpu.dcache.tags.sampled_refs 301 # Sample count of references to valid blocks. 607system.cpu.dcache.tags.avg_refs 290.913621 # Average number of references to valid blocks. 608system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 609system.cpu.dcache.tags.occ_blocks::cpu.data 244.658569 # Average occupied blocks per requestor 610system.cpu.dcache.tags.occ_percent::cpu.data 0.059731 # Average percentage of cache occupancy 611system.cpu.dcache.tags.occ_percent::total 0.059731 # Average percentage of cache occupancy 612system.cpu.dcache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id 613system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 614system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 615system.cpu.dcache.tags.age_task_id_blocks_1024::2 194 # Occupied blocks per task id 616system.cpu.dcache.tags.occ_task_id_percent::1024 0.073486 # Percentage of cache occupancy per task id 617system.cpu.dcache.tags.tag_accesses 179301 # Number of tag accesses 618system.cpu.dcache.tags.data_accesses 179301 # Number of data accesses 619system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states 620system.cpu.dcache.ReadReq_hits::cpu.data 51833 # number of ReadReq hits 621system.cpu.dcache.ReadReq_hits::total 51833 # number of ReadReq hits 622system.cpu.dcache.WriteReq_hits::cpu.data 35732 # number of WriteReq hits 623system.cpu.dcache.WriteReq_hits::total 35732 # number of WriteReq hits 624system.cpu.dcache.demand_hits::cpu.data 87565 # number of demand (read+write) hits 625system.cpu.dcache.demand_hits::total 87565 # number of demand (read+write) hits 626system.cpu.dcache.overall_hits::cpu.data 87565 # number of overall hits 627system.cpu.dcache.overall_hits::total 87565 # number of overall hits 628system.cpu.dcache.ReadReq_misses::cpu.data 438 # number of ReadReq misses 629system.cpu.dcache.ReadReq_misses::total 438 # number of ReadReq misses 630system.cpu.dcache.WriteReq_misses::cpu.data 1497 # number of WriteReq misses 631system.cpu.dcache.WriteReq_misses::total 1497 # number of WriteReq misses 632system.cpu.dcache.demand_misses::cpu.data 1935 # number of demand (read+write) misses 633system.cpu.dcache.demand_misses::total 1935 # number of demand (read+write) misses 634system.cpu.dcache.overall_misses::cpu.data 1935 # number of overall misses 635system.cpu.dcache.overall_misses::total 1935 # number of overall misses 636system.cpu.dcache.ReadReq_miss_latency::cpu.data 36015000 # number of ReadReq miss cycles 637system.cpu.dcache.ReadReq_miss_latency::total 36015000 # number of ReadReq miss cycles 638system.cpu.dcache.WriteReq_miss_latency::cpu.data 97868425 # number of WriteReq miss cycles 639system.cpu.dcache.WriteReq_miss_latency::total 97868425 # number of WriteReq miss cycles 640system.cpu.dcache.demand_miss_latency::cpu.data 133883425 # number of demand (read+write) miss cycles 641system.cpu.dcache.demand_miss_latency::total 133883425 # number of demand (read+write) miss cycles 642system.cpu.dcache.overall_miss_latency::cpu.data 133883425 # number of overall miss cycles 643system.cpu.dcache.overall_miss_latency::total 133883425 # number of overall miss cycles 644system.cpu.dcache.ReadReq_accesses::cpu.data 52271 # number of ReadReq accesses(hits+misses) 645system.cpu.dcache.ReadReq_accesses::total 52271 # number of ReadReq accesses(hits+misses) 646system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) 647system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) 648system.cpu.dcache.demand_accesses::cpu.data 89500 # number of demand (read+write) accesses 649system.cpu.dcache.demand_accesses::total 89500 # number of demand (read+write) accesses 650system.cpu.dcache.overall_accesses::cpu.data 89500 # number of overall (read+write) accesses 651system.cpu.dcache.overall_accesses::total 89500 # number of overall (read+write) accesses 652system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008379 # miss rate for ReadReq accesses 653system.cpu.dcache.ReadReq_miss_rate::total 0.008379 # miss rate for ReadReq accesses 654system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040211 # miss rate for WriteReq accesses 655system.cpu.dcache.WriteReq_miss_rate::total 0.040211 # miss rate for WriteReq accesses 656system.cpu.dcache.demand_miss_rate::cpu.data 0.021620 # miss rate for demand accesses 657system.cpu.dcache.demand_miss_rate::total 0.021620 # miss rate for demand accesses 658system.cpu.dcache.overall_miss_rate::cpu.data 0.021620 # miss rate for overall accesses 659system.cpu.dcache.overall_miss_rate::total 0.021620 # miss rate for overall accesses 660system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82226.027397 # average ReadReq miss latency 661system.cpu.dcache.ReadReq_avg_miss_latency::total 82226.027397 # average ReadReq miss latency 662system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65376.369405 # average WriteReq miss latency 663system.cpu.dcache.WriteReq_avg_miss_latency::total 65376.369405 # average WriteReq miss latency 664system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency 665system.cpu.dcache.demand_avg_miss_latency::total 69190.400517 # average overall miss latency 666system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency 667system.cpu.dcache.overall_avg_miss_latency::total 69190.400517 # average overall miss latency 668system.cpu.dcache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked 669system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu.dcache.blocked::no_mshrs 79 # number of cycles access was blocked 671system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.253165 # average number of cycles each access was blocked 673system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu.dcache.ReadReq_mshr_hits::cpu.data 341 # number of ReadReq MSHR hits 675system.cpu.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1293 # number of WriteReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::total 1293 # number of WriteReq MSHR hits 678system.cpu.dcache.demand_mshr_hits::cpu.data 1634 # number of demand (read+write) MSHR hits 679system.cpu.dcache.demand_mshr_hits::total 1634 # number of demand (read+write) MSHR hits 680system.cpu.dcache.overall_mshr_hits::cpu.data 1634 # number of overall MSHR hits 681system.cpu.dcache.overall_mshr_hits::total 1634 # number of overall MSHR hits 682system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses 683system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses 684system.cpu.dcache.WriteReq_mshr_misses::cpu.data 204 # number of WriteReq MSHR misses 685system.cpu.dcache.WriteReq_mshr_misses::total 204 # number of WriteReq MSHR misses 686system.cpu.dcache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses 687system.cpu.dcache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses 688system.cpu.dcache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses 689system.cpu.dcache.overall_mshr_misses::total 301 # number of overall MSHR misses 690system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8546500 # number of ReadReq MSHR miss cycles 691system.cpu.dcache.ReadReq_mshr_miss_latency::total 8546500 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17206500 # number of WriteReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::total 17206500 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25753000 # number of demand (read+write) MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::total 25753000 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25753000 # number of overall MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::total 25753000 # number of overall MSHR miss cycles 698system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001856 # mshr miss rate for ReadReq accesses 699system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001856 # mshr miss rate for ReadReq accesses 700system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005480 # mshr miss rate for WriteReq accesses 701system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005480 # mshr miss rate for WriteReq accesses 702system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003363 # mshr miss rate for demand accesses 703system.cpu.dcache.demand_mshr_miss_rate::total 0.003363 # mshr miss rate for demand accesses 704system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003363 # mshr miss rate for overall accesses 705system.cpu.dcache.overall_mshr_miss_rate::total 0.003363 # mshr miss rate for overall accesses 706system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88108.247423 # average ReadReq mshr miss latency 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88108.247423 # average ReadReq mshr miss latency 708system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84345.588235 # average WriteReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84345.588235 # average WriteReq mshr miss latency 710system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85558.139535 # average overall mshr miss latency 711system.cpu.dcache.demand_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency 712system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85558.139535 # average overall mshr miss latency 713system.cpu.dcache.overall_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency 714system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states 715system.cpu.icache.tags.replacements 70 # number of replacements 716system.cpu.icache.tags.tagsinuse 535.835535 # Cycle average of tags in use 717system.cpu.icache.tags.total_refs 59155 # Total number of references to valid blocks. 718system.cpu.icache.tags.sampled_refs 1035 # Sample count of references to valid blocks. 719system.cpu.icache.tags.avg_refs 57.154589 # Average number of references to valid blocks. 720system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 721system.cpu.icache.tags.occ_blocks::cpu.inst 535.835535 # Average occupied blocks per requestor 722system.cpu.icache.tags.occ_percent::cpu.inst 0.261638 # Average percentage of cache occupancy 723system.cpu.icache.tags.occ_percent::total 0.261638 # Average percentage of cache occupancy 724system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id 725system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 726system.cpu.icache.tags.age_task_id_blocks_1024::1 738 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id 728system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id 729system.cpu.icache.tags.tag_accesses 122053 # Number of tag accesses 730system.cpu.icache.tags.data_accesses 122053 # Number of data accesses 731system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states 732system.cpu.icache.ReadReq_hits::cpu.inst 59155 # number of ReadReq hits 733system.cpu.icache.ReadReq_hits::total 59155 # number of ReadReq hits 734system.cpu.icache.demand_hits::cpu.inst 59155 # number of demand (read+write) hits 735system.cpu.icache.demand_hits::total 59155 # number of demand (read+write) hits 736system.cpu.icache.overall_hits::cpu.inst 59155 # number of overall hits 737system.cpu.icache.overall_hits::total 59155 # number of overall hits 738system.cpu.icache.ReadReq_misses::cpu.inst 1354 # number of ReadReq misses 739system.cpu.icache.ReadReq_misses::total 1354 # number of ReadReq misses 740system.cpu.icache.demand_misses::cpu.inst 1354 # number of demand (read+write) misses 741system.cpu.icache.demand_misses::total 1354 # number of demand (read+write) misses 742system.cpu.icache.overall_misses::cpu.inst 1354 # number of overall misses 743system.cpu.icache.overall_misses::total 1354 # number of overall misses 744system.cpu.icache.ReadReq_miss_latency::cpu.inst 109143498 # number of ReadReq miss cycles 745system.cpu.icache.ReadReq_miss_latency::total 109143498 # number of ReadReq miss cycles 746system.cpu.icache.demand_miss_latency::cpu.inst 109143498 # number of demand (read+write) miss cycles 747system.cpu.icache.demand_miss_latency::total 109143498 # number of demand (read+write) miss cycles 748system.cpu.icache.overall_miss_latency::cpu.inst 109143498 # number of overall miss cycles 749system.cpu.icache.overall_miss_latency::total 109143498 # number of overall miss cycles 750system.cpu.icache.ReadReq_accesses::cpu.inst 60509 # number of ReadReq accesses(hits+misses) 751system.cpu.icache.ReadReq_accesses::total 60509 # number of ReadReq accesses(hits+misses) 752system.cpu.icache.demand_accesses::cpu.inst 60509 # number of demand (read+write) accesses 753system.cpu.icache.demand_accesses::total 60509 # number of demand (read+write) accesses 754system.cpu.icache.overall_accesses::cpu.inst 60509 # number of overall (read+write) accesses 755system.cpu.icache.overall_accesses::total 60509 # number of overall (read+write) accesses 756system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022377 # miss rate for ReadReq accesses 757system.cpu.icache.ReadReq_miss_rate::total 0.022377 # miss rate for ReadReq accesses 758system.cpu.icache.demand_miss_rate::cpu.inst 0.022377 # miss rate for demand accesses 759system.cpu.icache.demand_miss_rate::total 0.022377 # miss rate for demand accesses 760system.cpu.icache.overall_miss_rate::cpu.inst 0.022377 # miss rate for overall accesses 761system.cpu.icache.overall_miss_rate::total 0.022377 # miss rate for overall accesses 762system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80608.196455 # average ReadReq miss latency 763system.cpu.icache.ReadReq_avg_miss_latency::total 80608.196455 # average ReadReq miss latency 764system.cpu.icache.demand_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency 765system.cpu.icache.demand_avg_miss_latency::total 80608.196455 # average overall miss latency 766system.cpu.icache.overall_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency 767system.cpu.icache.overall_avg_miss_latency::total 80608.196455 # average overall miss latency 768system.cpu.icache.blocked_cycles::no_mshrs 2475 # number of cycles access was blocked 769system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 770system.cpu.icache.blocked::no_mshrs 34 # number of cycles access was blocked 771system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 772system.cpu.icache.avg_blocked_cycles::no_mshrs 72.794118 # average number of cycles each access was blocked 773system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 774system.cpu.icache.writebacks::writebacks 70 # number of writebacks 775system.cpu.icache.writebacks::total 70 # number of writebacks 776system.cpu.icache.ReadReq_mshr_hits::cpu.inst 319 # number of ReadReq MSHR hits 777system.cpu.icache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits 778system.cpu.icache.demand_mshr_hits::cpu.inst 319 # number of demand (read+write) MSHR hits 779system.cpu.icache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits 780system.cpu.icache.overall_mshr_hits::cpu.inst 319 # number of overall MSHR hits 781system.cpu.icache.overall_mshr_hits::total 319 # number of overall MSHR hits 782system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035 # number of ReadReq MSHR misses 783system.cpu.icache.ReadReq_mshr_misses::total 1035 # number of ReadReq MSHR misses 784system.cpu.icache.demand_mshr_misses::cpu.inst 1035 # number of demand (read+write) MSHR misses 785system.cpu.icache.demand_mshr_misses::total 1035 # number of demand (read+write) MSHR misses 786system.cpu.icache.overall_mshr_misses::cpu.inst 1035 # number of overall MSHR misses 787system.cpu.icache.overall_mshr_misses::total 1035 # number of overall MSHR misses 788system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86827498 # number of ReadReq MSHR miss cycles 789system.cpu.icache.ReadReq_mshr_miss_latency::total 86827498 # number of ReadReq MSHR miss cycles 790system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86827498 # number of demand (read+write) MSHR miss cycles 791system.cpu.icache.demand_mshr_miss_latency::total 86827498 # number of demand (read+write) MSHR miss cycles 792system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86827498 # number of overall MSHR miss cycles 793system.cpu.icache.overall_mshr_miss_latency::total 86827498 # number of overall MSHR miss cycles 794system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for ReadReq accesses 795system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017105 # mshr miss rate for ReadReq accesses 796system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for demand accesses 797system.cpu.icache.demand_mshr_miss_rate::total 0.017105 # mshr miss rate for demand accesses 798system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for overall accesses 799system.cpu.icache.overall_mshr_miss_rate::total 0.017105 # mshr miss rate for overall accesses 800system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83891.302415 # average ReadReq mshr miss latency 801system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83891.302415 # average ReadReq mshr miss latency 802system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency 803system.cpu.icache.demand_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency 804system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency 805system.cpu.icache.overall_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency 806system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states 807system.cpu.l2cache.tags.replacements 0 # number of replacements 808system.cpu.l2cache.tags.tagsinuse 808.901136 # Cycle average of tags in use 809system.cpu.l2cache.tags.total_refs 72 # Total number of references to valid blocks. 810system.cpu.l2cache.tags.sampled_refs 1331 # Sample count of references to valid blocks. 811system.cpu.l2cache.tags.avg_refs 0.054095 # Average number of references to valid blocks. 812system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 813system.cpu.l2cache.tags.occ_blocks::cpu.inst 564.214692 # Average occupied blocks per requestor 814system.cpu.l2cache.tags.occ_blocks::cpu.data 244.686444 # Average occupied blocks per requestor 815system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017218 # Average percentage of cache occupancy 816system.cpu.l2cache.tags.occ_percent::cpu.data 0.007467 # Average percentage of cache occupancy 817system.cpu.l2cache.tags.occ_percent::total 0.024686 # Average percentage of cache occupancy 818system.cpu.l2cache.tags.occ_task_id_blocks::1024 1331 # Occupied blocks per task id 819system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 820system.cpu.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id 821system.cpu.l2cache.tags.age_task_id_blocks_1024::2 338 # Occupied blocks per task id 822system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040619 # Percentage of cache occupancy per task id 823system.cpu.l2cache.tags.tag_accesses 12555 # Number of tag accesses 824system.cpu.l2cache.tags.data_accesses 12555 # Number of data accesses 825system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states 826system.cpu.l2cache.WritebackClean_hits::writebacks 70 # number of WritebackClean hits 827system.cpu.l2cache.WritebackClean_hits::total 70 # number of WritebackClean hits 828system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 829system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 830system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 831system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 832system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 833system.cpu.l2cache.overall_hits::total 2 # number of overall hits 834system.cpu.l2cache.ReadExReq_misses::cpu.data 204 # number of ReadExReq misses 835system.cpu.l2cache.ReadExReq_misses::total 204 # number of ReadExReq misses 836system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1030 # number of ReadCleanReq misses 837system.cpu.l2cache.ReadCleanReq_misses::total 1030 # number of ReadCleanReq misses 838system.cpu.l2cache.ReadSharedReq_misses::cpu.data 97 # number of ReadSharedReq misses 839system.cpu.l2cache.ReadSharedReq_misses::total 97 # number of ReadSharedReq misses 840system.cpu.l2cache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses 841system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses 842system.cpu.l2cache.demand_misses::total 1331 # number of demand (read+write) misses 843system.cpu.l2cache.overall_misses::cpu.inst 1030 # number of overall misses 844system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses 845system.cpu.l2cache.overall_misses::total 1331 # number of overall misses 846system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16900000 # number of ReadExReq miss cycles 847system.cpu.l2cache.ReadExReq_miss_latency::total 16900000 # number of ReadExReq miss cycles 848system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 85245000 # number of ReadCleanReq miss cycles 849system.cpu.l2cache.ReadCleanReq_miss_latency::total 85245000 # number of ReadCleanReq miss cycles 850system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8401000 # number of ReadSharedReq miss cycles 851system.cpu.l2cache.ReadSharedReq_miss_latency::total 8401000 # number of ReadSharedReq miss cycles 852system.cpu.l2cache.demand_miss_latency::cpu.inst 85245000 # number of demand (read+write) miss cycles 853system.cpu.l2cache.demand_miss_latency::cpu.data 25301000 # number of demand (read+write) miss cycles 854system.cpu.l2cache.demand_miss_latency::total 110546000 # number of demand (read+write) miss cycles 855system.cpu.l2cache.overall_miss_latency::cpu.inst 85245000 # number of overall miss cycles 856system.cpu.l2cache.overall_miss_latency::cpu.data 25301000 # number of overall miss cycles 857system.cpu.l2cache.overall_miss_latency::total 110546000 # number of overall miss cycles 858system.cpu.l2cache.WritebackClean_accesses::writebacks 70 # number of WritebackClean accesses(hits+misses) 859system.cpu.l2cache.WritebackClean_accesses::total 70 # number of WritebackClean accesses(hits+misses) 860system.cpu.l2cache.ReadExReq_accesses::cpu.data 204 # number of ReadExReq accesses(hits+misses) 861system.cpu.l2cache.ReadExReq_accesses::total 204 # number of ReadExReq accesses(hits+misses) 862system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1032 # number of ReadCleanReq accesses(hits+misses) 863system.cpu.l2cache.ReadCleanReq_accesses::total 1032 # number of ReadCleanReq accesses(hits+misses) 864system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses) 865system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses) 866system.cpu.l2cache.demand_accesses::cpu.inst 1032 # number of demand (read+write) accesses 867system.cpu.l2cache.demand_accesses::cpu.data 301 # number of demand (read+write) accesses 868system.cpu.l2cache.demand_accesses::total 1333 # number of demand (read+write) accesses 869system.cpu.l2cache.overall_accesses::cpu.inst 1032 # number of overall (read+write) accesses 870system.cpu.l2cache.overall_accesses::cpu.data 301 # number of overall (read+write) accesses 871system.cpu.l2cache.overall_accesses::total 1333 # number of overall (read+write) accesses 872system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 873system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 874system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998062 # miss rate for ReadCleanReq accesses 875system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998062 # miss rate for ReadCleanReq accesses 876system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 877system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 878system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998062 # miss rate for demand accesses 879system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 880system.cpu.l2cache.demand_miss_rate::total 0.998500 # miss rate for demand accesses 881system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998062 # miss rate for overall accesses 882system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 883system.cpu.l2cache.overall_miss_rate::total 0.998500 # miss rate for overall accesses 884system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82843.137255 # average ReadExReq miss latency 885system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82843.137255 # average ReadExReq miss latency 886system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82762.135922 # average ReadCleanReq miss latency 887system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82762.135922 # average ReadCleanReq miss latency 888system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86608.247423 # average ReadSharedReq miss latency 889system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86608.247423 # average ReadSharedReq miss latency 890system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82762.135922 # average overall miss latency 891system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84056.478405 # average overall miss latency 892system.cpu.l2cache.demand_avg_miss_latency::total 83054.845980 # average overall miss latency 893system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82762.135922 # average overall miss latency 894system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84056.478405 # average overall miss latency 895system.cpu.l2cache.overall_avg_miss_latency::total 83054.845980 # average overall miss latency 896system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 897system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 898system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 899system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 900system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 901system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 902system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 204 # number of ReadExReq MSHR misses 903system.cpu.l2cache.ReadExReq_mshr_misses::total 204 # number of ReadExReq MSHR misses 904system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1030 # number of ReadCleanReq MSHR misses 905system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1030 # number of ReadCleanReq MSHR misses 906system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 97 # number of ReadSharedReq MSHR misses 907system.cpu.l2cache.ReadSharedReq_mshr_misses::total 97 # number of ReadSharedReq MSHR misses 908system.cpu.l2cache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses 909system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses 910system.cpu.l2cache.demand_mshr_misses::total 1331 # number of demand (read+write) MSHR misses 911system.cpu.l2cache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses 912system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses 913system.cpu.l2cache.overall_mshr_misses::total 1331 # number of overall MSHR misses 914system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14860000 # number of ReadExReq MSHR miss cycles 915system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14860000 # number of ReadExReq MSHR miss cycles 916system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74945000 # number of ReadCleanReq MSHR miss cycles 917system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74945000 # number of ReadCleanReq MSHR miss cycles 918system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7431000 # number of ReadSharedReq MSHR miss cycles 919system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7431000 # number of ReadSharedReq MSHR miss cycles 920system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74945000 # number of demand (read+write) MSHR miss cycles 921system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22291000 # number of demand (read+write) MSHR miss cycles 922system.cpu.l2cache.demand_mshr_miss_latency::total 97236000 # number of demand (read+write) MSHR miss cycles 923system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74945000 # number of overall MSHR miss cycles 924system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22291000 # number of overall MSHR miss cycles 925system.cpu.l2cache.overall_mshr_miss_latency::total 97236000 # number of overall MSHR miss cycles 926system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 927system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 928system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for ReadCleanReq accesses 929system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998062 # mshr miss rate for ReadCleanReq accesses 930system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 931system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 932system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for demand accesses 933system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 934system.cpu.l2cache.demand_mshr_miss_rate::total 0.998500 # mshr miss rate for demand accesses 935system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for overall accesses 936system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 937system.cpu.l2cache.overall_mshr_miss_rate::total 0.998500 # mshr miss rate for overall accesses 938system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72843.137255 # average ReadExReq mshr miss latency 939system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72843.137255 # average ReadExReq mshr miss latency 940system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72762.135922 # average ReadCleanReq mshr miss latency 941system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72762.135922 # average ReadCleanReq mshr miss latency 942system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76608.247423 # average ReadSharedReq mshr miss latency 943system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76608.247423 # average ReadSharedReq mshr miss latency 944system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency 945system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency 946system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency 947system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency 948system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency 949system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency 950system.cpu.toL2Bus.snoop_filter.tot_requests 1406 # Total number of requests made to the snoop filter. 951system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data. 952system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 953system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 954system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 955system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 956system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states 957system.cpu.toL2Bus.trans_dist::ReadResp 1132 # Transaction distribution 958system.cpu.toL2Bus.trans_dist::WritebackClean 70 # Transaction distribution 959system.cpu.toL2Bus.trans_dist::ReadExReq 204 # Transaction distribution 960system.cpu.toL2Bus.trans_dist::ReadExResp 204 # Transaction distribution 961system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035 # Transaction distribution 962system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution 963system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2137 # Packet count per connected master and slave (bytes) 964system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 602 # Packet count per connected master and slave (bytes) 965system.cpu.toL2Bus.pkt_count::total 2739 # Packet count per connected master and slave (bytes) 966system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70528 # Cumulative packet size per connected master and slave (bytes) 967system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes) 968system.cpu.toL2Bus.pkt_size::total 89792 # Cumulative packet size per connected master and slave (bytes) 969system.cpu.toL2Bus.snoops 3 # Total snoops (count) 970system.cpu.toL2Bus.snoopTraffic 192 # Total snoop traffic (bytes) 971system.cpu.toL2Bus.snoop_fanout::samples 1336 # Request fanout histogram 972system.cpu.toL2Bus.snoop_fanout::mean 0.002246 # Request fanout histogram 973system.cpu.toL2Bus.snoop_fanout::stdev 0.047351 # Request fanout histogram 974system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 975system.cpu.toL2Bus.snoop_fanout::0 1333 99.78% 99.78% # Request fanout histogram 976system.cpu.toL2Bus.snoop_fanout::1 3 0.22% 100.00% # Request fanout histogram 977system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 978system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 979system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 980system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 981system.cpu.toL2Bus.snoop_fanout::total 1336 # Request fanout histogram 982system.cpu.toL2Bus.reqLayer0.occupancy 773000 # Layer occupancy (ticks) 983system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 984system.cpu.toL2Bus.respLayer0.occupancy 1552500 # Layer occupancy (ticks) 985system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 986system.cpu.toL2Bus.respLayer1.occupancy 451500 # Layer occupancy (ticks) 987system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 988system.membus.snoop_filter.tot_requests 1331 # Total number of requests made to the snoop filter. 989system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 990system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 991system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 992system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 993system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 994system.membus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states 995system.membus.trans_dist::ReadResp 1127 # Transaction distribution 996system.membus.trans_dist::ReadExReq 204 # Transaction distribution 997system.membus.trans_dist::ReadExResp 204 # Transaction distribution 998system.membus.trans_dist::ReadSharedReq 1127 # Transaction distribution 999system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2662 # Packet count per connected master and slave (bytes) 1000system.membus.pkt_count::total 2662 # Packet count per connected master and slave (bytes) 1001system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85184 # Cumulative packet size per connected master and slave (bytes) 1002system.membus.pkt_size::total 85184 # Cumulative packet size per connected master and slave (bytes) 1003system.membus.snoops 0 # Total snoops (count) 1004system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 1005system.membus.snoop_fanout::samples 1331 # Request fanout histogram 1006system.membus.snoop_fanout::mean 0 # Request fanout histogram 1007system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1008system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1009system.membus.snoop_fanout::0 1331 100.00% 100.00% # Request fanout histogram 1010system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1011system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1012system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1013system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1014system.membus.snoop_fanout::total 1331 # Request fanout histogram 1015system.membus.reqLayer0.occupancy 1624000 # Layer occupancy (ticks) 1016system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 1017system.membus.respLayer1.occupancy 7014000 # Layer occupancy (ticks) 1018system.membus.respLayer1.utilization 6.2 # Layer utilization (%)	3sim_seconds 0.000334 4sim_ticks 334241000 5final_tick 334241000 6sim_freq 1000000000000 7host_inst_rate 3258 8host_op_rate 3268 9host_tick_rate 2618086 10host_mem_usage 272352 11host_seconds 127.66 12sim_insts 416024 13sim_ops 417277 14system.voltage_domain.voltage 1 15system.clk_domain.clock 1000 16system.physmem.pwrStateResidencyTicks::UNDEFINED 334241000 17system.physmem.bytes_read::cpu.inst 79616 18system.physmem.bytes_read::cpu.data 34432 19system.physmem.bytes_read::total 114048 20system.physmem.bytes_inst_read::cpu.inst 79616 21system.physmem.bytes_inst_read::total 79616 22system.physmem.num_reads::cpu.inst 1244 23system.physmem.num_reads::cpu.data 538 24system.physmem.num_reads::total 1782 25system.physmem.bw_read::cpu.inst 238199383 26system.physmem.bw_read::cpu.data 103015488 27system.physmem.bw_read::total 341214871 28system.physmem.bw_inst_read::cpu.inst 238199383 29system.physmem.bw_inst_read::total 238199383 30system.physmem.bw_total::cpu.inst 238199383 31system.physmem.bw_total::cpu.data 103015488 32system.physmem.bw_total::total 341214871 33system.physmem.readReqs 1782 34system.physmem.writeReqs 0 35system.physmem.readBursts 1782 36system.physmem.writeBursts 0 37system.physmem.bytesReadDRAM 114048 38system.physmem.bytesReadWrQ 0 39system.physmem.bytesWritten 0 40system.physmem.bytesReadSys 114048 41system.physmem.bytesWrittenSys 0 42system.physmem.servicedByWrQ 0 43system.physmem.mergedWrBursts 0 44system.physmem.neitherReadNorWriteReqs 0 45system.physmem.perBankRdBursts::0 238 46system.physmem.perBankRdBursts::1 261 47system.physmem.perBankRdBursts::2 164 48system.physmem.perBankRdBursts::3 171 49system.physmem.perBankRdBursts::4 146 50system.physmem.perBankRdBursts::5 102 51system.physmem.perBankRdBursts::6 103 52system.physmem.perBankRdBursts::7 59 53system.physmem.perBankRdBursts::8 59 54system.physmem.perBankRdBursts::9 52 55system.physmem.perBankRdBursts::10 21 56system.physmem.perBankRdBursts::11 42 57system.physmem.perBankRdBursts::12 76 58system.physmem.perBankRdBursts::13 78 59system.physmem.perBankRdBursts::14 92 60system.physmem.perBankRdBursts::15 118 61system.physmem.perBankWrBursts::0 0 62system.physmem.perBankWrBursts::1 0 63system.physmem.perBankWrBursts::2 0 64system.physmem.perBankWrBursts::3 0 65system.physmem.perBankWrBursts::4 0 66system.physmem.perBankWrBursts::5 0 67system.physmem.perBankWrBursts::6 0 68system.physmem.perBankWrBursts::7 0 69system.physmem.perBankWrBursts::8 0 70system.physmem.perBankWrBursts::9 0 71system.physmem.perBankWrBursts::10 0 72system.physmem.perBankWrBursts::11 0 73system.physmem.perBankWrBursts::12 0 74system.physmem.perBankWrBursts::13 0 75system.physmem.perBankWrBursts::14 0 76system.physmem.perBankWrBursts::15 0 77system.physmem.numRdRetry 0 78system.physmem.numWrRetry 0 79system.physmem.totGap 334109500 80system.physmem.readPktSize::0 0 81system.physmem.readPktSize::1 0 82system.physmem.readPktSize::2 0 83system.physmem.readPktSize::3 0 84system.physmem.readPktSize::4 0 85system.physmem.readPktSize::5 0 86system.physmem.readPktSize::6 1782 87system.physmem.writePktSize::0 0 88system.physmem.writePktSize::1 0 89system.physmem.writePktSize::2 0 90system.physmem.writePktSize::3 0 91system.physmem.writePktSize::4 0 92system.physmem.writePktSize::5 0 93system.physmem.writePktSize::6 0 94system.physmem.rdQLenPdf::0 1136 95system.physmem.rdQLenPdf::1 450 96system.physmem.rdQLenPdf::2 141 97system.physmem.rdQLenPdf::3 42 98system.physmem.rdQLenPdf::4 11 99system.physmem.rdQLenPdf::5 2 100system.physmem.rdQLenPdf::6 0 101system.physmem.rdQLenPdf::7 0 102system.physmem.rdQLenPdf::8 0 103system.physmem.rdQLenPdf::9 0 104system.physmem.rdQLenPdf::10 0 105system.physmem.rdQLenPdf::11 0 106system.physmem.rdQLenPdf::12 0 107system.physmem.rdQLenPdf::13 0 108system.physmem.rdQLenPdf::14 0 109system.physmem.rdQLenPdf::15 0 110system.physmem.rdQLenPdf::16 0 111system.physmem.rdQLenPdf::17 0 112system.physmem.rdQLenPdf::18 0 113system.physmem.rdQLenPdf::19 0 114system.physmem.rdQLenPdf::20 0 115system.physmem.rdQLenPdf::21 0 116system.physmem.rdQLenPdf::22 0 117system.physmem.rdQLenPdf::23 0 118system.physmem.rdQLenPdf::24 0 119system.physmem.rdQLenPdf::25 0 120system.physmem.rdQLenPdf::26 0 121system.physmem.rdQLenPdf::27 0 122system.physmem.rdQLenPdf::28 0 123system.physmem.rdQLenPdf::29 0 124system.physmem.rdQLenPdf::30 0 125system.physmem.rdQLenPdf::31 0 126system.physmem.wrQLenPdf::0 0 127system.physmem.wrQLenPdf::1 0 128system.physmem.wrQLenPdf::2 0 129system.physmem.wrQLenPdf::3 0 130system.physmem.wrQLenPdf::4 0 131system.physmem.wrQLenPdf::5 0 132system.physmem.wrQLenPdf::6 0 133system.physmem.wrQLenPdf::7 0 134system.physmem.wrQLenPdf::8 0 135system.physmem.wrQLenPdf::9 0 136system.physmem.wrQLenPdf::10 0 137system.physmem.wrQLenPdf::11 0 138system.physmem.wrQLenPdf::12 0 139system.physmem.wrQLenPdf::13 0 140system.physmem.wrQLenPdf::14 0 141system.physmem.wrQLenPdf::15 0 142system.physmem.wrQLenPdf::16 0 143system.physmem.wrQLenPdf::17 0 144system.physmem.wrQLenPdf::18 0 145system.physmem.wrQLenPdf::19 0 146system.physmem.wrQLenPdf::20 0 147system.physmem.wrQLenPdf::21 0 148system.physmem.wrQLenPdf::22 0 149system.physmem.wrQLenPdf::23 0 150system.physmem.wrQLenPdf::24 0 151system.physmem.wrQLenPdf::25 0 152system.physmem.wrQLenPdf::26 0 153system.physmem.wrQLenPdf::27 0 154system.physmem.wrQLenPdf::28 0 155system.physmem.wrQLenPdf::29 0 156system.physmem.wrQLenPdf::30 0 157system.physmem.wrQLenPdf::31 0 158system.physmem.wrQLenPdf::32 0 159system.physmem.wrQLenPdf::33 0 160system.physmem.wrQLenPdf::34 0 161system.physmem.wrQLenPdf::35 0 162system.physmem.wrQLenPdf::36 0 163system.physmem.wrQLenPdf::37 0 164system.physmem.wrQLenPdf::38 0 165system.physmem.wrQLenPdf::39 0 166system.physmem.wrQLenPdf::40 0 167system.physmem.wrQLenPdf::41 0 168system.physmem.wrQLenPdf::42 0 169system.physmem.wrQLenPdf::43 0 170system.physmem.wrQLenPdf::44 0 171system.physmem.wrQLenPdf::45 0 172system.physmem.wrQLenPdf::46 0 173system.physmem.wrQLenPdf::47 0 174system.physmem.wrQLenPdf::48 0 175system.physmem.wrQLenPdf::49 0 176system.physmem.wrQLenPdf::50 0 177system.physmem.wrQLenPdf::51 0 178system.physmem.wrQLenPdf::52 0 179system.physmem.wrQLenPdf::53 0 180system.physmem.wrQLenPdf::54 0 181system.physmem.wrQLenPdf::55 0 182system.physmem.wrQLenPdf::56 0 183system.physmem.wrQLenPdf::57 0 184system.physmem.wrQLenPdf::58 0 185system.physmem.wrQLenPdf::59 0 186system.physmem.wrQLenPdf::60 0 187system.physmem.wrQLenPdf::61 0 188system.physmem.wrQLenPdf::62 0 189system.physmem.wrQLenPdf::63 0 190system.physmem.bytesPerActivate::samples 400 191system.physmem.bytesPerActivate::mean 278.239999 192system.physmem.bytesPerActivate::gmean 189.218763 193system.physmem.bytesPerActivate::stdev 254.162780 194system.physmem.bytesPerActivate::0-127 113 28.24% 28.24% 195system.physmem.bytesPerActivate::128-255 118 29.49% 57.74% 196system.physmem.bytesPerActivate::256-383 52 12.99% 70.74% 197system.physmem.bytesPerActivate::384-511 42 10.49% 81.24% 198system.physmem.bytesPerActivate::512-639 33 8.24% 89.49% 199system.physmem.bytesPerActivate::640-767 10 2.49% 91.99% 200system.physmem.bytesPerActivate::768-895 7 1.74% 93.74% 201system.physmem.bytesPerActivate::896-1023 11 2.74% 96.49% 202system.physmem.bytesPerActivate::1024-1151 14 3.49% 99.99% 203system.physmem.bytesPerActivate::total 400 204system.physmem.totQLat 28596250 205system.physmem.totMemAccLat 62008750 206system.physmem.totBusLat 8910000 207system.physmem.avgQLat 16047.27 208system.physmem.avgBusLat 5000.00 209system.physmem.avgMemAccLat 34797.27 210system.physmem.avgRdBW 341.21 211system.physmem.avgWrBW 0.00 212system.physmem.avgRdBWSys 341.21 213system.physmem.avgWrBWSys 0.00 214system.physmem.peakBW 12800.00 215system.physmem.busUtil 2.66 216system.physmem.busUtilRead 2.66 217system.physmem.busUtilWrite 0.00 218system.physmem.avgRdQLen 1.38 219system.physmem.avgWrQLen 0.00 220system.physmem.readRowHits 1368 221system.physmem.writeRowHits 0 222system.physmem.readRowHitRate 76.76 223system.physmem.writeRowHitRate nan 224system.physmem.avgGap 187491.30 225system.physmem.pageHitRate 76.76 226system.physmem_0.actEnergy 1927800 227system.physmem_0.preEnergy 998085 228system.physmem_0.readEnergy 8882160 229system.physmem_0.writeEnergy 0 230system.physmem_0.refreshEnergy 25814880 231system.physmem_0.actBackEnergy 18293580 232system.physmem_0.preBackEnergy 540000 233system.physmem_0.actPowerDownEnergy 129050280 234system.physmem_0.prePowerDownEnergy 3729600 235system.physmem_0.selfRefreshEnergy 0 236system.physmem_0.totalEnergy 189236385 237system.physmem_0.averagePower 566.167057 238system.physmem_0.totalIdleTime 292641750 239system.physmem_0.memoryStateTime::IDLE 245500 240system.physmem_0.memoryStateTime::REF 10920000 241system.physmem_0.memoryStateTime::SREF 0 242system.physmem_0.memoryStateTime::PRE_PDN 9705500 243system.physmem_0.memoryStateTime::ACT 30338500 244system.physmem_0.memoryStateTime::ACT_PDN 283031500 245system.physmem_1.actEnergy 1028160 246system.physmem_1.preEnergy 519915 247system.physmem_1.readEnergy 3841320 248system.physmem_1.writeEnergy 0 249system.physmem_1.refreshEnergy 11678160 250system.physmem_1.actBackEnergy 8555700 251system.physmem_1.preBackEnergy 555360 252system.physmem_1.actPowerDownEnergy 38406030 253system.physmem_1.prePowerDownEnergy 10018560 254system.physmem_1.selfRefreshEnergy 50549220 255system.physmem_1.totalEnergy 125152425 256system.physmem_1.averagePower 374.437401 257system.physmem_1.totalIdleTime 313185500 258system.physmem_1.memoryStateTime::IDLE 973000 259system.physmem_1.memoryStateTime::REF 4958000 260system.physmem_1.memoryStateTime::SREF 203719000 261system.physmem_1.memoryStateTime::PRE_PDN 26090000 262system.physmem_1.memoryStateTime::ACT 14271500 263system.physmem_1.memoryStateTime::ACT_PDN 84229500 264system.pwrStateResidencyTicks::UNDEFINED 334241000 265system.cpu.branchPred.lookups 127435 266system.cpu.branchPred.condPredicted 89833 267system.cpu.branchPred.condIncorrect 23395 268system.cpu.branchPred.BTBLookups 81108 269system.cpu.branchPred.BTBHits 45160 270system.cpu.branchPred.BTBCorrect 0 271system.cpu.branchPred.BTBHitPct 55.678847 272system.cpu.branchPred.usedRAS 0 273system.cpu.branchPred.RASInCorrect 0 274system.cpu.branchPred.indirectLookups 25902 275system.cpu.branchPred.indirectHits 14811 276system.cpu.branchPred.indirectMisses 11091 277system.cpu.branchPredindirectMispredicted 5072 278system.cpu_clk_domain.clock 500 279system.cpu.dtb.read_hits 0 280system.cpu.dtb.read_misses 0 281system.cpu.dtb.read_accesses 0 282system.cpu.dtb.write_hits 0 283system.cpu.dtb.write_misses 0 284system.cpu.dtb.write_accesses 0 285system.cpu.dtb.hits 0 286system.cpu.dtb.misses 0 287system.cpu.dtb.accesses 0 288system.cpu.itb.read_hits 0 289system.cpu.itb.read_misses 0 290system.cpu.itb.read_accesses 0 291system.cpu.itb.write_hits 0 292system.cpu.itb.write_misses 0 293system.cpu.itb.write_accesses 0 294system.cpu.itb.hits 0 295system.cpu.itb.misses 0 296system.cpu.itb.accesses 0 297system.cpu.workload.numSyscalls 216 298system.cpu.pwrStateResidencyTicks::ON 334241000 299system.cpu.numCycles 668483 300system.cpu.numWorkItemsStarted 0 301system.cpu.numWorkItemsCompleted 0 302system.cpu.fetch.icacheStallCycles 128666 303system.cpu.fetch.Insts 570376 304system.cpu.fetch.Branches 127435 305system.cpu.fetch.predictedBranches 59971 306system.cpu.fetch.Cycles 411263 307system.cpu.fetch.SquashCycles 47272 308system.cpu.fetch.MiscStallCycles 19 309system.cpu.fetch.PendingTrapStallCycles 76 310system.cpu.fetch.IcacheWaitRetryStallCycles 83 311system.cpu.fetch.CacheLines 90304 312system.cpu.fetch.IcacheSquashes 2386 313system.cpu.fetch.rateDist::samples 563743 314system.cpu.fetch.rateDist::mean 1.014057 315system.cpu.fetch.rateDist::stdev 0.982669 316system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% 317system.cpu.fetch.rateDist::0 163182 28.94% 28.94% 318system.cpu.fetch.rateDist::1 291750 51.75% 80.69% 319system.cpu.fetch.rateDist::2 72803 12.91% 93.61% 320system.cpu.fetch.rateDist::3 20031 3.55% 97.16% 321system.cpu.fetch.rateDist::4 9935 1.76% 98.92% 322system.cpu.fetch.rateDist::5 3180 0.56% 99.49% 323system.cpu.fetch.rateDist::6 1981 0.35% 99.84% 324system.cpu.fetch.rateDist::7 355 0.06% 99.90% 325system.cpu.fetch.rateDist::8 526 0.09% 99.99% 326system.cpu.fetch.rateDist::overflows 0 0.00% 99.99% 327system.cpu.fetch.rateDist::min_value 0 328system.cpu.fetch.rateDist::max_value 8 329system.cpu.fetch.rateDist::total 563743 330system.cpu.fetch.branchRate 0.190633 331system.cpu.fetch.rate 0.853239 332system.cpu.decode.IdleCycles 145658 333system.cpu.decode.BlockedCycles 50036 334system.cpu.decode.RunCycles 350465 335system.cpu.decode.UnblockCycles 2505 336system.cpu.decode.SquashCycles 15079 337system.cpu.decode.BranchResolved 43531 338system.cpu.decode.BranchMispred 8717 339system.cpu.decode.DecodedInsts 520617 340system.cpu.decode.SquashedInsts 13886 341system.cpu.rename.SquashCycles 15079 342system.cpu.rename.IdleCycles 162879 343system.cpu.rename.BlockCycles 5626 344system.cpu.rename.serializeStallCycles 37161 345system.cpu.rename.RunCycles 335687 346system.cpu.rename.UnblockCycles 7311 347system.cpu.rename.RenamedInsts 502269 348system.cpu.rename.ROBFullEvents 984 349system.cpu.rename.IQFullEvents 138 350system.cpu.rename.LQFullEvents 1822 351system.cpu.rename.SQFullEvents 3460 352system.cpu.rename.RenamedOperands 337685 353system.cpu.rename.RenameLookups 620018 354system.cpu.rename.int_rename_lookups 618230 355system.cpu.rename.fp_rename_lookups 1788 356system.cpu.rename.CommittedMaps 276598 357system.cpu.rename.UndoneMaps 61087 358system.cpu.rename.serializingInsts 1943 359system.cpu.rename.tempSerializingInsts 1943 360system.cpu.rename.skidInsts 3831 361system.cpu.memDep0.insertedLoads 119278 362system.cpu.memDep0.insertedStores 67494 363system.cpu.memDep0.conflictingLoads 532 364system.cpu.memDep0.conflictingStores 153 365system.cpu.iq.iqInstsAdded 466229 366system.cpu.iq.iqNonSpecInstsAdded 3274 367system.cpu.iq.iqInstsIssued 459327 368system.cpu.iq.iqSquashedInstsIssued 175 369system.cpu.iq.iqSquashedInstsExamined 52219 370system.cpu.iq.iqSquashedOperandsExamined 23838 371system.cpu.iq.iqSquashedNonSpecRemoved 88 372system.cpu.iq.issued_per_cycle::samples 563743 373system.cpu.iq.issued_per_cycle::mean 0.814780 374system.cpu.iq.issued_per_cycle::stdev 0.900911 375system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% 376system.cpu.iq.issued_per_cycle::0 233488 41.41% 41.41% 377system.cpu.iq.issued_per_cycle::1 239164 42.42% 83.84% 378system.cpu.iq.issued_per_cycle::2 63723 11.30% 95.14% 379system.cpu.iq.issued_per_cycle::3 22016 3.90% 99.05% 380system.cpu.iq.issued_per_cycle::4 2579 0.45% 99.50% 381system.cpu.iq.issued_per_cycle::5 1083 0.19% 99.70% 382system.cpu.iq.issued_per_cycle::6 919 0.16% 99.86% 383system.cpu.iq.issued_per_cycle::7 744 0.13% 99.99% 384system.cpu.iq.issued_per_cycle::8 27 0.00% 99.99% 385system.cpu.iq.issued_per_cycle::overflows 0 0.00% 99.99% 386system.cpu.iq.issued_per_cycle::min_value 0 387system.cpu.iq.issued_per_cycle::max_value 8 388system.cpu.iq.issued_per_cycle::total 563743 389system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% 390system.cpu.iq.fu_full::IntAlu 39 2.95% 2.95% 391system.cpu.iq.fu_full::IntMult 0 0.00% 2.95% 392system.cpu.iq.fu_full::IntDiv 0 0.00% 2.95% 393system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.95% 394system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.95% 395system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.95% 396system.cpu.iq.fu_full::FloatMult 0 0.00% 2.95% 397system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 2.95% 398system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.95% 399system.cpu.iq.fu_full::FloatMisc 0 0.00% 2.95% 400system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.95% 401system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.95% 402system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.95% 403system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.95% 404system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.95% 405system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.95% 406system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.95% 407system.cpu.iq.fu_full::SimdMult 0 0.00% 2.95% 408system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.95% 409system.cpu.iq.fu_full::SimdShift 0 0.00% 2.95% 410system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.95% 411system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.95% 412system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.95% 413system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.95% 414system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.95% 415system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.95% 416system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.95% 417system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.95% 418system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.95% 419system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.95% 420system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.95% 421system.cpu.iq.fu_full::MemRead 609 46.13% 49.09% 422system.cpu.iq.fu_full::MemWrite 669 50.68% 99.77% 423system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.77% 424system.cpu.iq.fu_full::FloatMemWrite 3 0.22% 99.99% 425system.cpu.iq.fu_full::IprAccess 0 0.00% 99.99% 426system.cpu.iq.fu_full::InstPrefetch 0 0.00% 99.99% 427system.cpu.iq.FU_type_0::No_OpClass 236 0.05% 0.05% 428system.cpu.iq.FU_type_0::IntAlu 272906 59.41% 59.46% 429system.cpu.iq.FU_type_0::IntMult 677 0.14% 59.61% 430system.cpu.iq.FU_type_0::IntDiv 645 0.14% 59.75% 431system.cpu.iq.FU_type_0::FloatAdd 128 0.02% 59.78% 432system.cpu.iq.FU_type_0::FloatCmp 161 0.03% 59.81% 433system.cpu.iq.FU_type_0::FloatCvt 109 0.02% 59.84% 434system.cpu.iq.FU_type_0::FloatMult 62 0.01% 59.85% 435system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 59.85% 436system.cpu.iq.FU_type_0::FloatDiv 11 0.00% 59.85% 437system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 59.85% 438system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 59.85% 439system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.85% 440system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.85% 441system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.85% 442system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.85% 443system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.85% 444system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.85% 445system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.85% 446system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.85% 447system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.85% 448system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.85% 449system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.85% 450system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.85% 451system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.85% 452system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.85% 453system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.85% 454system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.85% 455system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.85% 456system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.85% 457system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.85% 458system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.85% 459system.cpu.iq.FU_type_0::MemRead 117233 25.52% 85.37% 460system.cpu.iq.FU_type_0::MemWrite 66368 14.44% 99.82% 461system.cpu.iq.FU_type_0::FloatMemRead 614 0.13% 99.96% 462system.cpu.iq.FU_type_0::FloatMemWrite 172 0.03% 99.99% 463system.cpu.iq.FU_type_0::IprAccess 0 0.00% 99.99% 464system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 99.99% 465system.cpu.iq.FU_type_0::total 459327 466system.cpu.iq.rate 0.687118 467system.cpu.iq.fu_busy_cnt 1320 468system.cpu.iq.fu_busy_rate 0.002873 469system.cpu.iq.int_inst_queue_reads 1481365 470system.cpu.iq.int_inst_queue_writes 520340 471system.cpu.iq.int_inst_queue_wakeup_accesses 440331 472system.cpu.iq.fp_inst_queue_reads 2527 473system.cpu.iq.fp_inst_queue_writes 1401 474system.cpu.iq.fp_inst_queue_wakeup_accesses 1166 475system.cpu.iq.int_alu_accesses 459146 476system.cpu.iq.fp_alu_accesses 1265 477system.cpu.iew.lsq.thread0.forwLoads 234 478system.cpu.iew.lsq.thread0.invAddrLoads 0 479system.cpu.iew.lsq.thread0.squashedLoads 13780 480system.cpu.iew.lsq.thread0.ignoredResponses 17 481system.cpu.iew.lsq.thread0.memOrderViolation 17 482system.cpu.iew.lsq.thread0.squashedStores 3368 483system.cpu.iew.lsq.thread0.invAddrSwpfs 0 484system.cpu.iew.lsq.thread0.blockedLoads 0 485system.cpu.iew.lsq.thread0.rescheduledLoads 370 486system.cpu.iew.lsq.thread0.cacheBlocked 139 487system.cpu.iew.iewIdleCycles 0 488system.cpu.iew.iewSquashCycles 15079 489system.cpu.iew.iewBlockCycles 4278 490system.cpu.iew.iewUnblockCycles 898 491system.cpu.iew.iewDispatchedInsts 469497 492system.cpu.iew.iewDispSquashedInsts 15026 493system.cpu.iew.iewDispLoadInsts 119278 494system.cpu.iew.iewDispStoreInsts 67494 495system.cpu.iew.iewDispNonSpecInsts 3268 496system.cpu.iew.iewIQFullEvents 22 497system.cpu.iew.iewLSQFullEvents 852 498system.cpu.iew.memOrderViolationEvents 17 499system.cpu.iew.predictedTakenIncorrect 9022 500system.cpu.iew.predictedNotTakenIncorrect 7728 501system.cpu.iew.branchMispredicts 16750 502system.cpu.iew.iewExecutedInsts 445015 503system.cpu.iew.iewExecLoadInsts 114273 504system.cpu.iew.iewExecSquashedInsts 14312 505system.cpu.iew.exec_swp 0 506system.cpu.iew.exec_nop 0 507system.cpu.iew.exec_refs 180226 508system.cpu.iew.exec_branches 96621 509system.cpu.iew.exec_stores 65953 510system.cpu.iew.exec_rate 0.665708 511system.cpu.iew.wb_sent 442183 512system.cpu.iew.wb_count 441497 513system.cpu.iew.wb_producers 142269 514system.cpu.iew.wb_consumers 163893 515system.cpu.iew.wb_rate 0.660446 516system.cpu.iew.wb_fanout 0.868060 517system.cpu.commit.commitSquashedInsts 52233 518system.cpu.commit.commitNonSpecStalls 3180 519system.cpu.commit.branchMispredicts 14848 520system.cpu.commit.committed_per_cycle::samples 545846 521system.cpu.commit.committed_per_cycle::mean 0.764459 522system.cpu.commit.committed_per_cycle::stdev 1.249358 523system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% 524system.cpu.commit.committed_per_cycle::0 310862 56.95% 56.95% 525system.cpu.commit.committed_per_cycle::1 149504 27.38% 84.33% 526system.cpu.commit.committed_per_cycle::2 34535 6.32% 90.66% 527system.cpu.commit.committed_per_cycle::3 30814 5.64% 96.31% 528system.cpu.commit.committed_per_cycle::4 9598 1.75% 98.07% 529system.cpu.commit.committed_per_cycle::5 3078 0.56% 98.63% 530system.cpu.commit.committed_per_cycle::6 2903 0.53% 99.16% 531system.cpu.commit.committed_per_cycle::7 1355 0.24% 99.41% 532system.cpu.commit.committed_per_cycle::8 3197 0.58% 99.99% 533system.cpu.commit.committed_per_cycle::overflows 0 0.00% 99.99% 534system.cpu.commit.committed_per_cycle::min_value 0 535system.cpu.commit.committed_per_cycle::max_value 8 536system.cpu.commit.committed_per_cycle::total 545846 537system.cpu.commit.committedInsts 416024 538system.cpu.commit.committedOps 417277 539system.cpu.commit.swp_count 0 540system.cpu.commit.refs 169624 541system.cpu.commit.loads 105498 542system.cpu.commit.membars 4 543system.cpu.commit.branches 90856 544system.cpu.commit.vec_insts 0 545system.cpu.commit.fp_insts 1163 546system.cpu.commit.int_insts 415220 547system.cpu.commit.function_calls 23050 548system.cpu.commit.op_class_0::No_OpClass 20 0.00% 0.00% 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566system.cpu.commit.op_class_0::SimdMult 0 0.00% 59.34% 567system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 59.34% 568system.cpu.commit.op_class_0::SimdShift 0 0.00% 59.34% 569system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 59.34% 570system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 59.34% 571system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 59.34% 572system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 59.34% 573system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 59.34% 574system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 59.34% 575system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 59.34% 576system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 59.34% 577system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 59.34% 578system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 59.34% 579system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 59.34% 580system.cpu.commit.op_class_0::MemRead 104951 25.15% 84.50% 581system.cpu.commit.op_class_0::MemWrite 63954 15.32% 99.82% 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74792.202572 980system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79515.673981 981system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79515.673981 982system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74792.202572 983system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78600.371747 984system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75941.919191 985system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74792.202572 986system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78600.371747 987system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75941.919191 988system.cpu.toL2Bus.snoop_filter.tot_requests 1900 989system.cpu.toL2Bus.snoop_filter.hit_single_requests 105 990system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 991system.cpu.toL2Bus.snoop_filter.tot_snoops 0 992system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 993system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 994system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 334241000 995system.cpu.toL2Bus.trans_dist::ReadResp 1579 996system.cpu.toL2Bus.trans_dist::WritebackDirty 2 997system.cpu.toL2Bus.trans_dist::WritebackClean 100 998system.cpu.toL2Bus.trans_dist::ReadExReq 219 999system.cpu.toL2Bus.trans_dist::ReadExResp 219 1000system.cpu.toL2Bus.trans_dist::ReadCleanReq 1259 1001system.cpu.toL2Bus.trans_dist::ReadSharedReq 320 1002system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2618 1003system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1080 1004system.cpu.toL2Bus.pkt_count::total 3698 1005system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86976 1006system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 34624 1007system.cpu.toL2Bus.pkt_size::total 121600 1008system.cpu.toL2Bus.snoops 0 1009system.cpu.toL2Bus.snoopTraffic 0 1010system.cpu.toL2Bus.snoop_fanout::samples 1798 1011system.cpu.toL2Bus.snoop_fanout::mean 0.002224 1012system.cpu.toL2Bus.snoop_fanout::stdev 0.047127 1013system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% 1014system.cpu.toL2Bus.snoop_fanout::0 1794 99.77% 99.77% 1015system.cpu.toL2Bus.snoop_fanout::1 4 0.22% 99.99% 1016system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99% 1017system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99% 1018system.cpu.toL2Bus.snoop_fanout::min_value 0 1019system.cpu.toL2Bus.snoop_fanout::max_value 1 1020system.cpu.toL2Bus.snoop_fanout::total 1798 1021system.cpu.toL2Bus.reqLayer0.occupancy 1052000 1022system.cpu.toL2Bus.reqLayer0.utilization 0.3 1023system.cpu.toL2Bus.respLayer0.occupancy 1888500 1024system.cpu.toL2Bus.respLayer0.utilization 0.5 1025system.cpu.toL2Bus.respLayer1.occupancy 808500 1026system.cpu.toL2Bus.respLayer1.utilization 0.2 1027system.membus.snoop_filter.tot_requests 1782 1028system.membus.snoop_filter.hit_single_requests 0 1029system.membus.snoop_filter.hit_multi_requests 0 1030system.membus.snoop_filter.tot_snoops 0 1031system.membus.snoop_filter.hit_single_snoops 0 1032system.membus.snoop_filter.hit_multi_snoops 0 1033system.membus.pwrStateResidencyTicks::UNDEFINED 334241000 1034system.membus.trans_dist::ReadResp 1563 1035system.membus.trans_dist::ReadExReq 219 1036system.membus.trans_dist::ReadExResp 219 1037system.membus.trans_dist::ReadSharedReq 1563 1038system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3564 1039system.membus.pkt_count::total 3564 1040system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 114048 1041system.membus.pkt_size::total 114048 1042system.membus.snoops 0 1043system.membus.snoopTraffic 0 1044system.membus.snoop_fanout::samples 1782 1045system.membus.snoop_fanout::mean 0 1046system.membus.snoop_fanout::stdev -0 1047system.membus.snoop_fanout::underflows 0 0.00% 0.00% 1048system.membus.snoop_fanout::0 1782 100.00% 100.00% 1049system.membus.snoop_fanout::1 0 0.00% 100.00% 1050system.membus.snoop_fanout::overflows 0 0.00% 100.00% 1051system.membus.snoop_fanout::min_value 0 1052system.membus.snoop_fanout::max_value 0 1053system.membus.snoop_fanout::total 1782 1054system.membus.reqLayer0.occupancy 2193000 1055system.membus.reqLayer0.utilization 0.6 1056system.membus.respLayer1.occupancy 9460500 1057system.membus.respLayer1.utilization 2.8
1019 1020---------- End Simulation Statistics ----------	1058 1059---------- End Simulation Statistics ----------