4,5c4,5
< sim_ticks 113397000 # Number of ticks simulated
< final_tick 113397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 113383000 # Number of ticks simulated
> final_tick 113383000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 22733 # Simulator instruction rate (inst/s)
< host_op_rate 22733 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 11398414 # Simulator tick rate (ticks/s)
< host_mem_usage 246096 # Number of bytes of host memory used
< host_seconds 9.95 # Real time elapsed on the host
---
> host_inst_rate 167766 # Simulator instruction rate (inst/s)
> host_op_rate 167765 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 84106882 # Simulator tick rate (ticks/s)
> host_mem_usage 263760 # Number of bytes of host memory used
> host_seconds 1.35 # Real time elapsed on the host
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 65856 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 65920 # Number of bytes read from this memory
19,22c19,22
< system.physmem.bytes_read::total 85120 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 65856 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 65856 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 1029 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 85184 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 65920 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 65920 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 1030 # Number of read requests responded to by this memory
24,33c24,33
< system.physmem.num_reads::total 1330 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 580756105 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 169881037 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 750637142 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 580756105 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 580756105 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 580756105 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 169881037 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 750637142 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 1330 # Number of read requests accepted
---
> system.physmem.num_reads::total 1331 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 581392272 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 169902014 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 751294286 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 581392272 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 581392272 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 581392272 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 169902014 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 751294286 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 1331 # Number of read requests accepted
35c35
< system.physmem.readBursts 1330 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 1331 # Number of DRAM read bursts, including those serviced by the write queue
37c37
< system.physmem.bytesReadDRAM 85120 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 85184 # Total number of bytes read from DRAM
40c40
< system.physmem.bytesReadSys 85120 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 85184 # Total read bytes from the system interface side
49c49
< system.physmem.perBankRdBursts::4 195 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 194 # Per bank write bursts
55c55
< system.physmem.perBankRdBursts::10 149 # Per bank write bursts
---
> system.physmem.perBankRdBursts::10 150 # Per bank write bursts
58c58
< system.physmem.perBankRdBursts::13 51 # Per bank write bursts
---
> system.physmem.perBankRdBursts::13 52 # Per bank write bursts
79c79
< system.physmem.totGap 113291000 # Total gap between requests
---
> system.physmem.totGap 113277000 # Total gap between requests
86c86
< system.physmem.readPktSize::6 1330 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 1331 # Read request sizes (log2)
94,98c94,98
< system.physmem.rdQLenPdf::0 807 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 369 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 107 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 810 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 44 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
190,207c190,207
< system.physmem.bytesPerActivate::samples 210 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 393.752381 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 254.589157 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 342.600882 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 48 22.86% 22.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 44 20.95% 43.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 35 16.67% 60.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 18 8.57% 69.05% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 13 6.19% 75.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 10 4.76% 80.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 5 2.38% 82.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5 2.38% 84.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 32 15.24% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 210 # Bytes accessed per row activation
< system.physmem.totQLat 16749000 # Total ticks spent queuing
< system.physmem.totMemAccLat 41686500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 6650000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 12593.23 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 212 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 390.641509 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 252.461189 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 341.274727 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 49 23.11% 23.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 43 20.28% 43.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 38 17.92% 61.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 18 8.49% 69.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 13 6.13% 75.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 8 3.77% 79.72% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 6 2.83% 82.55% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5 2.36% 84.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 32 15.09% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 212 # Bytes accessed per row activation
> system.physmem.totQLat 17606250 # Total ticks spent queuing
> system.physmem.totMemAccLat 42562500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 6655000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 13227.84 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 31343.23 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 750.64 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 31977.84 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 751.29 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 750.64 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 751.29 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 5.86 # Data bus utilization in percentage
< system.physmem.busUtilRead 5.86 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 5.87 # Data bus utilization in percentage
> system.physmem.busUtilRead 5.87 # Data bus utilization in percentage for reads
218c218
< system.physmem.avgRdQLen 1.57 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.58 # Average read queue length when enqueuing
220c220
< system.physmem.readRowHits 1108 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 1107 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 83.17 # Row buffer hit rate for reads
224,228c224,228
< system.physmem.avgGap 85181.20 # Average gap between requests
< system.physmem.pageHitRate 83.31 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 763980 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 387090 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 85106.69 # Average gap between requests
> system.physmem.pageHitRate 83.17 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 771120 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 390885 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 5447820 # Energy for read commands per rank (pJ)
231,234c231,234
< system.physmem_0.actBackEnergy 9828510 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 194400 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 40216350 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 1207200 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actBackEnergy 9821100 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 199200 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 40147950 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 1260960 # Energy for precharge power-down per rank (pJ)
236,238c236,238
< system.physmem_0.totalEnergy 66657450 # Total energy per rank (pJ)
< system.physmem_0.averagePower 587.821160 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 91041000 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalEnergy 66643995 # Total energy per rank (pJ)
> system.physmem_0.averagePower 587.773777 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 90897000 # Total Idle time Per DRAM Rank
242,247c242,247
< system.physmem_0.memoryStateTime::PRE_PDN 3144500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 18326750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 88196250 # Time in different power states
< system.physmem_1.actEnergy 821100 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 409860 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 4041240 # Energy for read commands per rank (pJ)
---
> system.physmem_0.memoryStateTime::PRE_PDN 3282750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 18328750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 88042000 # Time in different power states
> system.physmem_1.actEnergy 828240 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 413655 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 4055520 # Energy for read commands per rank (pJ)
250,253c250,253
< system.physmem_1.actBackEnergy 7868280 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 220800 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 41251470 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 1959840 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actBackEnergy 7853460 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 220320 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 41175660 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 2031360 # Energy for precharge power-down per rank (pJ)
255,257c255,257
< system.physmem_1.totalEnergy 65177550 # Total energy per rank (pJ)
< system.physmem_1.averagePower 574.770608 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 95505000 # Total Idle time Per DRAM Rank
---
> system.physmem_1.totalEnergy 65183175 # Total energy per rank (pJ)
> system.physmem_1.averagePower 574.889920 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 95520250 # Total Idle time Per DRAM Rank
261,269c261,269
< system.physmem_1.memoryStateTime::PRE_PDN 5102500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 14007750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 90472250 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 78040 # Number of BP lookups
< system.cpu.branchPred.condPredicted 47825 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 4968 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 59525 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 36023 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::PRE_PDN 5288750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 13978500 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 90301250 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 78097 # Number of BP lookups
> system.cpu.branchPred.condPredicted 47857 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 4973 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 59652 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 36130 # Number of BTB hits
271c271
< system.cpu.branchPred.BTBHitPct 60.517430 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 60.567961 # BTB Hit Percentage
274,277c274,277
< system.cpu.branchPred.indirectLookups 14832 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 6672 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 8160 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 2577 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.indirectLookups 14779 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 6634 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 8145 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 2576 # Number of mispredicted indirect branches.
298,299c298,299
< system.cpu.pwrStateResidencyTicks::ON 113397000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 226795 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 113383000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 226767 # number of cpu cycles simulated
302,314c302,314
< system.cpu.fetch.icacheStallCycles 73757 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 336548 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 78040 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 42695 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 87262 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 10228 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 401 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 60631 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 2398 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 166726 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.018569 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.822541 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 73708 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 336580 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 78097 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 42764 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 87814 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 10240 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 400 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.IcacheWaitRetryStallCycles 177 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 60514 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 2320 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 167219 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.012810 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.818543 # Number of instructions fetched each cycle (Total)
316,324c316,324
< system.cpu.fetch.rateDist::0 89937 53.94% 53.94% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 11784 7.07% 61.01% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 13843 8.30% 69.31% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 11668 7.00% 76.31% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 5791 3.47% 79.79% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 6797 4.08% 83.86% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 2856 1.71% 85.58% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 4611 2.77% 88.34% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 19439 11.66% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 90347 54.03% 54.03% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 11793 7.05% 61.08% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 13895 8.31% 69.39% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 11689 6.99% 76.38% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 5745 3.44% 79.82% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 6911 4.13% 83.95% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 2836 1.70% 85.65% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 4645 2.78% 88.42% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 19358 11.58% 100.00% # Number of instructions fetched each cycle (Total)
328,349c328,349
< system.cpu.fetch.rateDist::total 166726 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.344099 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.483930 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 72653 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 18351 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 70165 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 1269 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 4288 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 13538 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 899 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 310274 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 2536 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 4288 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 75144 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 7711 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 3158 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 68795 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 7630 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 298982 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 168 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 64 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 782 # Number of times rename has blocked due to LQ full
---
> system.cpu.fetch.rateDist::total 167219 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.344393 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.484255 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 72610 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 18818 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 70228 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 1268 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 4295 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 35338 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 921 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 310147 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 2548 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 4295 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 75141 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 8221 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 3161 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 68810 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 7591 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 298778 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 161 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 69 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 743 # Number of times rename has blocked due to LQ full
351,354c351,354
< system.cpu.rename.RenamedOperands 208109 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 389749 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 387389 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 2360 # Number of floating rename lookups
---
> system.cpu.rename.RenamedOperands 207984 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 389381 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 387034 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 2347 # Number of floating rename lookups
356c356
< system.cpu.rename.UndoneMaps 52968 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 52843 # Number of HB maps that are undone due to squashing
359,373c359,373
< system.cpu.rename.skidInsts 3030 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 62164 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 43440 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 1172 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 335 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 273555 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 154 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 261697 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 610 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 47545 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 26182 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 33 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 166726 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.569623 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.886679 # Number of insts issued each cycle
---
> system.cpu.rename.skidInsts 3092 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 62122 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 43306 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 1169 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 342 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 273422 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 166 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 261550 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 571 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 47419 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 26031 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 167219 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.564117 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.884378 # Number of insts issued each cycle
375,383c375,383
< system.cpu.iq.issued_per_cycle::0 67362 40.40% 40.40% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 36208 21.72% 62.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 23951 14.37% 76.49% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 10817 6.49% 82.97% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 10352 6.21% 89.18% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 8029 4.82% 94.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 7579 4.55% 98.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 1315 0.79% 99.33% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 1113 0.67% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 67857 40.58% 40.58% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 36223 21.66% 62.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 23953 14.32% 76.57% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 10828 6.48% 83.04% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 10307 6.16% 89.21% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 8097 4.84% 94.05% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 7553 4.52% 98.56% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 1302 0.78% 99.34% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 1099 0.66% 100.00% # Number of insts issued each cycle
387c387
< system.cpu.iq.issued_per_cycle::total 166726 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 167219 # Number of insts issued each cycle
389,422c389,422
< system.cpu.iq.fu_full::IntAlu 704 10.43% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 2989 44.27% 54.69% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 2970 43.99% 98.68% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 88 1.30% 99.99% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 716 10.62% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.62% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 2981 44.22% 54.84% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 2955 43.84% 98.68% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 88 1.31% 99.99% # attempts to use FU when none available
427,460c427,460
< system.cpu.iq.FU_type_0::IntAlu 159679 61.02% 61.06% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.19% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.20% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 172 0.07% 61.27% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.31% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.34% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.35% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 59286 22.65% 84.01% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 40948 15.65% 99.66% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMemRead 721 0.28% 99.93% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 159688 61.05% 61.10% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 326 0.12% 61.22% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 44 0.02% 61.24% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 170 0.06% 61.31% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 120 0.05% 61.35% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 58 0.02% 61.37% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 30 0.01% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 12 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 5 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.39% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 59226 22.64% 84.04% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 40848 15.62% 99.65% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMemRead 727 0.28% 99.93% # Type of FU issued
464,476c464,476
< system.cpu.iq.FU_type_0::total 261697 # Type of FU issued
< system.cpu.iq.rate 1.153892 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 6752 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.025801 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 694798 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 318360 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 249994 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 2684 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 2938 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 1006 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 266946 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 1386 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 5628 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 261550 # Type of FU issued
> system.cpu.iq.rate 1.153387 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 6741 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.025773 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 694940 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 318115 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 249943 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 2691 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 2944 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 1007 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 266784 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 1390 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 5624 # Number of loads that had data forwarded from stores
478,481c478,481
< system.cpu.iew.lsq.thread0.squashedLoads 10453 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 28 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 6211 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 10411 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 34 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 6077 # Number of stores squashed
484c484
< system.cpu.iew.lsq.thread0.rescheduledLoads 10 # Number of loads that were rescheduled
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 9 # Number of loads that were rescheduled
487,503c487,503
< system.cpu.iew.iewSquashCycles 4288 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 4913 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 272 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 273705 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 3278 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 62164 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 43440 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 150 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 40 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 1281 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 3469 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 4750 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 254156 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 58399 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 7541 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 4295 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 4907 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 918 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 273579 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 3363 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 62122 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 43306 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 157 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 908 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 41 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 1293 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 3450 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 4743 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 254044 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 58349 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 7506 # Number of squashed instructions skipped in execute
506,516c506,516
< system.cpu.iew.exec_refs 98174 # number of memory reference insts executed
< system.cpu.iew.exec_branches 57098 # Number of branches executed
< system.cpu.iew.exec_stores 39775 # Number of stores executed
< system.cpu.iew.exec_rate 1.120642 # Inst execution rate
< system.cpu.iew.wb_sent 252228 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 251000 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 95690 # num instructions producing a value
< system.cpu.iew.wb_consumers 132115 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.106726 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.724293 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 47577 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_refs 98069 # number of memory reference insts executed
> system.cpu.iew.exec_branches 57083 # Number of branches executed
> system.cpu.iew.exec_stores 39720 # Number of stores executed
> system.cpu.iew.exec_rate 1.120286 # Inst execution rate
> system.cpu.iew.wb_sent 252158 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 250950 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 95653 # num instructions producing a value
> system.cpu.iew.wb_consumers 131997 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.106643 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.724660 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 47451 # The number of squashed insts skipped by commit
518,521c518,521
< system.cpu.commit.branchMispredicts 4142 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 157673 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.434355 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.158076 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 4148 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 158171 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.429839 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.156696 # Number of insts commited each cycle
523,531c523,531
< system.cpu.commit.committed_per_cycle::0 82961 52.62% 52.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 25849 16.39% 69.01% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 14396 9.13% 78.14% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 11000 6.98% 85.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 5848 3.71% 88.83% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 5974 3.79% 92.61% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 3323 2.11% 94.72% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 1258 0.80% 95.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 7064 4.48% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 83501 52.79% 52.79% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 25809 16.32% 69.11% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 14383 9.09% 78.20% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 10997 6.95% 85.15% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 5860 3.70% 88.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 5977 3.78% 92.64% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 3309 2.09% 94.73% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 1266 0.80% 95.53% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 7069 4.47% 100.00% # Number of insts commited each cycle
535c535
< system.cpu.commit.committed_per_cycle::total 157673 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 158171 # Number of insts commited each cycle
585,589c585,589
< system.cpu.commit.bw_lim_events 7064 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 422850 # The number of ROB reads
< system.cpu.rob.rob_writes 556608 # The number of ROB writes
< system.cpu.timesIdled 458 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 60069 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 7069 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 423217 # The number of ROB reads
> system.cpu.rob.rob_writes 556357 # The number of ROB writes
> system.cpu.timesIdled 459 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 59548 # Total number of cycles that the CPU has spent unscheduled due to idling
592,600c592,600
< system.cpu.cpi 1.002812 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 1.002812 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.997196 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.997196 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 329004 # number of integer regfile reads
< system.cpu.int_regfile_writes 174767 # number of integer regfile writes
< system.cpu.fp_regfile_reads 880 # number of floating regfile reads
< system.cpu.fp_regfile_writes 753 # number of floating regfile writes
< system.cpu.misc_regfile_reads 448 # number of misc regfile reads
---
> system.cpu.cpi 1.002688 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.002688 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.997319 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.997319 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 329254 # number of integer regfile reads
> system.cpu.int_regfile_writes 174794 # number of integer regfile writes
> system.cpu.fp_regfile_reads 878 # number of floating regfile reads
> system.cpu.fp_regfile_writes 754 # number of floating regfile writes
> system.cpu.misc_regfile_reads 446 # number of misc regfile reads
602c602
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
604,605c604,605
< system.cpu.dcache.tags.tagsinuse 244.736374 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 87597 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 244.658569 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 87565 # Total number of references to valid blocks.
607c607
< system.cpu.dcache.tags.avg_refs 291.019934 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 290.913621 # Average number of references to valid blocks.
609,611c609,611
< system.cpu.dcache.tags.occ_blocks::cpu.data 244.736374 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.059750 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.059750 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 244.658569 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.059731 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.059731 # Average percentage of cache occupancy
617,645c617,645
< system.cpu.dcache.tags.tag_accesses 179361 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 179361 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 51858 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 51858 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 35739 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 35739 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 87597 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 87597 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 87597 # number of overall hits
< system.cpu.dcache.overall_hits::total 87597 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 443 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 443 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 1490 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 1490 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 1933 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1933 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1933 # number of overall misses
< system.cpu.dcache.overall_misses::total 1933 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 36817500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 36817500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 96718425 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 96718425 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 133535925 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 133535925 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 133535925 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 133535925 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 52301 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 52301 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.tags.tag_accesses 179301 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 179301 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 51833 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 51833 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 35732 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 35732 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 87565 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 87565 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 87565 # number of overall hits
> system.cpu.dcache.overall_hits::total 87565 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 438 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 438 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 1497 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 1497 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 1935 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1935 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1935 # number of overall misses
> system.cpu.dcache.overall_misses::total 1935 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 36015000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 36015000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 97868425 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 97868425 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 133883425 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 133883425 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 133883425 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 133883425 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 52271 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 52271 # number of ReadReq accesses(hits+misses)
648,668c648,668
< system.cpu.dcache.demand_accesses::cpu.data 89530 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 89530 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 89530 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 89530 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008470 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.008470 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040023 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.040023 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.021591 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.021591 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.021591 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.021591 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83109.480813 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 83109.480813 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64911.694631 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 64911.694631 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 69082.216762 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 69082.216762 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 69082.216762 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 5513 # number of cycles access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 89500 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 89500 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 89500 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 89500 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008379 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.008379 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.040211 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.040211 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.021620 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.021620 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.021620 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.021620 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82226.027397 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 82226.027397 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65376.369405 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 65376.369405 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 69190.400517 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 69190.400517 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 69190.400517 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 6103 # number of cycles access was blocked
672c672
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.784810 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.253165 # average number of cycles each access was blocked
674,681c674,681
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 346 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 346 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1286 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1286 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 1632 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 1632 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 1632 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 1632 # number of overall MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 341 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 341 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1293 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1293 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 1634 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 1634 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 1634 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 1634 # number of overall MSHR hits
690,699c690,699
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8757000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8757000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16055500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 16055500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24812500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 24812500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24812500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 24812500 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001855 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001855 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8546500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8546500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17206500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 17206500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25753000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 25753000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25753000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 25753000 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001856 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001856 # mshr miss rate for ReadReq accesses
702,719c702,719
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.003362 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003362 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.003362 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90278.350515 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90278.350515 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78703.431373 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78703.431373 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82433.554817 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 82433.554817 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 69 # number of replacements
< system.cpu.icache.tags.tagsinuse 535.650396 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 59273 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1034 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 57.323985 # Average number of references to valid blocks.
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003363 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.003363 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003363 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.003363 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88108.247423 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88108.247423 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84345.588235 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84345.588235 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85558.139535 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85558.139535 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 85558.139535 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 70 # number of replacements
> system.cpu.icache.tags.tagsinuse 535.835535 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 59155 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1035 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 57.154589 # Average number of references to valid blocks.
721,723c721,723
< system.cpu.icache.tags.occ_blocks::cpu.inst 535.650396 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.261548 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.261548 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 535.835535 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.261638 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.261638 # Average percentage of cache occupancy
725c725
< system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id
727c727
< system.cpu.icache.tags.age_task_id_blocks_1024::2 120 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
729,768c729,768
< system.cpu.icache.tags.tag_accesses 122286 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 122286 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 59273 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 59273 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 59273 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 59273 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 59273 # number of overall hits
< system.cpu.icache.overall_hits::total 59273 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1353 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1353 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1353 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1353 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1353 # number of overall misses
< system.cpu.icache.overall_misses::total 1353 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 109130497 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 109130497 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 109130497 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 109130497 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 109130497 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 109130497 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 60626 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 60626 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 60626 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 60626 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 60626 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 60626 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022317 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.022317 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.022317 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.022317 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.022317 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.022317 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80658.164819 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 80658.164819 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 80658.164819 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 80658.164819 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 80658.164819 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 80658.164819 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 2365 # number of cycles access was blocked
---
> system.cpu.icache.tags.tag_accesses 122053 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 122053 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 59155 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 59155 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 59155 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 59155 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 59155 # number of overall hits
> system.cpu.icache.overall_hits::total 59155 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1354 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1354 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1354 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1354 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1354 # number of overall misses
> system.cpu.icache.overall_misses::total 1354 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 109143498 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 109143498 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 109143498 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 109143498 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 109143498 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 109143498 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 60509 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 60509 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 60509 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 60509 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 60509 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 60509 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.022377 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.022377 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.022377 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.022377 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.022377 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.022377 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80608.196455 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 80608.196455 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 80608.196455 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 80608.196455 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 80608.196455 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 2475 # number of cycles access was blocked
770c770
< system.cpu.icache.blocked::no_mshrs 33 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 34 # number of cycles access was blocked
772c772
< system.cpu.icache.avg_blocked_cycles::no_mshrs 71.666667 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 72.794118 # average number of cycles each access was blocked
774,775c774,775
< system.cpu.icache.writebacks::writebacks 69 # number of writebacks
< system.cpu.icache.writebacks::total 69 # number of writebacks
---
> system.cpu.icache.writebacks::writebacks 70 # number of writebacks
> system.cpu.icache.writebacks::total 70 # number of writebacks
782,806c782,806
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1034 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1034 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1034 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1034 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1034 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1034 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86838997 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 86838997 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86838997 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 86838997 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86838997 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 86838997 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017055 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.017055 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.017055 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.017055 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83983.556093 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83983.556093 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83983.556093 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 83983.556093 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83983.556093 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 83983.556093 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1035 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1035 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1035 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1035 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1035 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86827498 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 86827498 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86827498 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 86827498 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86827498 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 86827498 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.017105 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.017105 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.017105 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.017105 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83891.302415 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83891.302415 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83891.302415 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 83891.302415 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
808,811c808,811
< system.cpu.l2cache.tags.tagsinuse 808.401303 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 71 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 1330 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.053383 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 808.901136 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 72 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 1331 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.054095 # Average number of references to valid blocks.
813,827c813,827
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 563.637058 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 244.764245 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017201 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.007470 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.024670 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 1330 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 879 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040588 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 12538 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 12538 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 564.214692 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 244.686444 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017218 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.007467 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.024686 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 1331 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 880 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 338 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.040619 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 12555 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 12555 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackClean_hits::writebacks 70 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 70 # number of WritebackClean hits
836,837c836,837
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1029 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 1029 # number of ReadCleanReq misses
---
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1030 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 1030 # number of ReadCleanReq misses
840c840
< system.cpu.l2cache.demand_misses::cpu.inst 1029 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses
842,843c842,843
< system.cpu.l2cache.demand_misses::total 1330 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 1029 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 1331 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 1030 # number of overall misses
845,859c845,859
< system.cpu.l2cache.overall_misses::total 1330 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15749000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 15749000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 85256500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 85256500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8611500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 8611500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 85256500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 24360500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 109617000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 85256500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 24360500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 109617000 # number of overall miss cycles
< system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::total 1331 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16900000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 16900000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 85245000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 85245000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8401000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 8401000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 85245000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 25301000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 110546000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 85245000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 25301000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 110546000 # number of overall miss cycles
> system.cpu.l2cache.WritebackClean_accesses::writebacks 70 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 70 # number of WritebackClean accesses(hits+misses)
862,863c862,863
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1031 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1031 # number of ReadCleanReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1032 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1032 # number of ReadCleanReq accesses(hits+misses)
866c866
< system.cpu.l2cache.demand_accesses::cpu.inst 1031 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 1032 # number of demand (read+write) accesses
868,869c868,869
< system.cpu.l2cache.demand_accesses::total 1332 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1031 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 1333 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1032 # number of overall (read+write) accesses
871c871
< system.cpu.l2cache.overall_accesses::total 1332 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 1333 # number of overall (read+write) accesses
874,875c874,875
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998060 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998060 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.998062 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.998062 # miss rate for ReadCleanReq accesses
878c878
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998060 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.998062 # miss rate for demand accesses
880,881c880,881
< system.cpu.l2cache.demand_miss_rate::total 0.998498 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998060 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.998500 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.998062 # miss rate for overall accesses
883,895c883,895
< system.cpu.l2cache.overall_miss_rate::total 0.998498 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77200.980392 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77200.980392 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82853.741497 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82853.741497 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88778.350515 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88778.350515 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82853.741497 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80931.893688 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 82418.796992 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82853.741497 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80931.893688 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 82418.796992 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.998500 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82843.137255 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82843.137255 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82762.135922 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82762.135922 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86608.247423 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86608.247423 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82762.135922 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84056.478405 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 83054.845980 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82762.135922 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84056.478405 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 83054.845980 # average overall miss latency
904,905c904,905
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1029 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1029 # number of ReadCleanReq MSHR misses
---
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1030 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1030 # number of ReadCleanReq MSHR misses
908c908
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 1029 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 1030 # number of demand (read+write) MSHR misses
910,911c910,911
< system.cpu.l2cache.demand_mshr_misses::total 1330 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 1029 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 1331 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 1030 # number of overall MSHR misses
913,925c913,925
< system.cpu.l2cache.overall_mshr_misses::total 1330 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13709000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13709000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74966500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74966500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7641500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7641500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74966500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21350500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 96317000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74966500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21350500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 96317000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::total 1331 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 14860000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 14860000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74945000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74945000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7431000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7431000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74945000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22291000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 97236000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74945000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22291000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 97236000 # number of overall MSHR miss cycles
928,929c928,929
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998060 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998062 # mshr miss rate for ReadCleanReq accesses
932c932
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for demand accesses
934,935c934,935
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.998498 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998060 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.998500 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998062 # mshr miss rate for overall accesses
937,951c937,951
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.998498 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67200.980392 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67200.980392 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72853.741497 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72853.741497 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78778.350515 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78778.350515 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72853.741497 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70931.893688 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72418.796992 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 1404 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 72 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.998500 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72843.137255 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72843.137255 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72762.135922 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72762.135922 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76608.247423 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76608.247423 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72762.135922 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74056.478405 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73054.845980 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 1406 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 73 # Number of requests hitting in the snoop filter with a single holder of the requested data.
956,958c956,958
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 1131 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 1132 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 70 # Transaction distribution
961c961
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1034 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1035 # Transaction distribution
963c963
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2134 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2137 # Packet count per connected master and slave (bytes)
965,966c965,966
< system.cpu.toL2Bus.pkt_count::total 2736 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70400 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 2739 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 70528 # Cumulative packet size per connected master and slave (bytes)
968c968
< system.cpu.toL2Bus.pkt_size::total 89664 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 89792 # Cumulative packet size per connected master and slave (bytes)
971,973c971,973
< system.cpu.toL2Bus.snoop_fanout::samples 1335 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.002247 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.047369 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 1336 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.002246 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.047351 # Request fanout histogram
975c975
< system.cpu.toL2Bus.snoop_fanout::0 1332 99.78% 99.78% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 1333 99.78% 99.78% # Request fanout histogram
981,982c981,982
< system.cpu.toL2Bus.snoop_fanout::total 1335 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 771000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 1336 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 773000 # Layer occupancy (ticks)
984c984
< system.cpu.toL2Bus.respLayer0.occupancy 1551000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1552500 # Layer occupancy (ticks)
988c988
< system.membus.snoop_filter.tot_requests 1330 # Total number of requests made to the snoop filter.
---
> system.membus.snoop_filter.tot_requests 1331 # Total number of requests made to the snoop filter.
994,995c994,995
< system.membus.pwrStateResidencyTicks::UNDEFINED 113397000 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 1126 # Transaction distribution
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 113383000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 1127 # Transaction distribution
998,1002c998,1002
< system.membus.trans_dist::ReadSharedReq 1126 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2660 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 2660 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85120 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 85120 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadSharedReq 1127 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2662 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 2662 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 85184 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 85184 # Cumulative packet size per connected master and slave (bytes)
1005c1005
< system.membus.snoop_fanout::samples 1330 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 1331 # Request fanout histogram
1009c1009
< system.membus.snoop_fanout::0 1330 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 1331 100.00% 100.00% # Request fanout histogram
1014,1015c1014,1015
< system.membus.snoop_fanout::total 1330 # Request fanout histogram
< system.membus.reqLayer0.occupancy 1627500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 1331 # Request fanout histogram
> system.membus.reqLayer0.occupancy 1624000 # Layer occupancy (ticks)
1017c1017
< system.membus.respLayer1.occupancy 7008750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 7014000 # Layer occupancy (ticks)