3sim_seconds 0.000270 # Number of seconds simulated
4sim_ticks 269998000 # Number of ticks simulated
5final_tick 269998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 216821 # Simulator instruction rate (inst/s)
8host_op_rate 216819 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 258712153 # Simulator tick rate (ticks/s)
10host_mem_usage 263004 # Number of bytes of host memory used
11host_seconds 1.04 # Real time elapsed on the host
12sim_insts 226275 # Number of instructions simulated
13sim_ops 226275 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory
19system.physmem.bytes_read::total 86336 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 67072 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 67072 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 248416655 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 71348677 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 319765332 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 248416655 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 248416655 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 248416655 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 71348677 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 319765332 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.readReqs 1349 # Number of read requests accepted
34system.physmem.writeReqs 0 # Number of write requests accepted
35system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM 86336 # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40system.physmem.bytesReadSys 86336 # Total read bytes from the system interface side
41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45system.physmem.perBankRdBursts::0 173 # Per bank write bursts
46system.physmem.perBankRdBursts::1 19 # Per bank write bursts
47system.physmem.perBankRdBursts::2 18 # Per bank write bursts
48system.physmem.perBankRdBursts::3 76 # Per bank write bursts
49system.physmem.perBankRdBursts::4 196 # Per bank write bursts
50system.physmem.perBankRdBursts::5 259 # Per bank write bursts
51system.physmem.perBankRdBursts::6 19 # Per bank write bursts
52system.physmem.perBankRdBursts::7 4 # Per bank write bursts
53system.physmem.perBankRdBursts::8 26 # Per bank write bursts
54system.physmem.perBankRdBursts::9 99 # Per bank write bursts
55system.physmem.perBankRdBursts::10 157 # Per bank write bursts
56system.physmem.perBankRdBursts::11 158 # Per bank write bursts
57system.physmem.perBankRdBursts::12 48 # Per bank write bursts
58system.physmem.perBankRdBursts::13 47 # Per bank write bursts
59system.physmem.perBankRdBursts::14 17 # Per bank write bursts
60system.physmem.perBankRdBursts::15 33 # Per bank write bursts
61system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79system.physmem.totGap 269757000 # Total gap between requests
80system.physmem.readPktSize::0 0 # Read request sizes (log2)
81system.physmem.readPktSize::1 0 # Read request sizes (log2)
82system.physmem.readPktSize::2 0 # Read request sizes (log2)
83system.physmem.readPktSize::3 0 # Read request sizes (log2)
84system.physmem.readPktSize::4 0 # Read request sizes (log2)
85system.physmem.readPktSize::5 0 # Read request sizes (log2)
86system.physmem.readPktSize::6 1349 # Read request sizes (log2)
87system.physmem.writePktSize::0 0 # Write request sizes (log2)
88system.physmem.writePktSize::1 0 # Write request sizes (log2)
89system.physmem.writePktSize::2 0 # Write request sizes (log2)
90system.physmem.writePktSize::3 0 # Write request sizes (log2)
91system.physmem.writePktSize::4 0 # Write request sizes (log2)
92system.physmem.writePktSize::5 0 # Write request sizes (log2)
93system.physmem.writePktSize::6 0 # Write request sizes (log2)
94system.physmem.rdQLenPdf::0 1287 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1 59 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::2 3 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 237.806193 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 293.628623 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::0-127 54 22.59% 22.59% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::128-255 57 23.85% 46.44% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383 29 12.13% 58.58% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 20 8.37% 81.59% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 17 7.11% 88.70% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation
204system.physmem.totQLat 15217250 # Total ticks spent queuing
205system.physmem.totMemAccLat 40511000 # Total ticks spent from burst creation until serviced by the DRAM
206system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers
207system.physmem.avgQLat 11280.39 # Average queueing delay per DRAM burst
208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
209system.physmem.avgMemAccLat 30030.39 # Average memory access latency per DRAM burst
210system.physmem.avgRdBW 319.77 # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys 319.77 # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil 2.50 # Data bus utilization in percentage
216system.physmem.busUtilRead 2.50 # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220system.physmem.readRowHits 1101 # Number of row buffer hits during reads
221system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads
223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224system.physmem.avgGap 199968.12 # Average gap between requests
225system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined
226system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ)
227system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ)
228system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ)
229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ)
231system.physmem_0.actBackEnergy 13384170 # Energy for active background per rank (pJ)
232system.physmem_0.preBackEnergy 450240 # Energy for precharge background per rank (pJ)
233system.physmem_0.actPowerDownEnergy 94080210 # Energy for active power-down per rank (pJ)
234system.physmem_0.prePowerDownEnergy 12732960 # Energy for precharge power-down per rank (pJ)
235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
236system.physmem_0.totalEnergy 148362930 # Total energy per rank (pJ)
237system.physmem_0.averagePower 549.494877 # Core power per rank (mW)
238system.physmem_0.totalIdleTime 238782750 # Total Idle time Per DRAM Rank
239system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states
240system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states
241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
242system.physmem_0.memoryStateTime::PRE_PDN 33151500 # Time in different power states
243system.physmem_0.memoryStateTime::ACT 21477500 # Time in different power states
244system.physmem_0.memoryStateTime::ACT_PDN 206319000 # Time in different power states
245system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ)
246system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ)
247system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ)
248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ)
250system.physmem_1.actBackEnergy 11660490 # Energy for active background per rank (pJ)
251system.physmem_1.preBackEnergy 3532800 # Energy for precharge background per rank (pJ)
252system.physmem_1.actPowerDownEnergy 84455190 # Energy for active power-down per rank (pJ)
253system.physmem_1.prePowerDownEnergy 18941760 # Energy for precharge power-down per rank (pJ)
254system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ)
255system.physmem_1.totalEnergy 146312775 # Total energy per rank (pJ)
256system.physmem_1.averagePower 541.901675 # Core power per rank (mW)
257system.physmem_1.totalIdleTime 235034750 # Total Idle time Per DRAM Rank
258system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states
259system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states
260system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states
261system.physmem_1.memoryStateTime::PRE_PDN 49337750 # Time in different power states
262system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states
263system.physmem_1.memoryStateTime::ACT_PDN 185210500 # Time in different power states
264system.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
265system.cpu.branchPred.lookups 61459 # Number of BP lookups
266system.cpu.branchPred.condPredicted 39303 # Number of conditional branches predicted
267system.cpu.branchPred.condIncorrect 4350 # Number of conditional branches incorrect
268system.cpu.branchPred.BTBLookups 48024 # Number of BTB lookups
269system.cpu.branchPred.BTBHits 29463 # Number of BTB hits
270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
271system.cpu.branchPred.BTBHitPct 61.350575 # BTB Hit Percentage
272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
274system.cpu.branchPred.indirectLookups 10253 # Number of indirect predictor lookups.
275system.cpu.branchPred.indirectHits 6091 # Number of indirect target hits.
276system.cpu.branchPred.indirectMisses 4162 # Number of indirect misses.
277system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches.
278system.cpu_clk_domain.clock 500 # Clock period in ticks
279system.cpu.dtb.read_hits 0 # DTB read hits
280system.cpu.dtb.read_misses 0 # DTB read misses
281system.cpu.dtb.read_accesses 0 # DTB read accesses
282system.cpu.dtb.write_hits 0 # DTB write hits
283system.cpu.dtb.write_misses 0 # DTB write misses
284system.cpu.dtb.write_accesses 0 # DTB write accesses
285system.cpu.dtb.hits 0 # DTB hits
286system.cpu.dtb.misses 0 # DTB misses
287system.cpu.dtb.accesses 0 # DTB accesses
288system.cpu.itb.read_hits 0 # DTB read hits
289system.cpu.itb.read_misses 0 # DTB read misses
290system.cpu.itb.read_accesses 0 # DTB read accesses
291system.cpu.itb.write_hits 0 # DTB write hits
292system.cpu.itb.write_misses 0 # DTB write misses
293system.cpu.itb.write_accesses 0 # DTB write accesses
294system.cpu.itb.hits 0 # DTB hits
295system.cpu.itb.misses 0 # DTB misses
296system.cpu.itb.accesses 0 # DTB accesses
297system.cpu.workload.numSyscalls 115 # Number of system calls
298system.cpu.pwrStateResidencyTicks::ON 269998000 # Cumulative time (in ticks) in various power states
299system.cpu.numCycles 539996 # number of cpu cycles simulated
300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
302system.cpu.committedInsts 226275 # Number of instructions committed
303system.cpu.committedOps 226275 # Number of ops (including micro ops) committed
304system.cpu.discardedOps 10605 # Number of ops (including micro ops) which were discarded before commit
305system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
306system.cpu.cpi 2.386459 # CPI: cycles per instruction
307system.cpu.ipc 0.419031 # IPC: instructions per cycle
308system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction
309system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction
310system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction
311system.cpu.op_class_0::IntDiv 40 0.02% 60.56% # Class of committed instruction
312system.cpu.op_class_0::FloatAdd 104 0.05% 60.60% # Class of committed instruction
313system.cpu.op_class_0::FloatCmp 119 0.05% 60.65% # Class of committed instruction
314system.cpu.op_class_0::FloatCvt 43 0.02% 60.67% # Class of committed instruction
315system.cpu.op_class_0::FloatMult 30 0.01% 60.69% # Class of committed instruction
316system.cpu.op_class_0::FloatMultAcc 0 0.00% 60.69% # Class of committed instruction
317system.cpu.op_class_0::FloatDiv 11 0.00% 60.69% # Class of committed instruction
318system.cpu.op_class_0::FloatMisc 0 0.00% 60.69% # Class of committed instruction
319system.cpu.op_class_0::FloatSqrt 5 0.00% 60.69% # Class of committed instruction
320system.cpu.op_class_0::SimdAdd 0 0.00% 60.69% # Class of committed instruction
321system.cpu.op_class_0::SimdAddAcc 0 0.00% 60.69% # Class of committed instruction
322system.cpu.op_class_0::SimdAlu 0 0.00% 60.69% # Class of committed instruction
323system.cpu.op_class_0::SimdCmp 0 0.00% 60.69% # Class of committed instruction
324system.cpu.op_class_0::SimdCvt 0 0.00% 60.69% # Class of committed instruction
325system.cpu.op_class_0::SimdMisc 0 0.00% 60.69% # Class of committed instruction
326system.cpu.op_class_0::SimdMult 0 0.00% 60.69% # Class of committed instruction
327system.cpu.op_class_0::SimdMultAcc 0 0.00% 60.69% # Class of committed instruction
328system.cpu.op_class_0::SimdShift 0 0.00% 60.69% # Class of committed instruction
329system.cpu.op_class_0::SimdShiftAcc 0 0.00% 60.69% # Class of committed instruction
330system.cpu.op_class_0::SimdSqrt 0 0.00% 60.69% # Class of committed instruction
331system.cpu.op_class_0::SimdFloatAdd 0 0.00% 60.69% # Class of committed instruction
332system.cpu.op_class_0::SimdFloatAlu 0 0.00% 60.69% # Class of committed instruction
333system.cpu.op_class_0::SimdFloatCmp 0 0.00% 60.69% # Class of committed instruction
334system.cpu.op_class_0::SimdFloatCvt 0 0.00% 60.69% # Class of committed instruction
335system.cpu.op_class_0::SimdFloatDiv 0 0.00% 60.69% # Class of committed instruction
336system.cpu.op_class_0::SimdFloatMisc 0 0.00% 60.69% # Class of committed instruction
337system.cpu.op_class_0::SimdFloatMult 0 0.00% 60.69% # Class of committed instruction
338system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 60.69% # Class of committed instruction
339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.69% # Class of committed instruction
340system.cpu.op_class_0::MemRead 51297 22.67% 83.36% # Class of committed instruction
341system.cpu.op_class_0::MemWrite 37094 16.39% 99.76% # Class of committed instruction
342system.cpu.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction
343system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction
344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
346system.cpu.op_class_0::total 226275 # Class of committed instruction
347system.cpu.tickCycles 339832 # Number of cycles that the object actually ticked
348system.cpu.idleCycles 200164 # Total number of cycles that the object has spent stopped
349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
350system.cpu.dcache.tags.replacements 0 # number of replacements
351system.cpu.dcache.tags.tagsinuse 242.012615 # Cycle average of tags in use
352system.cpu.dcache.tags.total_refs 90016 # Total number of references to valid blocks.
353system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks.
354system.cpu.dcache.tags.avg_refs 298.066225 # Average number of references to valid blocks.
355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
356system.cpu.dcache.tags.occ_blocks::cpu.data 242.012615 # Average occupied blocks per requestor
357system.cpu.dcache.tags.occ_percent::cpu.data 0.059085 # Average percentage of cache occupancy
358system.cpu.dcache.tags.occ_percent::total 0.059085 # Average percentage of cache occupancy
359system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id
360system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
361system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
362system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id
363system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id
364system.cpu.dcache.tags.tag_accesses 181332 # Number of tag accesses
365system.cpu.dcache.tags.data_accesses 181332 # Number of data accesses
366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
367system.cpu.dcache.ReadReq_hits::cpu.data 53183 # number of ReadReq hits
368system.cpu.dcache.ReadReq_hits::total 53183 # number of ReadReq hits
369system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits
370system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits
371system.cpu.dcache.demand_hits::cpu.data 90016 # number of demand (read+write) hits
372system.cpu.dcache.demand_hits::total 90016 # number of demand (read+write) hits
373system.cpu.dcache.overall_hits::cpu.data 90016 # number of overall hits
374system.cpu.dcache.overall_hits::total 90016 # number of overall hits
375system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses
376system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses
377system.cpu.dcache.WriteReq_misses::cpu.data 396 # number of WriteReq misses
378system.cpu.dcache.WriteReq_misses::total 396 # number of WriteReq misses
379system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses
380system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses
381system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses
382system.cpu.dcache.overall_misses::total 499 # number of overall misses
383system.cpu.dcache.ReadReq_miss_latency::cpu.data 9627000 # number of ReadReq miss cycles
384system.cpu.dcache.ReadReq_miss_latency::total 9627000 # number of ReadReq miss cycles
385system.cpu.dcache.WriteReq_miss_latency::cpu.data 31678500 # number of WriteReq miss cycles
386system.cpu.dcache.WriteReq_miss_latency::total 31678500 # number of WriteReq miss cycles
387system.cpu.dcache.demand_miss_latency::cpu.data 41305500 # number of demand (read+write) miss cycles
388system.cpu.dcache.demand_miss_latency::total 41305500 # number of demand (read+write) miss cycles
389system.cpu.dcache.overall_miss_latency::cpu.data 41305500 # number of overall miss cycles
390system.cpu.dcache.overall_miss_latency::total 41305500 # number of overall miss cycles
391system.cpu.dcache.ReadReq_accesses::cpu.data 53286 # number of ReadReq accesses(hits+misses)
392system.cpu.dcache.ReadReq_accesses::total 53286 # number of ReadReq accesses(hits+misses)
393system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses)
394system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses)
395system.cpu.dcache.demand_accesses::cpu.data 90515 # number of demand (read+write) accesses
396system.cpu.dcache.demand_accesses::total 90515 # number of demand (read+write) accesses
397system.cpu.dcache.overall_accesses::cpu.data 90515 # number of overall (read+write) accesses
398system.cpu.dcache.overall_accesses::total 90515 # number of overall (read+write) accesses
399system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001933 # miss rate for ReadReq accesses
400system.cpu.dcache.ReadReq_miss_rate::total 0.001933 # miss rate for ReadReq accesses
401system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010637 # miss rate for WriteReq accesses
402system.cpu.dcache.WriteReq_miss_rate::total 0.010637 # miss rate for WriteReq accesses
403system.cpu.dcache.demand_miss_rate::cpu.data 0.005513 # miss rate for demand accesses
404system.cpu.dcache.demand_miss_rate::total 0.005513 # miss rate for demand accesses
405system.cpu.dcache.overall_miss_rate::cpu.data 0.005513 # miss rate for overall accesses
406system.cpu.dcache.overall_miss_rate::total 0.005513 # miss rate for overall accesses
407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93466.019417 # average ReadReq miss latency
408system.cpu.dcache.ReadReq_avg_miss_latency::total 93466.019417 # average ReadReq miss latency
409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79996.212121 # average WriteReq miss latency
410system.cpu.dcache.WriteReq_avg_miss_latency::total 79996.212121 # average WriteReq miss latency
411system.cpu.dcache.demand_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency
412system.cpu.dcache.demand_avg_miss_latency::total 82776.553106 # average overall miss latency
413system.cpu.dcache.overall_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency
414system.cpu.dcache.overall_avg_miss_latency::total 82776.553106 # average overall miss latency
415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
421system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits
422system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
423system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits
424system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits
425system.cpu.dcache.demand_mshr_hits::cpu.data 197 # number of demand (read+write) MSHR hits
426system.cpu.dcache.demand_mshr_hits::total 197 # number of demand (read+write) MSHR hits
427system.cpu.dcache.overall_mshr_hits::cpu.data 197 # number of overall MSHR hits
428system.cpu.dcache.overall_mshr_hits::total 197 # number of overall MSHR hits
429system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses
430system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses
431system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses
432system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses
433system.cpu.dcache.demand_mshr_misses::cpu.data 302 # number of demand (read+write) MSHR misses
434system.cpu.dcache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
435system.cpu.dcache.overall_mshr_misses::cpu.data 302 # number of overall MSHR misses
436system.cpu.dcache.overall_mshr_misses::total 302 # number of overall MSHR misses
437system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9014000 # number of ReadReq MSHR miss cycles
438system.cpu.dcache.ReadReq_mshr_miss_latency::total 9014000 # number of ReadReq MSHR miss cycles
439system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16356000 # number of WriteReq MSHR miss cycles
440system.cpu.dcache.WriteReq_mshr_miss_latency::total 16356000 # number of WriteReq MSHR miss cycles
441system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25370000 # number of demand (read+write) MSHR miss cycles
442system.cpu.dcache.demand_mshr_miss_latency::total 25370000 # number of demand (read+write) MSHR miss cycles
443system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25370000 # number of overall MSHR miss cycles
444system.cpu.dcache.overall_mshr_miss_latency::total 25370000 # number of overall MSHR miss cycles
445system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001820 # mshr miss rate for ReadReq accesses
446system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001820 # mshr miss rate for ReadReq accesses
447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005506 # mshr miss rate for WriteReq accesses
448system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005506 # mshr miss rate for WriteReq accesses
449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for demand accesses
450system.cpu.dcache.demand_mshr_miss_rate::total 0.003336 # mshr miss rate for demand accesses
451system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for overall accesses
452system.cpu.dcache.overall_mshr_miss_rate::total 0.003336 # mshr miss rate for overall accesses
453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92927.835052 # average ReadReq mshr miss latency
454system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92927.835052 # average ReadReq mshr miss latency
455system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79785.365854 # average WriteReq mshr miss latency
456system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79785.365854 # average WriteReq mshr miss latency
457system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency
458system.cpu.dcache.demand_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency
459system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency
460system.cpu.dcache.overall_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency
461system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
462system.cpu.icache.tags.replacements 69 # number of replacements
463system.cpu.icache.tags.tagsinuse 555.459146 # Cycle average of tags in use
464system.cpu.icache.tags.total_refs 101640 # Total number of references to valid blocks.
465system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks.
466system.cpu.icache.tags.avg_refs 96.707897 # Average number of references to valid blocks.
467system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
468system.cpu.icache.tags.occ_blocks::cpu.inst 555.459146 # Average occupied blocks per requestor
469system.cpu.icache.tags.occ_percent::cpu.inst 0.271220 # Average percentage of cache occupancy
470system.cpu.icache.tags.occ_percent::total 0.271220 # Average percentage of cache occupancy
471system.cpu.icache.tags.occ_task_id_blocks::1024 982 # Occupied blocks per task id
472system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id
473system.cpu.icache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id
474system.cpu.icache.tags.age_task_id_blocks_1024::2 724 # Occupied blocks per task id
475system.cpu.icache.tags.occ_task_id_percent::1024 0.479492 # Percentage of cache occupancy per task id
476system.cpu.icache.tags.tag_accesses 206433 # Number of tag accesses
477system.cpu.icache.tags.data_accesses 206433 # Number of data accesses
478system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
479system.cpu.icache.ReadReq_hits::cpu.inst 101640 # number of ReadReq hits
480system.cpu.icache.ReadReq_hits::total 101640 # number of ReadReq hits
481system.cpu.icache.demand_hits::cpu.inst 101640 # number of demand (read+write) hits
482system.cpu.icache.demand_hits::total 101640 # number of demand (read+write) hits
483system.cpu.icache.overall_hits::cpu.inst 101640 # number of overall hits
484system.cpu.icache.overall_hits::total 101640 # number of overall hits
485system.cpu.icache.ReadReq_misses::cpu.inst 1051 # number of ReadReq misses
486system.cpu.icache.ReadReq_misses::total 1051 # number of ReadReq misses
487system.cpu.icache.demand_misses::cpu.inst 1051 # number of demand (read+write) misses
488system.cpu.icache.demand_misses::total 1051 # number of demand (read+write) misses
489system.cpu.icache.overall_misses::cpu.inst 1051 # number of overall misses
490system.cpu.icache.overall_misses::total 1051 # number of overall misses
491system.cpu.icache.ReadReq_miss_latency::cpu.inst 87010500 # number of ReadReq miss cycles
492system.cpu.icache.ReadReq_miss_latency::total 87010500 # number of ReadReq miss cycles
493system.cpu.icache.demand_miss_latency::cpu.inst 87010500 # number of demand (read+write) miss cycles
494system.cpu.icache.demand_miss_latency::total 87010500 # number of demand (read+write) miss cycles
495system.cpu.icache.overall_miss_latency::cpu.inst 87010500 # number of overall miss cycles
496system.cpu.icache.overall_miss_latency::total 87010500 # number of overall miss cycles
497system.cpu.icache.ReadReq_accesses::cpu.inst 102691 # number of ReadReq accesses(hits+misses)
498system.cpu.icache.ReadReq_accesses::total 102691 # number of ReadReq accesses(hits+misses)
499system.cpu.icache.demand_accesses::cpu.inst 102691 # number of demand (read+write) accesses
500system.cpu.icache.demand_accesses::total 102691 # number of demand (read+write) accesses
501system.cpu.icache.overall_accesses::cpu.inst 102691 # number of overall (read+write) accesses
502system.cpu.icache.overall_accesses::total 102691 # number of overall (read+write) accesses
503system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010235 # miss rate for ReadReq accesses
504system.cpu.icache.ReadReq_miss_rate::total 0.010235 # miss rate for ReadReq accesses
505system.cpu.icache.demand_miss_rate::cpu.inst 0.010235 # miss rate for demand accesses
506system.cpu.icache.demand_miss_rate::total 0.010235 # miss rate for demand accesses
507system.cpu.icache.overall_miss_rate::cpu.inst 0.010235 # miss rate for overall accesses
508system.cpu.icache.overall_miss_rate::total 0.010235 # miss rate for overall accesses
509system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82788.296860 # average ReadReq miss latency
510system.cpu.icache.ReadReq_avg_miss_latency::total 82788.296860 # average ReadReq miss latency
511system.cpu.icache.demand_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency
512system.cpu.icache.demand_avg_miss_latency::total 82788.296860 # average overall miss latency
513system.cpu.icache.overall_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency
514system.cpu.icache.overall_avg_miss_latency::total 82788.296860 # average overall miss latency
515system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
516system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
517system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
518system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
519system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
520system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
521system.cpu.icache.writebacks::writebacks 69 # number of writebacks
522system.cpu.icache.writebacks::total 69 # number of writebacks
523system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1051 # number of ReadReq MSHR misses
524system.cpu.icache.ReadReq_mshr_misses::total 1051 # number of ReadReq MSHR misses
525system.cpu.icache.demand_mshr_misses::cpu.inst 1051 # number of demand (read+write) MSHR misses
526system.cpu.icache.demand_mshr_misses::total 1051 # number of demand (read+write) MSHR misses
527system.cpu.icache.overall_mshr_misses::cpu.inst 1051 # number of overall MSHR misses
528system.cpu.icache.overall_mshr_misses::total 1051 # number of overall MSHR misses
529system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 85959500 # number of ReadReq MSHR miss cycles
530system.cpu.icache.ReadReq_mshr_miss_latency::total 85959500 # number of ReadReq MSHR miss cycles
531system.cpu.icache.demand_mshr_miss_latency::cpu.inst 85959500 # number of demand (read+write) MSHR miss cycles
532system.cpu.icache.demand_mshr_miss_latency::total 85959500 # number of demand (read+write) MSHR miss cycles
533system.cpu.icache.overall_mshr_miss_latency::cpu.inst 85959500 # number of overall MSHR miss cycles
534system.cpu.icache.overall_mshr_miss_latency::total 85959500 # number of overall MSHR miss cycles
535system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for ReadReq accesses
536system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010235 # mshr miss rate for ReadReq accesses
537system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for demand accesses
538system.cpu.icache.demand_mshr_miss_rate::total 0.010235 # mshr miss rate for demand accesses
539system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for overall accesses
540system.cpu.icache.overall_mshr_miss_rate::total 0.010235 # mshr miss rate for overall accesses
541system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81788.296860 # average ReadReq mshr miss latency
542system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81788.296860 # average ReadReq mshr miss latency
543system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency
544system.cpu.icache.demand_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency
545system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency
546system.cpu.icache.overall_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency
547system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
548system.cpu.l2cache.tags.replacements 0 # number of replacements
549system.cpu.l2cache.tags.tagsinuse 826.940635 # Cycle average of tags in use
550system.cpu.l2cache.tags.total_refs 73 # Total number of references to valid blocks.
551system.cpu.l2cache.tags.sampled_refs 1349 # Sample count of references to valid blocks.
552system.cpu.l2cache.tags.avg_refs 0.054114 # Average number of references to valid blocks.
553system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
554system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.573058 # Average occupied blocks per requestor
555system.cpu.l2cache.tags.occ_blocks::cpu.data 241.367577 # Average occupied blocks per requestor
556system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017870 # Average percentage of cache occupancy
557system.cpu.l2cache.tags.occ_percent::cpu.data 0.007366 # Average percentage of cache occupancy
558system.cpu.l2cache.tags.occ_percent::total 0.025236 # Average percentage of cache occupancy
559system.cpu.l2cache.tags.occ_task_id_blocks::1024 1349 # Occupied blocks per task id
560system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
561system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id
562system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id
563system.cpu.l2cache.tags.occ_task_id_percent::1024 0.041168 # Percentage of cache occupancy per task id
564system.cpu.l2cache.tags.tag_accesses 12725 # Number of tag accesses
565system.cpu.l2cache.tags.data_accesses 12725 # Number of data accesses
566system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
567system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits
568system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits
569system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
570system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
571system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits
572system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits
573system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
574system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
575system.cpu.l2cache.demand_hits::total 4 # number of demand (read+write) hits
576system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
577system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
578system.cpu.l2cache.overall_hits::total 4 # number of overall hits
579system.cpu.l2cache.ReadExReq_misses::cpu.data 205 # number of ReadExReq misses
580system.cpu.l2cache.ReadExReq_misses::total 205 # number of ReadExReq misses
581system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1048 # number of ReadCleanReq misses
582system.cpu.l2cache.ReadCleanReq_misses::total 1048 # number of ReadCleanReq misses
583system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses
584system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses
585system.cpu.l2cache.demand_misses::cpu.inst 1048 # number of demand (read+write) misses
586system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses
587system.cpu.l2cache.demand_misses::total 1349 # number of demand (read+write) misses
588system.cpu.l2cache.overall_misses::cpu.inst 1048 # number of overall misses
589system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses
590system.cpu.l2cache.overall_misses::total 1349 # number of overall misses
591system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16048500 # number of ReadExReq miss cycles
592system.cpu.l2cache.ReadExReq_miss_latency::total 16048500 # number of ReadExReq miss cycles
593system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84351500 # number of ReadCleanReq miss cycles
594system.cpu.l2cache.ReadCleanReq_miss_latency::total 84351500 # number of ReadCleanReq miss cycles
595system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8856000 # number of ReadSharedReq miss cycles
596system.cpu.l2cache.ReadSharedReq_miss_latency::total 8856000 # number of ReadSharedReq miss cycles
597system.cpu.l2cache.demand_miss_latency::cpu.inst 84351500 # number of demand (read+write) miss cycles
598system.cpu.l2cache.demand_miss_latency::cpu.data 24904500 # number of demand (read+write) miss cycles
599system.cpu.l2cache.demand_miss_latency::total 109256000 # number of demand (read+write) miss cycles
600system.cpu.l2cache.overall_miss_latency::cpu.inst 84351500 # number of overall miss cycles
601system.cpu.l2cache.overall_miss_latency::cpu.data 24904500 # number of overall miss cycles
602system.cpu.l2cache.overall_miss_latency::total 109256000 # number of overall miss cycles
603system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses)
604system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses)
605system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses)
606system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses)
607system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1051 # number of ReadCleanReq accesses(hits+misses)
608system.cpu.l2cache.ReadCleanReq_accesses::total 1051 # number of ReadCleanReq accesses(hits+misses)
609system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses)
610system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses)
611system.cpu.l2cache.demand_accesses::cpu.inst 1051 # number of demand (read+write) accesses
612system.cpu.l2cache.demand_accesses::cpu.data 302 # number of demand (read+write) accesses
613system.cpu.l2cache.demand_accesses::total 1353 # number of demand (read+write) accesses
614system.cpu.l2cache.overall_accesses::cpu.inst 1051 # number of overall (read+write) accesses
615system.cpu.l2cache.overall_accesses::cpu.data 302 # number of overall (read+write) accesses
616system.cpu.l2cache.overall_accesses::total 1353 # number of overall (read+write) accesses
617system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
618system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
619system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997146 # miss rate for ReadCleanReq accesses
620system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997146 # miss rate for ReadCleanReq accesses
621system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.989691 # miss rate for ReadSharedReq accesses
622system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.989691 # miss rate for ReadSharedReq accesses
623system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997146 # miss rate for demand accesses
624system.cpu.l2cache.demand_miss_rate::cpu.data 0.996689 # miss rate for demand accesses
625system.cpu.l2cache.demand_miss_rate::total 0.997044 # miss rate for demand accesses
626system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997146 # miss rate for overall accesses
627system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689 # miss rate for overall accesses
628system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses
629system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency
630system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency
631system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80488.072519 # average ReadCleanReq miss latency
632system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80488.072519 # average ReadCleanReq miss latency
633system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92250 # average ReadSharedReq miss latency
634system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92250 # average ReadSharedReq miss latency
635system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency
636system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency
637system.cpu.l2cache.demand_avg_miss_latency::total 80990.363232 # average overall miss latency
638system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency
639system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency
640system.cpu.l2cache.overall_avg_miss_latency::total 80990.363232 # average overall miss latency
641system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
642system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
643system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
644system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
645system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
646system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
647system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses
648system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses
649system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1048 # number of ReadCleanReq MSHR misses
650system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1048 # number of ReadCleanReq MSHR misses
651system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses
652system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses
653system.cpu.l2cache.demand_mshr_misses::cpu.inst 1048 # number of demand (read+write) MSHR misses
654system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses
655system.cpu.l2cache.demand_mshr_misses::total 1349 # number of demand (read+write) MSHR misses
656system.cpu.l2cache.overall_mshr_misses::cpu.inst 1048 # number of overall MSHR misses
657system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses
658system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses
659system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles
660system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles
661system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73871500 # number of ReadCleanReq MSHR miss cycles
662system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73871500 # number of ReadCleanReq MSHR miss cycles
663system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7896000 # number of ReadSharedReq MSHR miss cycles
664system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7896000 # number of ReadSharedReq MSHR miss cycles
665system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73871500 # number of demand (read+write) MSHR miss cycles
666system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21894500 # number of demand (read+write) MSHR miss cycles
667system.cpu.l2cache.demand_mshr_miss_latency::total 95766000 # number of demand (read+write) MSHR miss cycles
668system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73871500 # number of overall MSHR miss cycles
669system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21894500 # number of overall MSHR miss cycles
670system.cpu.l2cache.overall_mshr_miss_latency::total 95766000 # number of overall MSHR miss cycles
671system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
672system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
673system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses
674system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997146 # mshr miss rate for ReadCleanReq accesses
675system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.989691 # mshr miss rate for ReadSharedReq accesses
676system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989691 # mshr miss rate for ReadSharedReq accesses
677system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for demand accesses
678system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for demand accesses
679system.cpu.l2cache.demand_mshr_miss_rate::total 0.997044 # mshr miss rate for demand accesses
680system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for overall accesses
681system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for overall accesses
682system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses
683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency
684system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency
685system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70488.072519 # average ReadCleanReq mshr miss latency
686system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70488.072519 # average ReadCleanReq mshr miss latency
687system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency
688system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82250 # average ReadSharedReq mshr miss latency
689system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency
690system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency
691system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency
692system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency
693system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency
694system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency
695system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter.
696system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data.
697system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
698system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
699system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
700system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
701system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
702system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution
703system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution
704system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution
705system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution
706system.cpu.toL2Bus.trans_dist::ReadCleanReq 1051 # Transaction distribution
707system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution
708system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171 # Packet count per connected master and slave (bytes)
709system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 604 # Packet count per connected master and slave (bytes)
710system.cpu.toL2Bus.pkt_count::total 2775 # Packet count per connected master and slave (bytes)
711system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 71680 # Cumulative packet size per connected master and slave (bytes)
712system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 19328 # Cumulative packet size per connected master and slave (bytes)
713system.cpu.toL2Bus.pkt_size::total 91008 # Cumulative packet size per connected master and slave (bytes)
714system.cpu.toL2Bus.snoops 0 # Total snoops (count)
715system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
716system.cpu.toL2Bus.snoop_fanout::samples 1353 # Request fanout histogram
717system.cpu.toL2Bus.snoop_fanout::mean 0.000739 # Request fanout histogram
718system.cpu.toL2Bus.snoop_fanout::stdev 0.027186 # Request fanout histogram
719system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
720system.cpu.toL2Bus.snoop_fanout::0 1352 99.93% 99.93% # Request fanout histogram
721system.cpu.toL2Bus.snoop_fanout::1 1 0.07% 100.00% # Request fanout histogram
722system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
723system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
724system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
725system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
726system.cpu.toL2Bus.snoop_fanout::total 1353 # Request fanout histogram
727system.cpu.toL2Bus.reqLayer0.occupancy 780000 # Layer occupancy (ticks)
728system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
729system.cpu.toL2Bus.respLayer0.occupancy 1576500 # Layer occupancy (ticks)
730system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
731system.cpu.toL2Bus.respLayer1.occupancy 453000 # Layer occupancy (ticks)
732system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
733system.membus.snoop_filter.tot_requests 1349 # Total number of requests made to the snoop filter.
734system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
735system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
736system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
737system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
738system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
739system.membus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
740system.membus.trans_dist::ReadResp 1144 # Transaction distribution
741system.membus.trans_dist::ReadExReq 205 # Transaction distribution
742system.membus.trans_dist::ReadExResp 205 # Transaction distribution
743system.membus.trans_dist::ReadSharedReq 1144 # Transaction distribution
744system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2698 # Packet count per connected master and slave (bytes)
745system.membus.pkt_count::total 2698 # Packet count per connected master and slave (bytes)
746system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 86336 # Cumulative packet size per connected master and slave (bytes)
747system.membus.pkt_size::total 86336 # Cumulative packet size per connected master and slave (bytes)
748system.membus.snoops 0 # Total snoops (count)
749system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
750system.membus.snoop_fanout::samples 1349 # Request fanout histogram
751system.membus.snoop_fanout::mean 0 # Request fanout histogram
752system.membus.snoop_fanout::stdev 0 # Request fanout histogram
753system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
754system.membus.snoop_fanout::0 1349 100.00% 100.00% # Request fanout histogram
755system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
756system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
757system.membus.snoop_fanout::min_value 0 # Request fanout histogram
758system.membus.snoop_fanout::max_value 0 # Request fanout histogram
759system.membus.snoop_fanout::total 1349 # Request fanout histogram
760system.membus.reqLayer0.occupancy 1553000 # Layer occupancy (ticks)
761system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
762system.membus.respLayer1.occupancy 7152500 # Layer occupancy (ticks)
763system.membus.respLayer1.utilization 2.6 # Layer utilization (%)
| 3sim_seconds 0.000414
4sim_ticks 414261500
5final_tick 414261500
6sim_freq 1000000000000
7host_inst_rate 4344
8host_op_rate 4357
9host_tick_rate 4323449
10host_mem_usage 272860
11host_seconds 95.81
12sim_insts 416240
13sim_ops 417493
14system.voltage_domain.voltage 1
15system.clk_domain.clock 1000
16system.physmem.pwrStateResidencyTicks::UNDEFINED 414261500
17system.physmem.bytes_read::cpu.inst 85248
18system.physmem.bytes_read::cpu.data 34368
19system.physmem.bytes_read::total 119616
20system.physmem.bytes_inst_read::cpu.inst 85248
21system.physmem.bytes_inst_read::total 85248
22system.physmem.num_reads::cpu.inst 1332
23system.physmem.num_reads::cpu.data 537
24system.physmem.num_reads::total 1869
25system.physmem.bw_read::cpu.inst 205783062
26system.physmem.bw_read::cpu.data 82962090
27system.physmem.bw_read::total 288745152
28system.physmem.bw_inst_read::cpu.inst 205783062
29system.physmem.bw_inst_read::total 205783062
30system.physmem.bw_total::cpu.inst 205783062
31system.physmem.bw_total::cpu.data 82962090
32system.physmem.bw_total::total 288745152
33system.physmem.readReqs 1869
34system.physmem.writeReqs 0
35system.physmem.readBursts 1869
36system.physmem.writeBursts 0
37system.physmem.bytesReadDRAM 119616
38system.physmem.bytesReadWrQ 0
39system.physmem.bytesWritten 0
40system.physmem.bytesReadSys 119616
41system.physmem.bytesWrittenSys 0
42system.physmem.servicedByWrQ 0
43system.physmem.mergedWrBursts 0
44system.physmem.neitherReadNorWriteReqs 0
45system.physmem.perBankRdBursts::0 238
46system.physmem.perBankRdBursts::1 263
47system.physmem.perBankRdBursts::2 168
48system.physmem.perBankRdBursts::3 170
49system.physmem.perBankRdBursts::4 149
50system.physmem.perBankRdBursts::5 98
51system.physmem.perBankRdBursts::6 118
52system.physmem.perBankRdBursts::7 65
53system.physmem.perBankRdBursts::8 62
54system.physmem.perBankRdBursts::9 64
55system.physmem.perBankRdBursts::10 21
56system.physmem.perBankRdBursts::11 43
57system.physmem.perBankRdBursts::12 80
58system.physmem.perBankRdBursts::13 100
59system.physmem.perBankRdBursts::14 109
60system.physmem.perBankRdBursts::15 121
61system.physmem.perBankWrBursts::0 0
62system.physmem.perBankWrBursts::1 0
63system.physmem.perBankWrBursts::2 0
64system.physmem.perBankWrBursts::3 0
65system.physmem.perBankWrBursts::4 0
66system.physmem.perBankWrBursts::5 0
67system.physmem.perBankWrBursts::6 0
68system.physmem.perBankWrBursts::7 0
69system.physmem.perBankWrBursts::8 0
70system.physmem.perBankWrBursts::9 0
71system.physmem.perBankWrBursts::10 0
72system.physmem.perBankWrBursts::11 0
73system.physmem.perBankWrBursts::12 0
74system.physmem.perBankWrBursts::13 0
75system.physmem.perBankWrBursts::14 0
76system.physmem.perBankWrBursts::15 0
77system.physmem.numRdRetry 0
78system.physmem.numWrRetry 0
79system.physmem.totGap 414165000
80system.physmem.readPktSize::0 0
81system.physmem.readPktSize::1 0
82system.physmem.readPktSize::2 0
83system.physmem.readPktSize::3 0
84system.physmem.readPktSize::4 0
85system.physmem.readPktSize::5 0
86system.physmem.readPktSize::6 1869
87system.physmem.writePktSize::0 0
88system.physmem.writePktSize::1 0
89system.physmem.writePktSize::2 0
90system.physmem.writePktSize::3 0
91system.physmem.writePktSize::4 0
92system.physmem.writePktSize::5 0
93system.physmem.writePktSize::6 0
94system.physmem.rdQLenPdf::0 1655
95system.physmem.rdQLenPdf::1 200
96system.physmem.rdQLenPdf::2 14
97system.physmem.rdQLenPdf::3 0
98system.physmem.rdQLenPdf::4 0
99system.physmem.rdQLenPdf::5 0
100system.physmem.rdQLenPdf::6 0
101system.physmem.rdQLenPdf::7 0
102system.physmem.rdQLenPdf::8 0
103system.physmem.rdQLenPdf::9 0
104system.physmem.rdQLenPdf::10 0
105system.physmem.rdQLenPdf::11 0
106system.physmem.rdQLenPdf::12 0
107system.physmem.rdQLenPdf::13 0
108system.physmem.rdQLenPdf::14 0
109system.physmem.rdQLenPdf::15 0
110system.physmem.rdQLenPdf::16 0
111system.physmem.rdQLenPdf::17 0
112system.physmem.rdQLenPdf::18 0
113system.physmem.rdQLenPdf::19 0
114system.physmem.rdQLenPdf::20 0
115system.physmem.rdQLenPdf::21 0
116system.physmem.rdQLenPdf::22 0
117system.physmem.rdQLenPdf::23 0
118system.physmem.rdQLenPdf::24 0
119system.physmem.rdQLenPdf::25 0
120system.physmem.rdQLenPdf::26 0
121system.physmem.rdQLenPdf::27 0
122system.physmem.rdQLenPdf::28 0
123system.physmem.rdQLenPdf::29 0
124system.physmem.rdQLenPdf::30 0
125system.physmem.rdQLenPdf::31 0
126system.physmem.wrQLenPdf::0 0
127system.physmem.wrQLenPdf::1 0
128system.physmem.wrQLenPdf::2 0
129system.physmem.wrQLenPdf::3 0
130system.physmem.wrQLenPdf::4 0
131system.physmem.wrQLenPdf::5 0
132system.physmem.wrQLenPdf::6 0
133system.physmem.wrQLenPdf::7 0
134system.physmem.wrQLenPdf::8 0
135system.physmem.wrQLenPdf::9 0
136system.physmem.wrQLenPdf::10 0
137system.physmem.wrQLenPdf::11 0
138system.physmem.wrQLenPdf::12 0
139system.physmem.wrQLenPdf::13 0
140system.physmem.wrQLenPdf::14 0
141system.physmem.wrQLenPdf::15 0
142system.physmem.wrQLenPdf::16 0
143system.physmem.wrQLenPdf::17 0
144system.physmem.wrQLenPdf::18 0
145system.physmem.wrQLenPdf::19 0
146system.physmem.wrQLenPdf::20 0
147system.physmem.wrQLenPdf::21 0
148system.physmem.wrQLenPdf::22 0
149system.physmem.wrQLenPdf::23 0
150system.physmem.wrQLenPdf::24 0
151system.physmem.wrQLenPdf::25 0
152system.physmem.wrQLenPdf::26 0
153system.physmem.wrQLenPdf::27 0
154system.physmem.wrQLenPdf::28 0
155system.physmem.wrQLenPdf::29 0
156system.physmem.wrQLenPdf::30 0
157system.physmem.wrQLenPdf::31 0
158system.physmem.wrQLenPdf::32 0
159system.physmem.wrQLenPdf::33 0
160system.physmem.wrQLenPdf::34 0
161system.physmem.wrQLenPdf::35 0
162system.physmem.wrQLenPdf::36 0
163system.physmem.wrQLenPdf::37 0
164system.physmem.wrQLenPdf::38 0
165system.physmem.wrQLenPdf::39 0
166system.physmem.wrQLenPdf::40 0
167system.physmem.wrQLenPdf::41 0
168system.physmem.wrQLenPdf::42 0
169system.physmem.wrQLenPdf::43 0
170system.physmem.wrQLenPdf::44 0
171system.physmem.wrQLenPdf::45 0
172system.physmem.wrQLenPdf::46 0
173system.physmem.wrQLenPdf::47 0
174system.physmem.wrQLenPdf::48 0
175system.physmem.wrQLenPdf::49 0
176system.physmem.wrQLenPdf::50 0
177system.physmem.wrQLenPdf::51 0
178system.physmem.wrQLenPdf::52 0
179system.physmem.wrQLenPdf::53 0
180system.physmem.wrQLenPdf::54 0
181system.physmem.wrQLenPdf::55 0
182system.physmem.wrQLenPdf::56 0
183system.physmem.wrQLenPdf::57 0
184system.physmem.wrQLenPdf::58 0
185system.physmem.wrQLenPdf::59 0
186system.physmem.wrQLenPdf::60 0
187system.physmem.wrQLenPdf::61 0
188system.physmem.wrQLenPdf::62 0
189system.physmem.wrQLenPdf::63 0
190system.physmem.bytesPerActivate::samples 398
191system.physmem.bytesPerActivate::mean 295.557788
192system.physmem.bytesPerActivate::gmean 206.933383
193system.physmem.bytesPerActivate::stdev 254.300651
194system.physmem.bytesPerActivate::0-127 93 23.36% 23.36%
195system.physmem.bytesPerActivate::128-255 118 29.64% 53.01%
196system.physmem.bytesPerActivate::256-383 64 16.08% 69.09%
197system.physmem.bytesPerActivate::384-511 48 12.06% 81.15%
198system.physmem.bytesPerActivate::512-639 28 7.03% 88.19%
199system.physmem.bytesPerActivate::640-767 16 4.02% 92.21%
200system.physmem.bytesPerActivate::768-895 8 2.01% 94.22%
201system.physmem.bytesPerActivate::896-1023 7 1.75% 95.97%
202system.physmem.bytesPerActivate::1024-1151 16 4.02% 99.99%
203system.physmem.bytesPerActivate::total 398
204system.physmem.totQLat 24652500
205system.physmem.totMemAccLat 59696250
206system.physmem.totBusLat 9345000
207system.physmem.avgQLat 13190.20
208system.physmem.avgBusLat 5000.00
209system.physmem.avgMemAccLat 31940.20
210system.physmem.avgRdBW 288.74
211system.physmem.avgWrBW 0.00
212system.physmem.avgRdBWSys 288.74
213system.physmem.avgWrBWSys 0.00
214system.physmem.peakBW 12800.00
215system.physmem.busUtil 2.25
216system.physmem.busUtilRead 2.25
217system.physmem.busUtilWrite 0.00
218system.physmem.avgRdQLen 1.06
219system.physmem.avgWrQLen 0.00
220system.physmem.readRowHits 1463
221system.physmem.writeRowHits 0
222system.physmem.readRowHitRate 78.27
223system.physmem.writeRowHitRate nan
224system.physmem.avgGap 221597.11
225system.physmem.pageHitRate 78.27
226system.physmem_0.actEnergy 1992060
227system.physmem_0.preEnergy 1051215
228system.physmem_0.readEnergy 9060660
229system.physmem_0.writeEnergy 0
230system.physmem_0.refreshEnergy 32575920
231system.physmem_0.actBackEnergy 22658070
232system.physmem_0.preBackEnergy 684000
233system.physmem_0.actPowerDownEnergy 159927750
234system.physmem_0.prePowerDownEnergy 4636320
235system.physmem_0.selfRefreshEnergy 0
236system.physmem_0.totalEnergy 232585995
237system.physmem_0.averagePower 561.445931
238system.physmem_0.totalIdleTime 362517500
239system.physmem_0.memoryStateTime::IDLE 318000
240system.physmem_0.memoryStateTime::REF 13780000
241system.physmem_0.memoryStateTime::SREF 0
242system.physmem_0.memoryStateTime::PRE_PDN 12066000
243system.physmem_0.memoryStateTime::ACT 37356750
244system.physmem_0.memoryStateTime::ACT_PDN 350740750
245system.physmem_1.actEnergy 906780
246system.physmem_1.preEnergy 459195
247system.physmem_1.readEnergy 4284000
248system.physmem_1.writeEnergy 0
249system.physmem_1.refreshEnergy 15366000
250system.physmem_1.actBackEnergy 12000210
251system.physmem_1.preBackEnergy 728640
252system.physmem_1.actPowerDownEnergy 52156140
253system.physmem_1.prePowerDownEnergy 13950720
254system.physmem_1.selfRefreshEnergy 58138620
255system.physmem_1.totalEnergy 157990305
256system.physmem_1.averagePower 381.377278
257system.physmem_1.totalIdleTime 386011000
258system.physmem_1.memoryStateTime::IDLE 1203000
259system.physmem_1.memoryStateTime::REF 6518000
260system.physmem_1.memoryStateTime::SREF 235342000
261system.physmem_1.memoryStateTime::PRE_PDN 36329000
262system.physmem_1.memoryStateTime::ACT 20483500
263system.physmem_1.memoryStateTime::ACT_PDN 114386000
264system.pwrStateResidencyTicks::UNDEFINED 414261500
265system.cpu.branchPred.lookups 113788
266system.cpu.branchPred.condPredicted 80533
267system.cpu.branchPred.condIncorrect 8262
268system.cpu.branchPred.BTBLookups 70464
269system.cpu.branchPred.BTBHits 37407
270system.cpu.branchPred.BTBCorrect 0
271system.cpu.branchPred.BTBHitPct 53.086682
272system.cpu.branchPred.usedRAS 0
273system.cpu.branchPred.RASInCorrect 0
274system.cpu.branchPred.indirectLookups 22847
275system.cpu.branchPred.indirectHits 13810
276system.cpu.branchPred.indirectMisses 9037
277system.cpu.branchPredindirectMispredicted 4771
278system.cpu_clk_domain.clock 500
279system.cpu.dtb.read_hits 0
280system.cpu.dtb.read_misses 0
281system.cpu.dtb.read_accesses 0
282system.cpu.dtb.write_hits 0
283system.cpu.dtb.write_misses 0
284system.cpu.dtb.write_accesses 0
285system.cpu.dtb.hits 0
286system.cpu.dtb.misses 0
287system.cpu.dtb.accesses 0
288system.cpu.itb.read_hits 0
289system.cpu.itb.read_misses 0
290system.cpu.itb.read_accesses 0
291system.cpu.itb.write_hits 0
292system.cpu.itb.write_misses 0
293system.cpu.itb.write_accesses 0
294system.cpu.itb.hits 0
295system.cpu.itb.misses 0
296system.cpu.itb.accesses 0
297system.cpu.workload.numSyscalls 216
298system.cpu.pwrStateResidencyTicks::ON 414261500
299system.cpu.numCycles 828523
300system.cpu.numWorkItemsStarted 0
301system.cpu.numWorkItemsCompleted 0
302system.cpu.committedInsts 416240
303system.cpu.committedOps 417493
304system.cpu.discardedOps 21677
305system.cpu.numFetchSuspends 0
306system.cpu.cpi 1.990493
307system.cpu.ipc 0.502387
308system.cpu.op_class_0::No_OpClass 236 0.05% 0.05%
309system.cpu.op_class_0::IntAlu 245871 58.89% 58.94%
310system.cpu.op_class_0::IntMult 674 0.16% 59.11%
311system.cpu.op_class_0::IntDiv 644 0.15% 59.26%
312system.cpu.op_class_0::FloatAdd 128 0.03% 59.29%
313system.cpu.op_class_0::FloatCmp 161 0.03% 59.33%
314system.cpu.op_class_0::FloatCvt 109 0.02% 59.35%
315system.cpu.op_class_0::FloatMult 30 0.00% 59.36%
316system.cpu.op_class_0::FloatMultAcc 0 0.00% 59.36%
317system.cpu.op_class_0::FloatDiv 11 0.00% 59.36%
318system.cpu.op_class_0::FloatMisc 0 0.00% 59.36%
319system.cpu.op_class_0::FloatSqrt 5 0.00% 59.37%
320system.cpu.op_class_0::SimdAdd 0 0.00% 59.37%
321system.cpu.op_class_0::SimdAddAcc 0 0.00% 59.37%
322system.cpu.op_class_0::SimdAlu 0 0.00% 59.37%
323system.cpu.op_class_0::SimdCmp 0 0.00% 59.37%
324system.cpu.op_class_0::SimdCvt 0 0.00% 59.37%
325system.cpu.op_class_0::SimdMisc 0 0.00% 59.37%
326system.cpu.op_class_0::SimdMult 0 0.00% 59.37%
327system.cpu.op_class_0::SimdMultAcc 0 0.00% 59.37%
328system.cpu.op_class_0::SimdShift 0 0.00% 59.37%
329system.cpu.op_class_0::SimdShiftAcc 0 0.00% 59.37%
330system.cpu.op_class_0::SimdSqrt 0 0.00% 59.37%
331system.cpu.op_class_0::SimdFloatAdd 0 0.00% 59.37%
332system.cpu.op_class_0::SimdFloatAlu 0 0.00% 59.37%
333system.cpu.op_class_0::SimdFloatCmp 0 0.00% 59.37%
334system.cpu.op_class_0::SimdFloatCvt 0 0.00% 59.37%
335system.cpu.op_class_0::SimdFloatDiv 0 0.00% 59.37%
336system.cpu.op_class_0::SimdFloatMisc 0 0.00% 59.37%
337system.cpu.op_class_0::SimdFloatMult 0 0.00% 59.37%
338system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 59.37%
339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 59.37%
340system.cpu.op_class_0::MemRead 104951 25.13% 84.50%
341system.cpu.op_class_0::MemWrite 63954 15.31% 99.82%
342system.cpu.op_class_0::FloatMemRead 547 0.13% 99.95%
343system.cpu.op_class_0::FloatMemWrite 172 0.04% 99.99%
344system.cpu.op_class_0::IprAccess 0 0.00% 99.99%
345system.cpu.op_class_0::InstPrefetch 0 0.00% 99.99%
346system.cpu.op_class_0::total 417493
347system.cpu.tickCycles 557012
348system.cpu.idleCycles 271511
349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 414261500
350system.cpu.dcache.tags.replacements 2
351system.cpu.dcache.tags.tagsinuse 414.110238
352system.cpu.dcache.tags.total_refs 172703
353system.cpu.dcache.tags.sampled_refs 538
354system.cpu.dcache.tags.avg_refs 321.009293
355system.cpu.dcache.tags.warmup_cycle 0
356system.cpu.dcache.tags.occ_blocks::cpu.data 414.110238
357system.cpu.dcache.tags.occ_percent::cpu.data 0.101101
358system.cpu.dcache.tags.occ_percent::total 0.101101
359system.cpu.dcache.tags.occ_task_id_blocks::1024 536
360system.cpu.dcache.tags.age_task_id_blocks_1024::0 15
361system.cpu.dcache.tags.age_task_id_blocks_1024::1 24
362system.cpu.dcache.tags.age_task_id_blocks_1024::2 497
363system.cpu.dcache.tags.occ_task_id_percent::1024 0.130859
364system.cpu.dcache.tags.tag_accesses 347344
365system.cpu.dcache.tags.data_accesses 347344
366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 414261500
367system.cpu.dcache.ReadReq_hits::cpu.data 107273
368system.cpu.dcache.ReadReq_hits::total 107273
369system.cpu.dcache.WriteReq_hits::cpu.data 62050
370system.cpu.dcache.WriteReq_hits::total 62050
371system.cpu.dcache.LoadLockedReq_hits::cpu.data 1689
372system.cpu.dcache.LoadLockedReq_hits::total 1689
373system.cpu.dcache.StoreCondReq_hits::cpu.data 1691
374system.cpu.dcache.StoreCondReq_hits::total 1691
375system.cpu.dcache.demand_hits::cpu.data 169323
376system.cpu.dcache.demand_hits::total 169323
377system.cpu.dcache.overall_hits::cpu.data 169323
378system.cpu.dcache.overall_hits::total 169323
379system.cpu.dcache.ReadReq_misses::cpu.data 313
380system.cpu.dcache.ReadReq_misses::total 313
381system.cpu.dcache.WriteReq_misses::cpu.data 385
382system.cpu.dcache.WriteReq_misses::total 385
383system.cpu.dcache.LoadLockedReq_misses::cpu.data 2
384system.cpu.dcache.LoadLockedReq_misses::total 2
385system.cpu.dcache.demand_misses::cpu.data 698
386system.cpu.dcache.demand_misses::total 698
387system.cpu.dcache.overall_misses::cpu.data 698
388system.cpu.dcache.overall_misses::total 698
389system.cpu.dcache.ReadReq_miss_latency::cpu.data 27269500
390system.cpu.dcache.ReadReq_miss_latency::total 27269500
391system.cpu.dcache.WriteReq_miss_latency::cpu.data 31180500
392system.cpu.dcache.WriteReq_miss_latency::total 31180500
393system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 198500
394system.cpu.dcache.LoadLockedReq_miss_latency::total 198500
395system.cpu.dcache.demand_miss_latency::cpu.data 58450000
396system.cpu.dcache.demand_miss_latency::total 58450000
397system.cpu.dcache.overall_miss_latency::cpu.data 58450000
398system.cpu.dcache.overall_miss_latency::total 58450000
399system.cpu.dcache.ReadReq_accesses::cpu.data 107586
400system.cpu.dcache.ReadReq_accesses::total 107586
401system.cpu.dcache.WriteReq_accesses::cpu.data 62435
402system.cpu.dcache.WriteReq_accesses::total 62435
403system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1691
404system.cpu.dcache.LoadLockedReq_accesses::total 1691
405system.cpu.dcache.StoreCondReq_accesses::cpu.data 1691
406system.cpu.dcache.StoreCondReq_accesses::total 1691
407system.cpu.dcache.demand_accesses::cpu.data 170021
408system.cpu.dcache.demand_accesses::total 170021
409system.cpu.dcache.overall_accesses::cpu.data 170021
410system.cpu.dcache.overall_accesses::total 170021
411system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002909
412system.cpu.dcache.ReadReq_miss_rate::total 0.002909
413system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006166
414system.cpu.dcache.WriteReq_miss_rate::total 0.006166
415system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001182
416system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001182
417system.cpu.dcache.demand_miss_rate::cpu.data 0.004105
418system.cpu.dcache.demand_miss_rate::total 0.004105
419system.cpu.dcache.overall_miss_rate::cpu.data 0.004105
420system.cpu.dcache.overall_miss_rate::total 0.004105
421system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 87123.003194
422system.cpu.dcache.ReadReq_avg_miss_latency::total 87123.003194
423system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80988.311688
424system.cpu.dcache.WriteReq_avg_miss_latency::total 80988.311688
425system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99250
426system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99250
427system.cpu.dcache.demand_avg_miss_latency::cpu.data 83739.255014
428system.cpu.dcache.demand_avg_miss_latency::total 83739.255014
429system.cpu.dcache.overall_avg_miss_latency::cpu.data 83739.255014
430system.cpu.dcache.overall_avg_miss_latency::total 83739.255014
431system.cpu.dcache.blocked_cycles::no_mshrs 0
432system.cpu.dcache.blocked_cycles::no_targets 0
433system.cpu.dcache.blocked::no_mshrs 0
434system.cpu.dcache.blocked::no_targets 0
435system.cpu.dcache.avg_blocked_cycles::no_mshrs nan
436system.cpu.dcache.avg_blocked_cycles::no_targets nan
437system.cpu.dcache.writebacks::writebacks 2
438system.cpu.dcache.writebacks::total 2
439system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3
440system.cpu.dcache.ReadReq_mshr_hits::total 3
441system.cpu.dcache.WriteReq_mshr_hits::cpu.data 159
442system.cpu.dcache.WriteReq_mshr_hits::total 159
443system.cpu.dcache.demand_mshr_hits::cpu.data 162
444system.cpu.dcache.demand_mshr_hits::total 162
445system.cpu.dcache.overall_mshr_hits::cpu.data 162
446system.cpu.dcache.overall_mshr_hits::total 162
447system.cpu.dcache.ReadReq_mshr_misses::cpu.data 310
448system.cpu.dcache.ReadReq_mshr_misses::total 310
449system.cpu.dcache.WriteReq_mshr_misses::cpu.data 226
450system.cpu.dcache.WriteReq_mshr_misses::total 226
451system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 2
452system.cpu.dcache.LoadLockedReq_mshr_misses::total 2
453system.cpu.dcache.demand_mshr_misses::cpu.data 536
454system.cpu.dcache.demand_mshr_misses::total 536
455system.cpu.dcache.overall_mshr_misses::cpu.data 536
456system.cpu.dcache.overall_mshr_misses::total 536
457system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26720000
458system.cpu.dcache.ReadReq_mshr_miss_latency::total 26720000
459system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 18848500
460system.cpu.dcache.WriteReq_mshr_miss_latency::total 18848500
461system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196500
462system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196500
463system.cpu.dcache.demand_mshr_miss_latency::cpu.data 45568500
464system.cpu.dcache.demand_mshr_miss_latency::total 45568500
465system.cpu.dcache.overall_mshr_miss_latency::cpu.data 45568500
466system.cpu.dcache.overall_mshr_miss_latency::total 45568500
467system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002881
468system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002881
469system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003619
470system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003619
471system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.001182
472system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.001182
473system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003152
474system.cpu.dcache.demand_mshr_miss_rate::total 0.003152
475system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003152
476system.cpu.dcache.overall_mshr_miss_rate::total 0.003152
477system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86193.548387
478system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86193.548387
479system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83400.442477
480system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83400.442477
481system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 98250
482system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 98250
483system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85015.858208
484system.cpu.dcache.demand_avg_mshr_miss_latency::total 85015.858208
485system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85015.858208
486system.cpu.dcache.overall_avg_mshr_miss_latency::total 85015.858208
487system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 414261500
488system.cpu.icache.tags.replacements 118
489system.cpu.icache.tags.tagsinuse 820.164908
490system.cpu.icache.tags.total_refs 153400
491system.cpu.icache.tags.sampled_refs 1339
492system.cpu.icache.tags.avg_refs 114.563106
493system.cpu.icache.tags.warmup_cycle 0
494system.cpu.icache.tags.occ_blocks::cpu.inst 820.164908
495system.cpu.icache.tags.occ_percent::cpu.inst 0.400471
496system.cpu.icache.tags.occ_percent::total 0.400471
497system.cpu.icache.tags.occ_task_id_blocks::1024 1221
498system.cpu.icache.tags.age_task_id_blocks_1024::0 51
499system.cpu.icache.tags.age_task_id_blocks_1024::1 123
500system.cpu.icache.tags.age_task_id_blocks_1024::2 1047
501system.cpu.icache.tags.occ_task_id_percent::1024 0.596191
502system.cpu.icache.tags.tag_accesses 310819
503system.cpu.icache.tags.data_accesses 310819
504system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 414261500
505system.cpu.icache.ReadReq_hits::cpu.inst 153400
506system.cpu.icache.ReadReq_hits::total 153400
507system.cpu.icache.demand_hits::cpu.inst 153400
508system.cpu.icache.demand_hits::total 153400
509system.cpu.icache.overall_hits::cpu.inst 153400
510system.cpu.icache.overall_hits::total 153400
511system.cpu.icache.ReadReq_misses::cpu.inst 1340
512system.cpu.icache.ReadReq_misses::total 1340
513system.cpu.icache.demand_misses::cpu.inst 1340
514system.cpu.icache.demand_misses::total 1340
515system.cpu.icache.overall_misses::cpu.inst 1340
516system.cpu.icache.overall_misses::total 1340
517system.cpu.icache.ReadReq_miss_latency::cpu.inst 113521500
518system.cpu.icache.ReadReq_miss_latency::total 113521500
519system.cpu.icache.demand_miss_latency::cpu.inst 113521500
520system.cpu.icache.demand_miss_latency::total 113521500
521system.cpu.icache.overall_miss_latency::cpu.inst 113521500
522system.cpu.icache.overall_miss_latency::total 113521500
523system.cpu.icache.ReadReq_accesses::cpu.inst 154740
524system.cpu.icache.ReadReq_accesses::total 154740
525system.cpu.icache.demand_accesses::cpu.inst 154740
526system.cpu.icache.demand_accesses::total 154740
527system.cpu.icache.overall_accesses::cpu.inst 154740
528system.cpu.icache.overall_accesses::total 154740
529system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008659
530system.cpu.icache.ReadReq_miss_rate::total 0.008659
531system.cpu.icache.demand_miss_rate::cpu.inst 0.008659
532system.cpu.icache.demand_miss_rate::total 0.008659
533system.cpu.icache.overall_miss_rate::cpu.inst 0.008659
534system.cpu.icache.overall_miss_rate::total 0.008659
535system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84717.537313
536system.cpu.icache.ReadReq_avg_miss_latency::total 84717.537313
537system.cpu.icache.demand_avg_miss_latency::cpu.inst 84717.537313
538system.cpu.icache.demand_avg_miss_latency::total 84717.537313
539system.cpu.icache.overall_avg_miss_latency::cpu.inst 84717.537313
540system.cpu.icache.overall_avg_miss_latency::total 84717.537313
541system.cpu.icache.blocked_cycles::no_mshrs 0
542system.cpu.icache.blocked_cycles::no_targets 0
543system.cpu.icache.blocked::no_mshrs 0
544system.cpu.icache.blocked::no_targets 0
545system.cpu.icache.avg_blocked_cycles::no_mshrs nan
546system.cpu.icache.avg_blocked_cycles::no_targets nan
547system.cpu.icache.writebacks::writebacks 118
548system.cpu.icache.writebacks::total 118
549system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1340
550system.cpu.icache.ReadReq_mshr_misses::total 1340
551system.cpu.icache.demand_mshr_misses::cpu.inst 1340
552system.cpu.icache.demand_mshr_misses::total 1340
553system.cpu.icache.overall_mshr_misses::cpu.inst 1340
554system.cpu.icache.overall_mshr_misses::total 1340
555system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 112182500
556system.cpu.icache.ReadReq_mshr_miss_latency::total 112182500
557system.cpu.icache.demand_mshr_miss_latency::cpu.inst 112182500
558system.cpu.icache.demand_mshr_miss_latency::total 112182500
559system.cpu.icache.overall_mshr_miss_latency::cpu.inst 112182500
560system.cpu.icache.overall_mshr_miss_latency::total 112182500
561system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008659
562system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008659
563system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008659
564system.cpu.icache.demand_mshr_miss_rate::total 0.008659
565system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008659
566system.cpu.icache.overall_mshr_miss_rate::total 0.008659
567system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83718.283582
568system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83718.283582
569system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83718.283582
570system.cpu.icache.demand_avg_mshr_miss_latency::total 83718.283582
571system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83718.283582
572system.cpu.icache.overall_avg_mshr_miss_latency::total 83718.283582
573system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 414261500
574system.cpu.l2cache.tags.replacements 0
575system.cpu.l2cache.tags.tagsinuse 1287.297048
576system.cpu.l2cache.tags.total_refs 128
577system.cpu.l2cache.tags.sampled_refs 1869
578system.cpu.l2cache.tags.avg_refs 0.068485
579system.cpu.l2cache.tags.warmup_cycle 0
580system.cpu.l2cache.tags.occ_blocks::cpu.inst 873.530918
581system.cpu.l2cache.tags.occ_blocks::cpu.data 413.766129
582system.cpu.l2cache.tags.occ_percent::cpu.inst 0.026658
583system.cpu.l2cache.tags.occ_percent::cpu.data 0.012627
584system.cpu.l2cache.tags.occ_percent::total 0.039285
585system.cpu.l2cache.tags.occ_task_id_blocks::1024 1869
586system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65
587system.cpu.l2cache.tags.age_task_id_blocks_1024::1 147
588system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1657
589system.cpu.l2cache.tags.occ_task_id_percent::1024 0.057037
590system.cpu.l2cache.tags.tag_accesses 17853
591system.cpu.l2cache.tags.data_accesses 17853
592system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 414261500
593system.cpu.l2cache.WritebackDirty_hits::writebacks 2
594system.cpu.l2cache.WritebackDirty_hits::total 2
595system.cpu.l2cache.WritebackClean_hits::writebacks 118
596system.cpu.l2cache.WritebackClean_hits::total 118
597system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 7
598system.cpu.l2cache.ReadCleanReq_hits::total 7
599system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1
600system.cpu.l2cache.ReadSharedReq_hits::total 1
601system.cpu.l2cache.demand_hits::cpu.inst 7
602system.cpu.l2cache.demand_hits::cpu.data 1
603system.cpu.l2cache.demand_hits::total 8
604system.cpu.l2cache.overall_hits::cpu.inst 7
605system.cpu.l2cache.overall_hits::cpu.data 1
606system.cpu.l2cache.overall_hits::total 8
607system.cpu.l2cache.ReadExReq_misses::cpu.data 226
608system.cpu.l2cache.ReadExReq_misses::total 226
609system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1333
610system.cpu.l2cache.ReadCleanReq_misses::total 1333
611system.cpu.l2cache.ReadSharedReq_misses::cpu.data 311
612system.cpu.l2cache.ReadSharedReq_misses::total 311
613system.cpu.l2cache.demand_misses::cpu.inst 1333
614system.cpu.l2cache.demand_misses::cpu.data 537
615system.cpu.l2cache.demand_misses::total 1870
616system.cpu.l2cache.overall_misses::cpu.inst 1333
617system.cpu.l2cache.overall_misses::cpu.data 537
618system.cpu.l2cache.overall_misses::total 1870
619system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18508000
620system.cpu.l2cache.ReadExReq_miss_latency::total 18508000
621system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 110100500
622system.cpu.l2cache.ReadCleanReq_miss_latency::total 110100500
623system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 26435000
624system.cpu.l2cache.ReadSharedReq_miss_latency::total 26435000
625system.cpu.l2cache.demand_miss_latency::cpu.inst 110100500
626system.cpu.l2cache.demand_miss_latency::cpu.data 44943000
627system.cpu.l2cache.demand_miss_latency::total 155043500
628system.cpu.l2cache.overall_miss_latency::cpu.inst 110100500
629system.cpu.l2cache.overall_miss_latency::cpu.data 44943000
630system.cpu.l2cache.overall_miss_latency::total 155043500
631system.cpu.l2cache.WritebackDirty_accesses::writebacks 2
632system.cpu.l2cache.WritebackDirty_accesses::total 2
633system.cpu.l2cache.WritebackClean_accesses::writebacks 118
634system.cpu.l2cache.WritebackClean_accesses::total 118
635system.cpu.l2cache.ReadExReq_accesses::cpu.data 226
636system.cpu.l2cache.ReadExReq_accesses::total 226
637system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1340
638system.cpu.l2cache.ReadCleanReq_accesses::total 1340
639system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 312
640system.cpu.l2cache.ReadSharedReq_accesses::total 312
641system.cpu.l2cache.demand_accesses::cpu.inst 1340
642system.cpu.l2cache.demand_accesses::cpu.data 538
643system.cpu.l2cache.demand_accesses::total 1878
644system.cpu.l2cache.overall_accesses::cpu.inst 1340
645system.cpu.l2cache.overall_accesses::cpu.data 538
646system.cpu.l2cache.overall_accesses::total 1878
647system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1
648system.cpu.l2cache.ReadExReq_miss_rate::total 1
649system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.994776
650system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.994776
651system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.996794
652system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.996794
653system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994776
654system.cpu.l2cache.demand_miss_rate::cpu.data 0.998141
655system.cpu.l2cache.demand_miss_rate::total 0.995740
656system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994776
657system.cpu.l2cache.overall_miss_rate::cpu.data 0.998141
658system.cpu.l2cache.overall_miss_rate::total 0.995740
659system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81893.805309
660system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81893.805309
661system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82596.024006
662system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82596.024006
663system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85000
664system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85000
665system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82596.024006
666system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83692.737430
667system.cpu.l2cache.demand_avg_miss_latency::total 82910.962566
668system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82596.024006
669system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83692.737430
670system.cpu.l2cache.overall_avg_miss_latency::total 82910.962566
671system.cpu.l2cache.blocked_cycles::no_mshrs 0
672system.cpu.l2cache.blocked_cycles::no_targets 0
673system.cpu.l2cache.blocked::no_mshrs 0
674system.cpu.l2cache.blocked::no_targets 0
675system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
676system.cpu.l2cache.avg_blocked_cycles::no_targets nan
677system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 226
678system.cpu.l2cache.ReadExReq_mshr_misses::total 226
679system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1333
680system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1333
681system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 311
682system.cpu.l2cache.ReadSharedReq_mshr_misses::total 311
683system.cpu.l2cache.demand_mshr_misses::cpu.inst 1333
684system.cpu.l2cache.demand_mshr_misses::cpu.data 537
685system.cpu.l2cache.demand_mshr_misses::total 1870
686system.cpu.l2cache.overall_mshr_misses::cpu.inst 1333
687system.cpu.l2cache.overall_mshr_misses::cpu.data 537
688system.cpu.l2cache.overall_mshr_misses::total 1870
689system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16248000
690system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16248000
691system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 96780500
692system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 96780500
693system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 23325000
694system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 23325000
695system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 96780500
696system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 39573000
697system.cpu.l2cache.demand_mshr_miss_latency::total 136353500
698system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 96780500
699system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 39573000
700system.cpu.l2cache.overall_mshr_miss_latency::total 136353500
701system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
702system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
703system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.994776
704system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.994776
705system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.996794
706system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.996794
707system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994776
708system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.998141
709system.cpu.l2cache.demand_mshr_miss_rate::total 0.995740
710system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994776
711system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.998141
712system.cpu.l2cache.overall_mshr_miss_rate::total 0.995740
713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71893.805309
714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71893.805309
715system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72603.525881
716system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72603.525881
717system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75000
718system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75000
719system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72603.525881
720system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73692.737430
721system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72916.310160
722system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72603.525881
723system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73692.737430
724system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72916.310160
725system.cpu.toL2Bus.snoop_filter.tot_requests 1998
726system.cpu.toL2Bus.snoop_filter.hit_single_requests 121
727system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
728system.cpu.toL2Bus.snoop_filter.tot_snoops 0
729system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
730system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
731system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 414261500
732system.cpu.toL2Bus.trans_dist::ReadResp 1651
733system.cpu.toL2Bus.trans_dist::WritebackDirty 2
734system.cpu.toL2Bus.trans_dist::WritebackClean 118
735system.cpu.toL2Bus.trans_dist::ReadExReq 226
736system.cpu.toL2Bus.trans_dist::ReadExResp 226
737system.cpu.toL2Bus.trans_dist::ReadCleanReq 1340
738system.cpu.toL2Bus.trans_dist::ReadSharedReq 312
739system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2797
740system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1078
741system.cpu.toL2Bus.pkt_count::total 3875
742system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93248
743system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 34560
744system.cpu.toL2Bus.pkt_size::total 127808
745system.cpu.toL2Bus.snoops 0
746system.cpu.toL2Bus.snoopTraffic 0
747system.cpu.toL2Bus.snoop_fanout::samples 1878
748system.cpu.toL2Bus.snoop_fanout::mean 0.000532
749system.cpu.toL2Bus.snoop_fanout::stdev 0.023075
750system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
751system.cpu.toL2Bus.snoop_fanout::0 1877 99.94% 99.94%
752system.cpu.toL2Bus.snoop_fanout::1 1 0.05% 99.99%
753system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 99.99%
754system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 99.99%
755system.cpu.toL2Bus.snoop_fanout::min_value 0
756system.cpu.toL2Bus.snoop_fanout::max_value 1
757system.cpu.toL2Bus.snoop_fanout::total 1878
758system.cpu.toL2Bus.reqLayer0.occupancy 1119000
759system.cpu.toL2Bus.reqLayer0.utilization 0.2
760system.cpu.toL2Bus.respLayer0.occupancy 2008500
761system.cpu.toL2Bus.respLayer0.utilization 0.4
762system.cpu.toL2Bus.respLayer1.occupancy 807000
763system.cpu.toL2Bus.respLayer1.utilization 0.1
764system.membus.snoop_filter.tot_requests 1869
765system.membus.snoop_filter.hit_single_requests 0
766system.membus.snoop_filter.hit_multi_requests 0
767system.membus.snoop_filter.tot_snoops 0
768system.membus.snoop_filter.hit_single_snoops 0
769system.membus.snoop_filter.hit_multi_snoops 0
770system.membus.pwrStateResidencyTicks::UNDEFINED 414261500
771system.membus.trans_dist::ReadResp 1643
772system.membus.trans_dist::ReadExReq 226
773system.membus.trans_dist::ReadExResp 226
774system.membus.trans_dist::ReadSharedReq 1643
775system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3738
776system.membus.pkt_count::total 3738
777system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 119616
778system.membus.pkt_size::total 119616
779system.membus.snoops 0
780system.membus.snoopTraffic 0
781system.membus.snoop_fanout::samples 1869
782system.membus.snoop_fanout::mean 0
783system.membus.snoop_fanout::stdev -0
784system.membus.snoop_fanout::underflows 0 0.00% 0.00%
785system.membus.snoop_fanout::0 1869 100.00% 100.00%
786system.membus.snoop_fanout::1 0 0.00% 100.00%
787system.membus.snoop_fanout::overflows 0 0.00% 100.00%
788system.membus.snoop_fanout::min_value 0
789system.membus.snoop_fanout::max_value 0
790system.membus.snoop_fanout::total 1869
791system.membus.reqLayer0.occupancy 2188500
792system.membus.reqLayer0.utilization 0.5
793system.membus.respLayer1.occupancy 9936000
794system.membus.respLayer1.utilization 2.3
|