| stats.txt (11731:c473ca7cc650) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000270 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000270 # Number of seconds simulated |
| 4sim_ticks 270200000 # Number of ticks simulated 5final_tick 270200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 269998000 # Number of ticks simulated 5final_tick 269998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 24805 # Simulator instruction rate (inst/s) 8host_op_rate 24804 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 29619482 # Simulator tick rate (ticks/s) 10host_mem_usage 244928 # Number of bytes of host memory used 11host_seconds 9.12 # Real time elapsed on the host | 7host_inst_rate 216821 # Simulator instruction rate (inst/s) 8host_op_rate 216819 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 258712153 # Simulator tick rate (ticks/s) 10host_mem_usage 263004 # Number of bytes of host memory used 11host_seconds 1.04 # Real time elapsed on the host |
| 12sim_insts 226275 # Number of instructions simulated 13sim_ops 226275 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 226275 # Number of instructions simulated 13sim_ops 226275 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory 19system.physmem.bytes_read::total 86336 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 67072 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 67072 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 67072 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 19264 # Number of bytes read from this memory 19system.physmem.bytes_read::total 86336 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 67072 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 67072 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 1048 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 301 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 1349 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 248230940 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 71295337 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 319526277 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 248230940 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 248230940 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 248230940 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 71295337 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 319526277 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 248416655 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 71348677 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 319765332 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 248416655 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 248416655 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 248416655 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 71348677 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 319765332 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 1349 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 86336 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 86336 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 1349 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 1349 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 86336 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 86336 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 269959000 # Total gap between requests | 79system.physmem.totGap 269757000 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 1349 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 96 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 1349 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 96 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 239 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 351.330544 # Bytes accessed per row activation |
| 192system.physmem.bytesPerActivate::gmean 238.583723 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 292.748127 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 53 22.18% 22.18% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 57 23.85% 46.03% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 30 12.55% 58.58% # Bytes accessed per row activation | 192system.physmem.bytesPerActivate::gmean 237.806193 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 293.628623 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 54 22.59% 22.59% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 57 23.85% 46.44% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 29 12.13% 58.58% # Bytes accessed per row activation |
| 197system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation | 197system.physmem.bytesPerActivate::384-511 35 14.64% 73.22% # Bytes accessed per row activation |
| 198system.physmem.bytesPerActivate::512-639 21 8.79% 82.01% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 16 6.69% 88.70% # Bytes accessed per row activation | 198system.physmem.bytesPerActivate::512-639 20 8.37% 81.59% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 17 7.11% 88.70% # Bytes accessed per row activation |
| 200system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation | 200system.physmem.bytesPerActivate::768-895 4 1.67% 90.38% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 1.26% 91.63% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 20 8.37% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 239 # Bytes accessed per row activation |
| 204system.physmem.totQLat 15283750 # Total ticks spent queuing 205system.physmem.totMemAccLat 40577500 # Total ticks spent from burst creation until serviced by the DRAM | 204system.physmem.totQLat 15217250 # Total ticks spent queuing 205system.physmem.totMemAccLat 40511000 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 6745000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 11329.69 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 11280.39 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 30079.69 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 319.53 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 30030.39 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 319.77 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 319.53 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 319.77 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 2.50 # Data bus utilization in percentage 216system.physmem.busUtilRead 2.50 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 1101 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 2.50 # Data bus utilization in percentage 216system.physmem.busUtilRead 2.50 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 1101 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 81.62 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 200117.87 # Average gap between requests | 224system.physmem.avgGap 199968.12 # Average gap between requests |
| 225system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) | 225system.physmem.pageHitRate 81.62 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 462990 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 5454960 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 20897760.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 13396710 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 455520 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 92913420 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 13776960 # Energy for precharge power-down per rank (pJ) | 231system.physmem_0.actBackEnergy 13384170 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 450240 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 94080210 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 12732960 # Energy for precharge power-down per rank (pJ) |
| 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 236system.physmem_0.totalEnergy 148257960 # Total energy per rank (pJ) 237system.physmem_0.averagePower 548.697113 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 238953500 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 216000 # Time in different power states | 236system.physmem_0.totalEnergy 148362930 # Total energy per rank (pJ) 237system.physmem_0.averagePower 549.494877 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 238782750 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states |
| 240system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states | 240system.physmem_0.memoryStateTime::REF 8840000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states |
| 242system.physmem_0.memoryStateTime::PRE_PDN 35871500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 21502750 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 203769750 # Time in different power states | 242system.physmem_0.memoryStateTime::PRE_PDN 33151500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 21477500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 206319000 # Time in different power states |
| 245system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ) | 245system.physmem_1.actEnergy 871080 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 444015 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 4176900 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 21512400.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 11664480 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 3533280 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 82867740 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 20352000 # Energy for precharge power-down per rank (pJ) | 250system.physmem_1.actBackEnergy 11660490 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 3532800 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 84455190 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 18941760 # Energy for precharge power-down per rank (pJ) |
| 254system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ) | 254system.physmem_1.selfRefreshEnergy 718140.000000 # Energy for self refresh per rank (pJ) |
| 255system.physmem_1.totalEnergy 146140035 # Total energy per rank (pJ) 256system.physmem_1.averagePower 540.858753 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 235236750 # Total Idle time Per DRAM Rank | 255system.physmem_1.totalEnergy 146312775 # Total energy per rank (pJ) 256system.physmem_1.averagePower 541.901675 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 235034750 # Total Idle time Per DRAM Rank |
| 258system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states 259system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states | 258system.physmem_1.memoryStateTime::IDLE 8236250 # Time in different power states 259system.physmem_1.memoryStateTime::REF 9106000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 690750 # Time in different power states |
| 261system.physmem_1.memoryStateTime::PRE_PDN 53009000 # Time in different power states | 261system.physmem_1.memoryStateTime::PRE_PDN 49337750 # Time in different power states |
| 262system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states | 262system.physmem_1.memoryStateTime::ACT 17416750 # Time in different power states |
| 263system.physmem_1.memoryStateTime::ACT_PDN 181741250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 61485 # Number of BP lookups 266system.cpu.branchPred.condPredicted 39320 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 4384 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 51667 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 29457 # Number of BTB hits | 263system.physmem_1.memoryStateTime::ACT_PDN 185210500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 61459 # Number of BP lookups 266system.cpu.branchPred.condPredicted 39303 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 4350 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 48024 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 29463 # Number of BTB hits |
| 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 271system.cpu.branchPred.BTBHitPct 57.013181 # BTB Hit Percentage | 271system.cpu.branchPred.BTBHitPct 61.350575 # BTB Hit Percentage |
| 272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. | 272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 274system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 6105 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 4159 # Number of indirect misses. | 274system.cpu.branchPred.indirectLookups 10253 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 6091 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 4162 # Number of indirect misses. |
| 277system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.write_accesses 0 # DTB write accesses --- 5 unchanged lines hidden (view full) --- 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 115 # Number of system calls | 277system.cpu.branchPredindirectMispredicted 2365 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.write_accesses 0 # DTB write accesses --- 5 unchanged lines hidden (view full) --- 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 115 # Number of system calls |
| 298system.cpu.pwrStateResidencyTicks::ON 270200000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 540400 # number of cpu cycles simulated | 298system.cpu.pwrStateResidencyTicks::ON 269998000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 539996 # number of cpu cycles simulated |
| 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.committedInsts 226275 # Number of instructions committed 303system.cpu.committedOps 226275 # Number of ops (including micro ops) committed | 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.committedInsts 226275 # Number of instructions committed 303system.cpu.committedOps 226275 # Number of ops (including micro ops) committed |
| 304system.cpu.discardedOps 10623 # Number of ops (including micro ops) which were discarded before commit | 304system.cpu.discardedOps 10605 # Number of ops (including micro ops) which were discarded before commit |
| 305system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 305system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 306system.cpu.cpi 2.388244 # CPI: cycles per instruction 307system.cpu.ipc 0.418718 # IPC: instructions per cycle | 306system.cpu.cpi 2.386459 # CPI: cycles per instruction 307system.cpu.ipc 0.419031 # IPC: instructions per cycle |
| 308system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction 309system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction 310system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction 311system.cpu.op_class_0::IntDiv 40 0.02% 60.56% # Class of committed instruction 312system.cpu.op_class_0::FloatAdd 104 0.05% 60.60% # Class of committed instruction 313system.cpu.op_class_0::FloatCmp 119 0.05% 60.65% # Class of committed instruction 314system.cpu.op_class_0::FloatCvt 43 0.02% 60.67% # Class of committed instruction 315system.cpu.op_class_0::FloatMult 30 0.01% 60.69% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.69% # Class of committed instruction 340system.cpu.op_class_0::MemRead 51297 22.67% 83.36% # Class of committed instruction 341system.cpu.op_class_0::MemWrite 37094 16.39% 99.76% # Class of committed instruction 342system.cpu.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction 343system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 226275 # Class of committed instruction | 308system.cpu.op_class_0::No_OpClass 117 0.05% 0.05% # Class of committed instruction 309system.cpu.op_class_0::IntAlu 136540 60.34% 60.39% # Class of committed instruction 310system.cpu.op_class_0::IntMult 325 0.14% 60.54% # Class of committed instruction 311system.cpu.op_class_0::IntDiv 40 0.02% 60.56% # Class of committed instruction 312system.cpu.op_class_0::FloatAdd 104 0.05% 60.60% # Class of committed instruction 313system.cpu.op_class_0::FloatCmp 119 0.05% 60.65% # Class of committed instruction 314system.cpu.op_class_0::FloatCvt 43 0.02% 60.67% # Class of committed instruction 315system.cpu.op_class_0::FloatMult 30 0.01% 60.69% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.69% # Class of committed instruction 340system.cpu.op_class_0::MemRead 51297 22.67% 83.36% # Class of committed instruction 341system.cpu.op_class_0::MemWrite 37094 16.39% 99.76% # Class of committed instruction 342system.cpu.op_class_0::FloatMemRead 414 0.18% 99.94% # Class of committed instruction 343system.cpu.op_class_0::FloatMemWrite 136 0.06% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 226275 # Class of committed instruction |
| 347system.cpu.tickCycles 340080 # Number of cycles that the object actually ticked 348system.cpu.idleCycles 200320 # Total number of cycles that the object has spent stopped 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states | 347system.cpu.tickCycles 339832 # Number of cycles that the object actually ticked 348system.cpu.idleCycles 200164 # Total number of cycles that the object has spent stopped 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states |
| 350system.cpu.dcache.tags.replacements 0 # number of replacements | 350system.cpu.dcache.tags.replacements 0 # number of replacements |
| 351system.cpu.dcache.tags.tagsinuse 242.026814 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 90015 # Total number of references to valid blocks. | 351system.cpu.dcache.tags.tagsinuse 242.012615 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 90016 # Total number of references to valid blocks. |
| 353system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks. | 353system.cpu.dcache.tags.sampled_refs 302 # Sample count of references to valid blocks. |
| 354system.cpu.dcache.tags.avg_refs 298.062914 # Average number of references to valid blocks. | 354system.cpu.dcache.tags.avg_refs 298.066225 # Average number of references to valid blocks. |
| 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 356system.cpu.dcache.tags.occ_blocks::cpu.data 242.026814 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.059089 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.059089 # Average percentage of cache occupancy | 356system.cpu.dcache.tags.occ_blocks::cpu.data 242.012615 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.059085 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.059085 # Average percentage of cache occupancy |
| 359system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 362system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id 363system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id | 359system.cpu.dcache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id 362system.cpu.dcache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id 363system.cpu.dcache.tags.occ_task_id_percent::1024 0.073730 # Percentage of cache occupancy per task id |
| 364system.cpu.dcache.tags.tag_accesses 181330 # Number of tag accesses 365system.cpu.dcache.tags.data_accesses 181330 # Number of data accesses 366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states 367system.cpu.dcache.ReadReq_hits::cpu.data 53182 # number of ReadReq hits 368system.cpu.dcache.ReadReq_hits::total 53182 # number of ReadReq hits | 364system.cpu.dcache.tags.tag_accesses 181332 # Number of tag accesses 365system.cpu.dcache.tags.data_accesses 181332 # Number of data accesses 366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states 367system.cpu.dcache.ReadReq_hits::cpu.data 53183 # number of ReadReq hits 368system.cpu.dcache.ReadReq_hits::total 53183 # number of ReadReq hits |
| 369system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits 370system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits | 369system.cpu.dcache.WriteReq_hits::cpu.data 36833 # number of WriteReq hits 370system.cpu.dcache.WriteReq_hits::total 36833 # number of WriteReq hits |
| 371system.cpu.dcache.demand_hits::cpu.data 90015 # number of demand (read+write) hits 372system.cpu.dcache.demand_hits::total 90015 # number of demand (read+write) hits 373system.cpu.dcache.overall_hits::cpu.data 90015 # number of overall hits 374system.cpu.dcache.overall_hits::total 90015 # number of overall hits | 371system.cpu.dcache.demand_hits::cpu.data 90016 # number of demand (read+write) hits 372system.cpu.dcache.demand_hits::total 90016 # number of demand (read+write) hits 373system.cpu.dcache.overall_hits::cpu.data 90016 # number of overall hits 374system.cpu.dcache.overall_hits::total 90016 # number of overall hits |
| 375system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses 376system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses 377system.cpu.dcache.WriteReq_misses::cpu.data 396 # number of WriteReq misses 378system.cpu.dcache.WriteReq_misses::total 396 # number of WriteReq misses 379system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses 380system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses 381system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses 382system.cpu.dcache.overall_misses::total 499 # number of overall misses | 375system.cpu.dcache.ReadReq_misses::cpu.data 103 # number of ReadReq misses 376system.cpu.dcache.ReadReq_misses::total 103 # number of ReadReq misses 377system.cpu.dcache.WriteReq_misses::cpu.data 396 # number of WriteReq misses 378system.cpu.dcache.WriteReq_misses::total 396 # number of WriteReq misses 379system.cpu.dcache.demand_misses::cpu.data 499 # number of demand (read+write) misses 380system.cpu.dcache.demand_misses::total 499 # number of demand (read+write) misses 381system.cpu.dcache.overall_misses::cpu.data 499 # number of overall misses 382system.cpu.dcache.overall_misses::total 499 # number of overall misses |
| 383system.cpu.dcache.ReadReq_miss_latency::cpu.data 9494000 # number of ReadReq miss cycles 384system.cpu.dcache.ReadReq_miss_latency::total 9494000 # number of ReadReq miss cycles | 383system.cpu.dcache.ReadReq_miss_latency::cpu.data 9627000 # number of ReadReq miss cycles 384system.cpu.dcache.ReadReq_miss_latency::total 9627000 # number of ReadReq miss cycles |
| 385system.cpu.dcache.WriteReq_miss_latency::cpu.data 31678500 # number of WriteReq miss cycles 386system.cpu.dcache.WriteReq_miss_latency::total 31678500 # number of WriteReq miss cycles | 385system.cpu.dcache.WriteReq_miss_latency::cpu.data 31678500 # number of WriteReq miss cycles 386system.cpu.dcache.WriteReq_miss_latency::total 31678500 # number of WriteReq miss cycles |
| 387system.cpu.dcache.demand_miss_latency::cpu.data 41172500 # number of demand (read+write) miss cycles 388system.cpu.dcache.demand_miss_latency::total 41172500 # number of demand (read+write) miss cycles 389system.cpu.dcache.overall_miss_latency::cpu.data 41172500 # number of overall miss cycles 390system.cpu.dcache.overall_miss_latency::total 41172500 # number of overall miss cycles 391system.cpu.dcache.ReadReq_accesses::cpu.data 53285 # number of ReadReq accesses(hits+misses) 392system.cpu.dcache.ReadReq_accesses::total 53285 # number of ReadReq accesses(hits+misses) | 387system.cpu.dcache.demand_miss_latency::cpu.data 41305500 # number of demand (read+write) miss cycles 388system.cpu.dcache.demand_miss_latency::total 41305500 # number of demand (read+write) miss cycles 389system.cpu.dcache.overall_miss_latency::cpu.data 41305500 # number of overall miss cycles 390system.cpu.dcache.overall_miss_latency::total 41305500 # number of overall miss cycles 391system.cpu.dcache.ReadReq_accesses::cpu.data 53286 # number of ReadReq accesses(hits+misses) 392system.cpu.dcache.ReadReq_accesses::total 53286 # number of ReadReq accesses(hits+misses) |
| 393system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) 394system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) | 393system.cpu.dcache.WriteReq_accesses::cpu.data 37229 # number of WriteReq accesses(hits+misses) 394system.cpu.dcache.WriteReq_accesses::total 37229 # number of WriteReq accesses(hits+misses) |
| 395system.cpu.dcache.demand_accesses::cpu.data 90514 # number of demand (read+write) accesses 396system.cpu.dcache.demand_accesses::total 90514 # number of demand (read+write) accesses 397system.cpu.dcache.overall_accesses::cpu.data 90514 # number of overall (read+write) accesses 398system.cpu.dcache.overall_accesses::total 90514 # number of overall (read+write) accesses | 395system.cpu.dcache.demand_accesses::cpu.data 90515 # number of demand (read+write) accesses 396system.cpu.dcache.demand_accesses::total 90515 # number of demand (read+write) accesses 397system.cpu.dcache.overall_accesses::cpu.data 90515 # number of overall (read+write) accesses 398system.cpu.dcache.overall_accesses::total 90515 # number of overall (read+write) accesses |
| 399system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001933 # miss rate for ReadReq accesses 400system.cpu.dcache.ReadReq_miss_rate::total 0.001933 # miss rate for ReadReq accesses 401system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010637 # miss rate for WriteReq accesses 402system.cpu.dcache.WriteReq_miss_rate::total 0.010637 # miss rate for WriteReq accesses 403system.cpu.dcache.demand_miss_rate::cpu.data 0.005513 # miss rate for demand accesses 404system.cpu.dcache.demand_miss_rate::total 0.005513 # miss rate for demand accesses 405system.cpu.dcache.overall_miss_rate::cpu.data 0.005513 # miss rate for overall accesses 406system.cpu.dcache.overall_miss_rate::total 0.005513 # miss rate for overall accesses | 399system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001933 # miss rate for ReadReq accesses 400system.cpu.dcache.ReadReq_miss_rate::total 0.001933 # miss rate for ReadReq accesses 401system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010637 # miss rate for WriteReq accesses 402system.cpu.dcache.WriteReq_miss_rate::total 0.010637 # miss rate for WriteReq accesses 403system.cpu.dcache.demand_miss_rate::cpu.data 0.005513 # miss rate for demand accesses 404system.cpu.dcache.demand_miss_rate::total 0.005513 # miss rate for demand accesses 405system.cpu.dcache.overall_miss_rate::cpu.data 0.005513 # miss rate for overall accesses 406system.cpu.dcache.overall_miss_rate::total 0.005513 # miss rate for overall accesses |
| 407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92174.757282 # average ReadReq miss latency 408system.cpu.dcache.ReadReq_avg_miss_latency::total 92174.757282 # average ReadReq miss latency | 407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93466.019417 # average ReadReq miss latency 408system.cpu.dcache.ReadReq_avg_miss_latency::total 93466.019417 # average ReadReq miss latency |
| 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79996.212121 # average WriteReq miss latency 410system.cpu.dcache.WriteReq_avg_miss_latency::total 79996.212121 # average WriteReq miss latency | 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79996.212121 # average WriteReq miss latency 410system.cpu.dcache.WriteReq_avg_miss_latency::total 79996.212121 # average WriteReq miss latency |
| 411system.cpu.dcache.demand_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency 412system.cpu.dcache.demand_avg_miss_latency::total 82510.020040 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency 414system.cpu.dcache.overall_avg_miss_latency::total 82510.020040 # average overall miss latency | 411system.cpu.dcache.demand_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency 412system.cpu.dcache.demand_avg_miss_latency::total 82776.553106 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency 414system.cpu.dcache.overall_avg_miss_latency::total 82776.553106 # average overall miss latency |
| 415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 422system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits --- 6 unchanged lines hidden (view full) --- 429system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses 430system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses 431system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses 432system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses 433system.cpu.dcache.demand_mshr_misses::cpu.data 302 # number of demand (read+write) MSHR misses 434system.cpu.dcache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses 435system.cpu.dcache.overall_mshr_misses::cpu.data 302 # number of overall MSHR misses 436system.cpu.dcache.overall_mshr_misses::total 302 # number of overall MSHR misses | 415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 422system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits --- 6 unchanged lines hidden (view full) --- 429system.cpu.dcache.ReadReq_mshr_misses::cpu.data 97 # number of ReadReq MSHR misses 430system.cpu.dcache.ReadReq_mshr_misses::total 97 # number of ReadReq MSHR misses 431system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses 432system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses 433system.cpu.dcache.demand_mshr_misses::cpu.data 302 # number of demand (read+write) MSHR misses 434system.cpu.dcache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses 435system.cpu.dcache.overall_mshr_misses::cpu.data 302 # number of overall MSHR misses 436system.cpu.dcache.overall_mshr_misses::total 302 # number of overall MSHR misses |
| 437system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8881000 # number of ReadReq MSHR miss cycles 438system.cpu.dcache.ReadReq_mshr_miss_latency::total 8881000 # number of ReadReq MSHR miss cycles | 437system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9014000 # number of ReadReq MSHR miss cycles 438system.cpu.dcache.ReadReq_mshr_miss_latency::total 9014000 # number of ReadReq MSHR miss cycles |
| 439system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16356000 # number of WriteReq MSHR miss cycles 440system.cpu.dcache.WriteReq_mshr_miss_latency::total 16356000 # number of WriteReq MSHR miss cycles | 439system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16356000 # number of WriteReq MSHR miss cycles 440system.cpu.dcache.WriteReq_mshr_miss_latency::total 16356000 # number of WriteReq MSHR miss cycles |
| 441system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25237000 # number of demand (read+write) MSHR miss cycles 442system.cpu.dcache.demand_mshr_miss_latency::total 25237000 # number of demand (read+write) MSHR miss cycles 443system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25237000 # number of overall MSHR miss cycles 444system.cpu.dcache.overall_mshr_miss_latency::total 25237000 # number of overall MSHR miss cycles | 441system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25370000 # number of demand (read+write) MSHR miss cycles 442system.cpu.dcache.demand_mshr_miss_latency::total 25370000 # number of demand (read+write) MSHR miss cycles 443system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25370000 # number of overall MSHR miss cycles 444system.cpu.dcache.overall_mshr_miss_latency::total 25370000 # number of overall MSHR miss cycles |
| 445system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001820 # mshr miss rate for ReadReq accesses 446system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001820 # mshr miss rate for ReadReq accesses 447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005506 # mshr miss rate for WriteReq accesses 448system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005506 # mshr miss rate for WriteReq accesses | 445system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001820 # mshr miss rate for ReadReq accesses 446system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001820 # mshr miss rate for ReadReq accesses 447system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005506 # mshr miss rate for WriteReq accesses 448system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005506 # mshr miss rate for WriteReq accesses |
| 449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for demand accesses 450system.cpu.dcache.demand_mshr_miss_rate::total 0.003337 # mshr miss rate for demand accesses 451system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for overall accesses 452system.cpu.dcache.overall_mshr_miss_rate::total 0.003337 # mshr miss rate for overall accesses 453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91556.701031 # average ReadReq mshr miss latency 454system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91556.701031 # average ReadReq mshr miss latency | 449system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for demand accesses 450system.cpu.dcache.demand_mshr_miss_rate::total 0.003336 # mshr miss rate for demand accesses 451system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for overall accesses 452system.cpu.dcache.overall_mshr_miss_rate::total 0.003336 # mshr miss rate for overall accesses 453system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92927.835052 # average ReadReq mshr miss latency 454system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92927.835052 # average ReadReq mshr miss latency |
| 455system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79785.365854 # average WriteReq mshr miss latency 456system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79785.365854 # average WriteReq mshr miss latency | 455system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79785.365854 # average WriteReq mshr miss latency 456system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79785.365854 # average WriteReq mshr miss latency |
| 457system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency 458system.cpu.dcache.demand_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency 459system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency 460system.cpu.dcache.overall_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency 461system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states | 457system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency 458system.cpu.dcache.demand_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency 459system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency 460system.cpu.dcache.overall_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency 461system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states |
| 462system.cpu.icache.tags.replacements 69 # number of replacements | 462system.cpu.icache.tags.replacements 69 # number of replacements |
| 463system.cpu.icache.tags.tagsinuse 555.532163 # Cycle average of tags in use 464system.cpu.icache.tags.total_refs 101722 # Total number of references to valid blocks. | 463system.cpu.icache.tags.tagsinuse 555.459146 # Cycle average of tags in use 464system.cpu.icache.tags.total_refs 101640 # Total number of references to valid blocks. |
| 465system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks. | 465system.cpu.icache.tags.sampled_refs 1051 # Sample count of references to valid blocks. |
| 466system.cpu.icache.tags.avg_refs 96.785918 # Average number of references to valid blocks. | 466system.cpu.icache.tags.avg_refs 96.707897 # Average number of references to valid blocks. |
| 467system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 467system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 468system.cpu.icache.tags.occ_blocks::cpu.inst 555.532163 # Average occupied blocks per requestor 469system.cpu.icache.tags.occ_percent::cpu.inst 0.271256 # Average percentage of cache occupancy 470system.cpu.icache.tags.occ_percent::total 0.271256 # Average percentage of cache occupancy | 468system.cpu.icache.tags.occ_blocks::cpu.inst 555.459146 # Average occupied blocks per requestor 469system.cpu.icache.tags.occ_percent::cpu.inst 0.271220 # Average percentage of cache occupancy 470system.cpu.icache.tags.occ_percent::total 0.271220 # Average percentage of cache occupancy |
| 471system.cpu.icache.tags.occ_task_id_blocks::1024 982 # Occupied blocks per task id 472system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id 473system.cpu.icache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id 474system.cpu.icache.tags.age_task_id_blocks_1024::2 724 # Occupied blocks per task id 475system.cpu.icache.tags.occ_task_id_percent::1024 0.479492 # Percentage of cache occupancy per task id | 471system.cpu.icache.tags.occ_task_id_blocks::1024 982 # Occupied blocks per task id 472system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id 473system.cpu.icache.tags.age_task_id_blocks_1024::1 189 # Occupied blocks per task id 474system.cpu.icache.tags.age_task_id_blocks_1024::2 724 # Occupied blocks per task id 475system.cpu.icache.tags.occ_task_id_percent::1024 0.479492 # Percentage of cache occupancy per task id |
| 476system.cpu.icache.tags.tag_accesses 206597 # Number of tag accesses 477system.cpu.icache.tags.data_accesses 206597 # Number of data accesses 478system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states 479system.cpu.icache.ReadReq_hits::cpu.inst 101722 # number of ReadReq hits 480system.cpu.icache.ReadReq_hits::total 101722 # number of ReadReq hits 481system.cpu.icache.demand_hits::cpu.inst 101722 # number of demand (read+write) hits 482system.cpu.icache.demand_hits::total 101722 # number of demand (read+write) hits 483system.cpu.icache.overall_hits::cpu.inst 101722 # number of overall hits 484system.cpu.icache.overall_hits::total 101722 # number of overall hits | 476system.cpu.icache.tags.tag_accesses 206433 # Number of tag accesses 477system.cpu.icache.tags.data_accesses 206433 # Number of data accesses 478system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states 479system.cpu.icache.ReadReq_hits::cpu.inst 101640 # number of ReadReq hits 480system.cpu.icache.ReadReq_hits::total 101640 # number of ReadReq hits 481system.cpu.icache.demand_hits::cpu.inst 101640 # number of demand (read+write) hits 482system.cpu.icache.demand_hits::total 101640 # number of demand (read+write) hits 483system.cpu.icache.overall_hits::cpu.inst 101640 # number of overall hits 484system.cpu.icache.overall_hits::total 101640 # number of overall hits |
| 485system.cpu.icache.ReadReq_misses::cpu.inst 1051 # number of ReadReq misses 486system.cpu.icache.ReadReq_misses::total 1051 # number of ReadReq misses 487system.cpu.icache.demand_misses::cpu.inst 1051 # number of demand (read+write) misses 488system.cpu.icache.demand_misses::total 1051 # number of demand (read+write) misses 489system.cpu.icache.overall_misses::cpu.inst 1051 # number of overall misses 490system.cpu.icache.overall_misses::total 1051 # number of overall misses | 485system.cpu.icache.ReadReq_misses::cpu.inst 1051 # number of ReadReq misses 486system.cpu.icache.ReadReq_misses::total 1051 # number of ReadReq misses 487system.cpu.icache.demand_misses::cpu.inst 1051 # number of demand (read+write) misses 488system.cpu.icache.demand_misses::total 1051 # number of demand (read+write) misses 489system.cpu.icache.overall_misses::cpu.inst 1051 # number of overall misses 490system.cpu.icache.overall_misses::total 1051 # number of overall misses |
| 491system.cpu.icache.ReadReq_miss_latency::cpu.inst 87209500 # number of ReadReq miss cycles 492system.cpu.icache.ReadReq_miss_latency::total 87209500 # number of ReadReq miss cycles 493system.cpu.icache.demand_miss_latency::cpu.inst 87209500 # number of demand (read+write) miss cycles 494system.cpu.icache.demand_miss_latency::total 87209500 # number of demand (read+write) miss cycles 495system.cpu.icache.overall_miss_latency::cpu.inst 87209500 # number of overall miss cycles 496system.cpu.icache.overall_miss_latency::total 87209500 # number of overall miss cycles 497system.cpu.icache.ReadReq_accesses::cpu.inst 102773 # number of ReadReq accesses(hits+misses) 498system.cpu.icache.ReadReq_accesses::total 102773 # number of ReadReq accesses(hits+misses) 499system.cpu.icache.demand_accesses::cpu.inst 102773 # number of demand (read+write) accesses 500system.cpu.icache.demand_accesses::total 102773 # number of demand (read+write) accesses 501system.cpu.icache.overall_accesses::cpu.inst 102773 # number of overall (read+write) accesses 502system.cpu.icache.overall_accesses::total 102773 # number of overall (read+write) accesses 503system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010226 # miss rate for ReadReq accesses 504system.cpu.icache.ReadReq_miss_rate::total 0.010226 # miss rate for ReadReq accesses 505system.cpu.icache.demand_miss_rate::cpu.inst 0.010226 # miss rate for demand accesses 506system.cpu.icache.demand_miss_rate::total 0.010226 # miss rate for demand accesses 507system.cpu.icache.overall_miss_rate::cpu.inst 0.010226 # miss rate for overall accesses 508system.cpu.icache.overall_miss_rate::total 0.010226 # miss rate for overall accesses 509system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82977.640343 # average ReadReq miss latency 510system.cpu.icache.ReadReq_avg_miss_latency::total 82977.640343 # average ReadReq miss latency 511system.cpu.icache.demand_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency 512system.cpu.icache.demand_avg_miss_latency::total 82977.640343 # average overall miss latency 513system.cpu.icache.overall_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency 514system.cpu.icache.overall_avg_miss_latency::total 82977.640343 # average overall miss latency | 491system.cpu.icache.ReadReq_miss_latency::cpu.inst 87010500 # number of ReadReq miss cycles 492system.cpu.icache.ReadReq_miss_latency::total 87010500 # number of ReadReq miss cycles 493system.cpu.icache.demand_miss_latency::cpu.inst 87010500 # number of demand (read+write) miss cycles 494system.cpu.icache.demand_miss_latency::total 87010500 # number of demand (read+write) miss cycles 495system.cpu.icache.overall_miss_latency::cpu.inst 87010500 # number of overall miss cycles 496system.cpu.icache.overall_miss_latency::total 87010500 # number of overall miss cycles 497system.cpu.icache.ReadReq_accesses::cpu.inst 102691 # number of ReadReq accesses(hits+misses) 498system.cpu.icache.ReadReq_accesses::total 102691 # number of ReadReq accesses(hits+misses) 499system.cpu.icache.demand_accesses::cpu.inst 102691 # number of demand (read+write) accesses 500system.cpu.icache.demand_accesses::total 102691 # number of demand (read+write) accesses 501system.cpu.icache.overall_accesses::cpu.inst 102691 # number of overall (read+write) accesses 502system.cpu.icache.overall_accesses::total 102691 # number of overall (read+write) accesses 503system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010235 # miss rate for ReadReq accesses 504system.cpu.icache.ReadReq_miss_rate::total 0.010235 # miss rate for ReadReq accesses 505system.cpu.icache.demand_miss_rate::cpu.inst 0.010235 # miss rate for demand accesses 506system.cpu.icache.demand_miss_rate::total 0.010235 # miss rate for demand accesses 507system.cpu.icache.overall_miss_rate::cpu.inst 0.010235 # miss rate for overall accesses 508system.cpu.icache.overall_miss_rate::total 0.010235 # miss rate for overall accesses 509system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82788.296860 # average ReadReq miss latency 510system.cpu.icache.ReadReq_avg_miss_latency::total 82788.296860 # average ReadReq miss latency 511system.cpu.icache.demand_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency 512system.cpu.icache.demand_avg_miss_latency::total 82788.296860 # average overall miss latency 513system.cpu.icache.overall_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency 514system.cpu.icache.overall_avg_miss_latency::total 82788.296860 # average overall miss latency |
| 515system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 516system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 517system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 518system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 519system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 520system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 521system.cpu.icache.writebacks::writebacks 69 # number of writebacks 522system.cpu.icache.writebacks::total 69 # number of writebacks 523system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1051 # number of ReadReq MSHR misses 524system.cpu.icache.ReadReq_mshr_misses::total 1051 # number of ReadReq MSHR misses 525system.cpu.icache.demand_mshr_misses::cpu.inst 1051 # number of demand (read+write) MSHR misses 526system.cpu.icache.demand_mshr_misses::total 1051 # number of demand (read+write) MSHR misses 527system.cpu.icache.overall_mshr_misses::cpu.inst 1051 # number of overall MSHR misses 528system.cpu.icache.overall_mshr_misses::total 1051 # number of overall MSHR misses | 515system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 516system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 517system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 518system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 519system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 520system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 521system.cpu.icache.writebacks::writebacks 69 # number of writebacks 522system.cpu.icache.writebacks::total 69 # number of writebacks 523system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1051 # number of ReadReq MSHR misses 524system.cpu.icache.ReadReq_mshr_misses::total 1051 # number of ReadReq MSHR misses 525system.cpu.icache.demand_mshr_misses::cpu.inst 1051 # number of demand (read+write) MSHR misses 526system.cpu.icache.demand_mshr_misses::total 1051 # number of demand (read+write) MSHR misses 527system.cpu.icache.overall_mshr_misses::cpu.inst 1051 # number of overall MSHR misses 528system.cpu.icache.overall_mshr_misses::total 1051 # number of overall MSHR misses |
| 529system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86158500 # number of ReadReq MSHR miss cycles 530system.cpu.icache.ReadReq_mshr_miss_latency::total 86158500 # number of ReadReq MSHR miss cycles 531system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86158500 # number of demand (read+write) MSHR miss cycles 532system.cpu.icache.demand_mshr_miss_latency::total 86158500 # number of demand (read+write) MSHR miss cycles 533system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86158500 # number of overall MSHR miss cycles 534system.cpu.icache.overall_mshr_miss_latency::total 86158500 # number of overall MSHR miss cycles 535system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for ReadReq accesses 536system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010226 # mshr miss rate for ReadReq accesses 537system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for demand accesses 538system.cpu.icache.demand_mshr_miss_rate::total 0.010226 # mshr miss rate for demand accesses 539system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for overall accesses 540system.cpu.icache.overall_mshr_miss_rate::total 0.010226 # mshr miss rate for overall accesses 541system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81977.640343 # average ReadReq mshr miss latency 542system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81977.640343 # average ReadReq mshr miss latency 543system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency 544system.cpu.icache.demand_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency 545system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency 546system.cpu.icache.overall_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency 547system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states | 529system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 85959500 # number of ReadReq MSHR miss cycles 530system.cpu.icache.ReadReq_mshr_miss_latency::total 85959500 # number of ReadReq MSHR miss cycles 531system.cpu.icache.demand_mshr_miss_latency::cpu.inst 85959500 # number of demand (read+write) MSHR miss cycles 532system.cpu.icache.demand_mshr_miss_latency::total 85959500 # number of demand (read+write) MSHR miss cycles 533system.cpu.icache.overall_mshr_miss_latency::cpu.inst 85959500 # number of overall MSHR miss cycles 534system.cpu.icache.overall_mshr_miss_latency::total 85959500 # number of overall MSHR miss cycles 535system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for ReadReq accesses 536system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010235 # mshr miss rate for ReadReq accesses 537system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for demand accesses 538system.cpu.icache.demand_mshr_miss_rate::total 0.010235 # mshr miss rate for demand accesses 539system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for overall accesses 540system.cpu.icache.overall_mshr_miss_rate::total 0.010235 # mshr miss rate for overall accesses 541system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81788.296860 # average ReadReq mshr miss latency 542system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81788.296860 # average ReadReq mshr miss latency 543system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency 544system.cpu.icache.demand_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency 545system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency 546system.cpu.icache.overall_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency 547system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states |
| 548system.cpu.l2cache.tags.replacements 0 # number of replacements | 548system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 549system.cpu.l2cache.tags.tagsinuse 827.037841 # Cycle average of tags in use | 549system.cpu.l2cache.tags.tagsinuse 826.940635 # Cycle average of tags in use |
| 550system.cpu.l2cache.tags.total_refs 73 # Total number of references to valid blocks. 551system.cpu.l2cache.tags.sampled_refs 1349 # Sample count of references to valid blocks. 552system.cpu.l2cache.tags.avg_refs 0.054114 # Average number of references to valid blocks. 553system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 550system.cpu.l2cache.tags.total_refs 73 # Total number of references to valid blocks. 551system.cpu.l2cache.tags.sampled_refs 1349 # Sample count of references to valid blocks. 552system.cpu.l2cache.tags.avg_refs 0.054114 # Average number of references to valid blocks. 553system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 554system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.656330 # Average occupied blocks per requestor 555system.cpu.l2cache.tags.occ_blocks::cpu.data 241.381510 # Average occupied blocks per requestor 556system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017873 # Average percentage of cache occupancy | 554system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.573058 # Average occupied blocks per requestor 555system.cpu.l2cache.tags.occ_blocks::cpu.data 241.367577 # Average occupied blocks per requestor 556system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017870 # Average percentage of cache occupancy |
| 557system.cpu.l2cache.tags.occ_percent::cpu.data 0.007366 # Average percentage of cache occupancy | 557system.cpu.l2cache.tags.occ_percent::cpu.data 0.007366 # Average percentage of cache occupancy |
| 558system.cpu.l2cache.tags.occ_percent::total 0.025239 # Average percentage of cache occupancy | 558system.cpu.l2cache.tags.occ_percent::total 0.025236 # Average percentage of cache occupancy |
| 559system.cpu.l2cache.tags.occ_task_id_blocks::1024 1349 # Occupied blocks per task id 560system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 561system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id 562system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id 563system.cpu.l2cache.tags.occ_task_id_percent::1024 0.041168 # Percentage of cache occupancy per task id 564system.cpu.l2cache.tags.tag_accesses 12725 # Number of tag accesses 565system.cpu.l2cache.tags.data_accesses 12725 # Number of data accesses | 559system.cpu.l2cache.tags.occ_task_id_blocks::1024 1349 # Occupied blocks per task id 560system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id 561system.cpu.l2cache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id 562system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id 563system.cpu.l2cache.tags.occ_task_id_percent::1024 0.041168 # Percentage of cache occupancy per task id 564system.cpu.l2cache.tags.tag_accesses 12725 # Number of tag accesses 565system.cpu.l2cache.tags.data_accesses 12725 # Number of data accesses |
| 566system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states | 566system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states |
| 567system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits 568system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits 569system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 570system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 571system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 572system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 573system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 574system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits --- 10 unchanged lines hidden (view full) --- 585system.cpu.l2cache.demand_misses::cpu.inst 1048 # number of demand (read+write) misses 586system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses 587system.cpu.l2cache.demand_misses::total 1349 # number of demand (read+write) misses 588system.cpu.l2cache.overall_misses::cpu.inst 1048 # number of overall misses 589system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses 590system.cpu.l2cache.overall_misses::total 1349 # number of overall misses 591system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16048500 # number of ReadExReq miss cycles 592system.cpu.l2cache.ReadExReq_miss_latency::total 16048500 # number of ReadExReq miss cycles | 567system.cpu.l2cache.WritebackClean_hits::writebacks 69 # number of WritebackClean hits 568system.cpu.l2cache.WritebackClean_hits::total 69 # number of WritebackClean hits 569system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 570system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 571system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits 572system.cpu.l2cache.ReadSharedReq_hits::total 1 # number of ReadSharedReq hits 573system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 574system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits --- 10 unchanged lines hidden (view full) --- 585system.cpu.l2cache.demand_misses::cpu.inst 1048 # number of demand (read+write) misses 586system.cpu.l2cache.demand_misses::cpu.data 301 # number of demand (read+write) misses 587system.cpu.l2cache.demand_misses::total 1349 # number of demand (read+write) misses 588system.cpu.l2cache.overall_misses::cpu.inst 1048 # number of overall misses 589system.cpu.l2cache.overall_misses::cpu.data 301 # number of overall misses 590system.cpu.l2cache.overall_misses::total 1349 # number of overall misses 591system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16048500 # number of ReadExReq miss cycles 592system.cpu.l2cache.ReadExReq_miss_latency::total 16048500 # number of ReadExReq miss cycles |
| 593system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84550500 # number of ReadCleanReq miss cycles 594system.cpu.l2cache.ReadCleanReq_miss_latency::total 84550500 # number of ReadCleanReq miss cycles 595system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8723000 # number of ReadSharedReq miss cycles 596system.cpu.l2cache.ReadSharedReq_miss_latency::total 8723000 # number of ReadSharedReq miss cycles 597system.cpu.l2cache.demand_miss_latency::cpu.inst 84550500 # number of demand (read+write) miss cycles 598system.cpu.l2cache.demand_miss_latency::cpu.data 24771500 # number of demand (read+write) miss cycles 599system.cpu.l2cache.demand_miss_latency::total 109322000 # number of demand (read+write) miss cycles 600system.cpu.l2cache.overall_miss_latency::cpu.inst 84550500 # number of overall miss cycles 601system.cpu.l2cache.overall_miss_latency::cpu.data 24771500 # number of overall miss cycles 602system.cpu.l2cache.overall_miss_latency::total 109322000 # number of overall miss cycles | 593system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84351500 # number of ReadCleanReq miss cycles 594system.cpu.l2cache.ReadCleanReq_miss_latency::total 84351500 # number of ReadCleanReq miss cycles 595system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8856000 # number of ReadSharedReq miss cycles 596system.cpu.l2cache.ReadSharedReq_miss_latency::total 8856000 # number of ReadSharedReq miss cycles 597system.cpu.l2cache.demand_miss_latency::cpu.inst 84351500 # number of demand (read+write) miss cycles 598system.cpu.l2cache.demand_miss_latency::cpu.data 24904500 # number of demand (read+write) miss cycles 599system.cpu.l2cache.demand_miss_latency::total 109256000 # number of demand (read+write) miss cycles 600system.cpu.l2cache.overall_miss_latency::cpu.inst 84351500 # number of overall miss cycles 601system.cpu.l2cache.overall_miss_latency::cpu.data 24904500 # number of overall miss cycles 602system.cpu.l2cache.overall_miss_latency::total 109256000 # number of overall miss cycles |
| 603system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses) 604system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses) 605system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses) 606system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses) 607system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1051 # number of ReadCleanReq accesses(hits+misses) 608system.cpu.l2cache.ReadCleanReq_accesses::total 1051 # number of ReadCleanReq accesses(hits+misses) 609system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses) 610system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 623system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997146 # miss rate for demand accesses 624system.cpu.l2cache.demand_miss_rate::cpu.data 0.996689 # miss rate for demand accesses 625system.cpu.l2cache.demand_miss_rate::total 0.997044 # miss rate for demand accesses 626system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997146 # miss rate for overall accesses 627system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689 # miss rate for overall accesses 628system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses 629system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency 630system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency | 603system.cpu.l2cache.WritebackClean_accesses::writebacks 69 # number of WritebackClean accesses(hits+misses) 604system.cpu.l2cache.WritebackClean_accesses::total 69 # number of WritebackClean accesses(hits+misses) 605system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses) 606system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses) 607system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1051 # number of ReadCleanReq accesses(hits+misses) 608system.cpu.l2cache.ReadCleanReq_accesses::total 1051 # number of ReadCleanReq accesses(hits+misses) 609system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 97 # number of ReadSharedReq accesses(hits+misses) 610system.cpu.l2cache.ReadSharedReq_accesses::total 97 # number of ReadSharedReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 623system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997146 # miss rate for demand accesses 624system.cpu.l2cache.demand_miss_rate::cpu.data 0.996689 # miss rate for demand accesses 625system.cpu.l2cache.demand_miss_rate::total 0.997044 # miss rate for demand accesses 626system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997146 # miss rate for overall accesses 627system.cpu.l2cache.overall_miss_rate::cpu.data 0.996689 # miss rate for overall accesses 628system.cpu.l2cache.overall_miss_rate::total 0.997044 # miss rate for overall accesses 629system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78285.365854 # average ReadExReq miss latency 630system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78285.365854 # average ReadExReq miss latency |
| 631system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80677.958015 # average ReadCleanReq miss latency 632system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80677.958015 # average ReadCleanReq miss latency 633system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90864.583333 # average ReadSharedReq miss latency 634system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90864.583333 # average ReadSharedReq miss latency 635system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency 636system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency 637system.cpu.l2cache.demand_avg_miss_latency::total 81039.288362 # average overall miss latency 638system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency 639system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency 640system.cpu.l2cache.overall_avg_miss_latency::total 81039.288362 # average overall miss latency | 631system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80488.072519 # average ReadCleanReq miss latency 632system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80488.072519 # average ReadCleanReq miss latency 633system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92250 # average ReadSharedReq miss latency 634system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92250 # average ReadSharedReq miss latency 635system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency 636system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency 637system.cpu.l2cache.demand_avg_miss_latency::total 80990.363232 # average overall miss latency 638system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency 639system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency 640system.cpu.l2cache.overall_avg_miss_latency::total 80990.363232 # average overall miss latency |
| 641system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 642system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 643system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 644system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 645system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 646system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 647system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses 648system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 653system.cpu.l2cache.demand_mshr_misses::cpu.inst 1048 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses 655system.cpu.l2cache.demand_mshr_misses::total 1349 # number of demand (read+write) MSHR misses 656system.cpu.l2cache.overall_mshr_misses::cpu.inst 1048 # number of overall MSHR misses 657system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses 658system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses 659system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles 660system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles | 641system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 642system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 643system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 644system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 645system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 646system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 647system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses 648system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 653system.cpu.l2cache.demand_mshr_misses::cpu.inst 1048 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.demand_mshr_misses::cpu.data 301 # number of demand (read+write) MSHR misses 655system.cpu.l2cache.demand_mshr_misses::total 1349 # number of demand (read+write) MSHR misses 656system.cpu.l2cache.overall_mshr_misses::cpu.inst 1048 # number of overall MSHR misses 657system.cpu.l2cache.overall_mshr_misses::cpu.data 301 # number of overall MSHR misses 658system.cpu.l2cache.overall_mshr_misses::total 1349 # number of overall MSHR misses 659system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13998500 # number of ReadExReq MSHR miss cycles 660system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13998500 # number of ReadExReq MSHR miss cycles |
| 661system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74070500 # number of ReadCleanReq MSHR miss cycles 662system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74070500 # number of ReadCleanReq MSHR miss cycles 663system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7763000 # number of ReadSharedReq MSHR miss cycles 664system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7763000 # number of ReadSharedReq MSHR miss cycles 665system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74070500 # number of demand (read+write) MSHR miss cycles 666system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21761500 # number of demand (read+write) MSHR miss cycles 667system.cpu.l2cache.demand_mshr_miss_latency::total 95832000 # number of demand (read+write) MSHR miss cycles 668system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74070500 # number of overall MSHR miss cycles 669system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21761500 # number of overall MSHR miss cycles 670system.cpu.l2cache.overall_mshr_miss_latency::total 95832000 # number of overall MSHR miss cycles | 661system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73871500 # number of ReadCleanReq MSHR miss cycles 662system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73871500 # number of ReadCleanReq MSHR miss cycles 663system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7896000 # number of ReadSharedReq MSHR miss cycles 664system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7896000 # number of ReadSharedReq MSHR miss cycles 665system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73871500 # number of demand (read+write) MSHR miss cycles 666system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21894500 # number of demand (read+write) MSHR miss cycles 667system.cpu.l2cache.demand_mshr_miss_latency::total 95766000 # number of demand (read+write) MSHR miss cycles 668system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73871500 # number of overall MSHR miss cycles 669system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21894500 # number of overall MSHR miss cycles 670system.cpu.l2cache.overall_mshr_miss_latency::total 95766000 # number of overall MSHR miss cycles |
| 671system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 672system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 673system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses 674system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997146 # mshr miss rate for ReadCleanReq accesses 675system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.989691 # mshr miss rate for ReadSharedReq accesses 676system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989691 # mshr miss rate for ReadSharedReq accesses 677system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for demand accesses 678system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for demand accesses 679system.cpu.l2cache.demand_mshr_miss_rate::total 0.997044 # mshr miss rate for demand accesses 680system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for overall accesses 681system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for overall accesses 682system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses 683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency 684system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency | 671system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 672system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 673system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for ReadCleanReq accesses 674system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997146 # mshr miss rate for ReadCleanReq accesses 675system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.989691 # mshr miss rate for ReadSharedReq accesses 676system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989691 # mshr miss rate for ReadSharedReq accesses 677system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for demand accesses 678system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for demand accesses 679system.cpu.l2cache.demand_mshr_miss_rate::total 0.997044 # mshr miss rate for demand accesses 680system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997146 # mshr miss rate for overall accesses 681system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.996689 # mshr miss rate for overall accesses 682system.cpu.l2cache.overall_mshr_miss_rate::total 0.997044 # mshr miss rate for overall accesses 683system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68285.365854 # average ReadExReq mshr miss latency 684system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68285.365854 # average ReadExReq mshr miss latency |
| 685system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70677.958015 # average ReadCleanReq mshr miss latency 686system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70677.958015 # average ReadCleanReq mshr miss latency 687system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80864.583333 # average ReadSharedReq mshr miss latency 688system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80864.583333 # average ReadSharedReq mshr miss latency 689system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency 690system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency 691system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency 692system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency 693system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency | 685system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70488.072519 # average ReadCleanReq mshr miss latency 686system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70488.072519 # average ReadCleanReq mshr miss latency 687system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency 688system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82250 # average ReadSharedReq mshr miss latency 689system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency 690system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency 691system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency 692system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency 693system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency 694system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency |
| 695system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter. 696system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data. 697system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 698system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 699system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 700system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 695system.cpu.toL2Bus.snoop_filter.tot_requests 1422 # Total number of requests made to the snoop filter. 696system.cpu.toL2Bus.snoop_filter.hit_single_requests 70 # Number of requests hitting in the snoop filter with a single holder of the requested data. 697system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 698system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 699system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 700system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 701system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states | 701system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states |
| 702system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution 703system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution 704system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution 705system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution 706system.cpu.toL2Bus.trans_dist::ReadCleanReq 1051 # Transaction distribution 707system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution 708system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171 # Packet count per connected master and slave (bytes) 709system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 604 # Packet count per connected master and slave (bytes) --- 21 unchanged lines hidden (view full) --- 731system.cpu.toL2Bus.respLayer1.occupancy 453000 # Layer occupancy (ticks) 732system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 733system.membus.snoop_filter.tot_requests 1349 # Total number of requests made to the snoop filter. 734system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 735system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 736system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 737system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 738system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 702system.cpu.toL2Bus.trans_dist::ReadResp 1148 # Transaction distribution 703system.cpu.toL2Bus.trans_dist::WritebackClean 69 # Transaction distribution 704system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution 705system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution 706system.cpu.toL2Bus.trans_dist::ReadCleanReq 1051 # Transaction distribution 707system.cpu.toL2Bus.trans_dist::ReadSharedReq 97 # Transaction distribution 708system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2171 # Packet count per connected master and slave (bytes) 709system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 604 # Packet count per connected master and slave (bytes) --- 21 unchanged lines hidden (view full) --- 731system.cpu.toL2Bus.respLayer1.occupancy 453000 # Layer occupancy (ticks) 732system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 733system.membus.snoop_filter.tot_requests 1349 # Total number of requests made to the snoop filter. 734system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 735system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 736system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 737system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 738system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 739system.membus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states | 739system.membus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states |
| 740system.membus.trans_dist::ReadResp 1144 # Transaction distribution 741system.membus.trans_dist::ReadExReq 205 # Transaction distribution 742system.membus.trans_dist::ReadExResp 205 # Transaction distribution 743system.membus.trans_dist::ReadSharedReq 1144 # Transaction distribution 744system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2698 # Packet count per connected master and slave (bytes) 745system.membus.pkt_count::total 2698 # Packet count per connected master and slave (bytes) 746system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 86336 # Cumulative packet size per connected master and slave (bytes) 747system.membus.pkt_size::total 86336 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 752system.membus.snoop_fanout::stdev 0 # Request fanout histogram 753system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 754system.membus.snoop_fanout::0 1349 100.00% 100.00% # Request fanout histogram 755system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 756system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 757system.membus.snoop_fanout::min_value 0 # Request fanout histogram 758system.membus.snoop_fanout::max_value 0 # Request fanout histogram 759system.membus.snoop_fanout::total 1349 # Request fanout histogram | 740system.membus.trans_dist::ReadResp 1144 # Transaction distribution 741system.membus.trans_dist::ReadExReq 205 # Transaction distribution 742system.membus.trans_dist::ReadExResp 205 # Transaction distribution 743system.membus.trans_dist::ReadSharedReq 1144 # Transaction distribution 744system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2698 # Packet count per connected master and slave (bytes) 745system.membus.pkt_count::total 2698 # Packet count per connected master and slave (bytes) 746system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 86336 # Cumulative packet size per connected master and slave (bytes) 747system.membus.pkt_size::total 86336 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 752system.membus.snoop_fanout::stdev 0 # Request fanout histogram 753system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 754system.membus.snoop_fanout::0 1349 100.00% 100.00% # Request fanout histogram 755system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 756system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 757system.membus.snoop_fanout::min_value 0 # Request fanout histogram 758system.membus.snoop_fanout::max_value 0 # Request fanout histogram 759system.membus.snoop_fanout::total 1349 # Request fanout histogram |
| 760system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks) | 760system.membus.reqLayer0.occupancy 1553000 # Layer occupancy (ticks) |
| 761system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) | 761system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 762system.membus.respLayer1.occupancy 7151000 # Layer occupancy (ticks) | 762system.membus.respLayer1.occupancy 7152500 # Layer occupancy (ticks) |
| 763system.membus.respLayer1.utilization 2.6 # Layer utilization (%) 764 765---------- End Simulation Statistics ---------- | 763system.membus.respLayer1.utilization 2.6 # Layer utilization (%) 764 765---------- End Simulation Statistics ---------- |