4,5c4,5
< sim_ticks 270200000 # Number of ticks simulated
< final_tick 270200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 269998000 # Number of ticks simulated
> final_tick 269998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 24805 # Simulator instruction rate (inst/s)
< host_op_rate 24804 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 29619482 # Simulator tick rate (ticks/s)
< host_mem_usage 244928 # Number of bytes of host memory used
< host_seconds 9.12 # Real time elapsed on the host
---
> host_inst_rate 216821 # Simulator instruction rate (inst/s)
> host_op_rate 216819 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 258712153 # Simulator tick rate (ticks/s)
> host_mem_usage 263004 # Number of bytes of host memory used
> host_seconds 1.04 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 248230940 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 71295337 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 319526277 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 248230940 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 248230940 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 248230940 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 71295337 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 319526277 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 248416655 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 71348677 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 319765332 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 248416655 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 248416655 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 248416655 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 71348677 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 319765332 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 269959000 # Total gap between requests
---
> system.physmem.totGap 269757000 # Total gap between requests
192,196c192,196
< system.physmem.bytesPerActivate::gmean 238.583723 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 292.748127 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 53 22.18% 22.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 57 23.85% 46.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 30 12.55% 58.58% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 237.806193 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 293.628623 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 54 22.59% 22.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 57 23.85% 46.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 29 12.13% 58.58% # Bytes accessed per row activation
198,199c198,199
< system.physmem.bytesPerActivate::512-639 21 8.79% 82.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 16 6.69% 88.70% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::512-639 20 8.37% 81.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 17 7.11% 88.70% # Bytes accessed per row activation
204,205c204,205
< system.physmem.totQLat 15283750 # Total ticks spent queuing
< system.physmem.totMemAccLat 40577500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 15217250 # Total ticks spent queuing
> system.physmem.totMemAccLat 40511000 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 11329.69 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 11280.39 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 30079.69 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 319.53 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 30030.39 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 319.77 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 319.53 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 319.77 # Average system read bandwidth in MiByte/s
224c224
< system.physmem.avgGap 200117.87 # Average gap between requests
---
> system.physmem.avgGap 199968.12 # Average gap between requests
231,234c231,234
< system.physmem_0.actBackEnergy 13396710 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 455520 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 92913420 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 13776960 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actBackEnergy 13384170 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 450240 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 94080210 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 12732960 # Energy for precharge power-down per rank (pJ)
236,239c236,239
< system.physmem_0.totalEnergy 148257960 # Total energy per rank (pJ)
< system.physmem_0.averagePower 548.697113 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 238953500 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 216000 # Time in different power states
---
> system.physmem_0.totalEnergy 148362930 # Total energy per rank (pJ)
> system.physmem_0.averagePower 549.494877 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 238782750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states
242,244c242,244
< system.physmem_0.memoryStateTime::PRE_PDN 35871500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 21502750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 203769750 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 33151500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 21477500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 206319000 # Time in different power states
250,253c250,253
< system.physmem_1.actBackEnergy 11664480 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 3533280 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 82867740 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 20352000 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actBackEnergy 11660490 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 3532800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 84455190 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 18941760 # Energy for precharge power-down per rank (pJ)
255,257c255,257
< system.physmem_1.totalEnergy 146140035 # Total energy per rank (pJ)
< system.physmem_1.averagePower 540.858753 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 235236750 # Total Idle time Per DRAM Rank
---
> system.physmem_1.totalEnergy 146312775 # Total energy per rank (pJ)
> system.physmem_1.averagePower 541.901675 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 235034750 # Total Idle time Per DRAM Rank
261c261
< system.physmem_1.memoryStateTime::PRE_PDN 53009000 # Time in different power states
---
> system.physmem_1.memoryStateTime::PRE_PDN 49337750 # Time in different power states
263,269c263,269
< system.physmem_1.memoryStateTime::ACT_PDN 181741250 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 61485 # Number of BP lookups
< system.cpu.branchPred.condPredicted 39320 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 4384 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 51667 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 29457 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::ACT_PDN 185210500 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 61459 # Number of BP lookups
> system.cpu.branchPred.condPredicted 39303 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 4350 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 48024 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 29463 # Number of BTB hits
271c271
< system.cpu.branchPred.BTBHitPct 57.013181 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 61.350575 # BTB Hit Percentage
274,276c274,276
< system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 6105 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 4159 # Number of indirect misses.
---
> system.cpu.branchPred.indirectLookups 10253 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 6091 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 4162 # Number of indirect misses.
298,299c298,299
< system.cpu.pwrStateResidencyTicks::ON 270200000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 540400 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 269998000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 539996 # number of cpu cycles simulated
304c304
< system.cpu.discardedOps 10623 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 10605 # Number of ops (including micro ops) which were discarded before commit
306,307c306,307
< system.cpu.cpi 2.388244 # CPI: cycles per instruction
< system.cpu.ipc 0.418718 # IPC: instructions per cycle
---
> system.cpu.cpi 2.386459 # CPI: cycles per instruction
> system.cpu.ipc 0.419031 # IPC: instructions per cycle
347,349c347,349
< system.cpu.tickCycles 340080 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 200320 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 339832 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 200164 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
351,352c351,352
< system.cpu.dcache.tags.tagsinuse 242.026814 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 90015 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 242.012615 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 90016 # Total number of references to valid blocks.
354c354
< system.cpu.dcache.tags.avg_refs 298.062914 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 298.066225 # Average number of references to valid blocks.
356,358c356,358
< system.cpu.dcache.tags.occ_blocks::cpu.data 242.026814 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.059089 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.059089 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 242.012615 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.059085 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.059085 # Average percentage of cache occupancy
364,368c364,368
< system.cpu.dcache.tags.tag_accesses 181330 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 181330 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 53182 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 53182 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 181332 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 181332 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 53183 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 53183 # number of ReadReq hits
371,374c371,374
< system.cpu.dcache.demand_hits::cpu.data 90015 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 90015 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 90015 # number of overall hits
< system.cpu.dcache.overall_hits::total 90015 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 90016 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 90016 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 90016 # number of overall hits
> system.cpu.dcache.overall_hits::total 90016 # number of overall hits
383,384c383,384
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9494000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9494000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9627000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9627000 # number of ReadReq miss cycles
387,392c387,392
< system.cpu.dcache.demand_miss_latency::cpu.data 41172500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 41172500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 41172500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 41172500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 53285 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 53285 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 41305500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 41305500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 41305500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 41305500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 53286 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 53286 # number of ReadReq accesses(hits+misses)
395,398c395,398
< system.cpu.dcache.demand_accesses::cpu.data 90514 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 90514 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 90514 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 90514 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 90515 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 90515 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 90515 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 90515 # number of overall (read+write) accesses
407,408c407,408
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92174.757282 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 92174.757282 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93466.019417 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 93466.019417 # average ReadReq miss latency
411,414c411,414
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 82510.020040 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 82510.020040 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 82776.553106 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 82776.553106 # average overall miss latency
437,438c437,438
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8881000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8881000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9014000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9014000 # number of ReadReq MSHR miss cycles
441,444c441,444
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25237000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 25237000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25237000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 25237000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25370000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 25370000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25370000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 25370000 # number of overall MSHR miss cycles
449,454c449,454
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.003337 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.003337 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91556.701031 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91556.701031 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.003336 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.003336 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92927.835052 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92927.835052 # average ReadReq mshr miss latency
457,461c457,461
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
463,464c463,464
< system.cpu.icache.tags.tagsinuse 555.532163 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 101722 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 555.459146 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 101640 # Total number of references to valid blocks.
466c466
< system.cpu.icache.tags.avg_refs 96.785918 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 96.707897 # Average number of references to valid blocks.
468,470c468,470
< system.cpu.icache.tags.occ_blocks::cpu.inst 555.532163 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.271256 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.271256 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 555.459146 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.271220 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.271220 # Average percentage of cache occupancy
476,484c476,484
< system.cpu.icache.tags.tag_accesses 206597 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 206597 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 101722 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 101722 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 101722 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 101722 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 101722 # number of overall hits
< system.cpu.icache.overall_hits::total 101722 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 206433 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 206433 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 101640 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 101640 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 101640 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 101640 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 101640 # number of overall hits
> system.cpu.icache.overall_hits::total 101640 # number of overall hits
491,514c491,514
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 87209500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 87209500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 87209500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 87209500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 87209500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 87209500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 102773 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 102773 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 102773 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 102773 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 102773 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 102773 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010226 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.010226 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.010226 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.010226 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.010226 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.010226 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82977.640343 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 82977.640343 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 82977.640343 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 82977.640343 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 87010500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 87010500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 87010500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 87010500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 87010500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 87010500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 102691 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 102691 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 102691 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 102691 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 102691 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 102691 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010235 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.010235 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.010235 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.010235 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.010235 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.010235 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82788.296860 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 82788.296860 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 82788.296860 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 82788.296860 # average overall miss latency
529,547c529,547
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86158500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 86158500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86158500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 86158500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86158500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 86158500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010226 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.010226 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.010226 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81977.640343 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81977.640343 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 85959500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 85959500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 85959500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 85959500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 85959500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 85959500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010235 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.010235 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.010235 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81788.296860 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81788.296860 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
549c549
< system.cpu.l2cache.tags.tagsinuse 827.037841 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 826.940635 # Cycle average of tags in use
554,556c554,556
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.656330 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 241.381510 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017873 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.573058 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 241.367577 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017870 # Average percentage of cache occupancy
558c558
< system.cpu.l2cache.tags.occ_percent::total 0.025239 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.025236 # Average percentage of cache occupancy
566c566
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
593,602c593,602
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84550500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 84550500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8723000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 8723000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 84550500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 24771500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 109322000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 84550500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 24771500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 109322000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84351500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 84351500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8856000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 8856000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 84351500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 24904500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 109256000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 84351500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 24904500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 109256000 # number of overall miss cycles
631,640c631,640
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80677.958015 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80677.958015 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90864.583333 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90864.583333 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 81039.288362 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 81039.288362 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80488.072519 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80488.072519 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92250 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92250 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 80990.363232 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 80990.363232 # average overall miss latency
661,670c661,670
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74070500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74070500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7763000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7763000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74070500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21761500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 95832000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74070500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21761500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 95832000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73871500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73871500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7896000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7896000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73871500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21894500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 95766000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73871500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21894500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 95766000 # number of overall MSHR miss cycles
685,694c685,694
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70677.958015 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70677.958015 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80864.583333 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80864.583333 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70488.072519 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70488.072519 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82250 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency
701c701
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
739c739
< system.membus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
760c760
< system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1553000 # Layer occupancy (ticks)
762c762
< system.membus.respLayer1.occupancy 7151000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 7152500 # Layer occupancy (ticks)
< sim_ticks 270200000 # Number of ticks simulated
< final_tick 270200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 269998000 # Number of ticks simulated
> final_tick 269998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 24805 # Simulator instruction rate (inst/s)
< host_op_rate 24804 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 29619482 # Simulator tick rate (ticks/s)
< host_mem_usage 244928 # Number of bytes of host memory used
< host_seconds 9.12 # Real time elapsed on the host
---
> host_inst_rate 216821 # Simulator instruction rate (inst/s)
> host_op_rate 216819 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 258712153 # Simulator tick rate (ticks/s)
> host_mem_usage 263004 # Number of bytes of host memory used
> host_seconds 1.04 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 248230940 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 71295337 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 319526277 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 248230940 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 248230940 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 248230940 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 71295337 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 319526277 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 248416655 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 71348677 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 319765332 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 248416655 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 248416655 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 248416655 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 71348677 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 319765332 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 269959000 # Total gap between requests
---
> system.physmem.totGap 269757000 # Total gap between requests
192,196c192,196
< system.physmem.bytesPerActivate::gmean 238.583723 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 292.748127 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 53 22.18% 22.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 57 23.85% 46.03% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 30 12.55% 58.58% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 237.806193 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 293.628623 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 54 22.59% 22.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 57 23.85% 46.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 29 12.13% 58.58% # Bytes accessed per row activation
198,199c198,199
< system.physmem.bytesPerActivate::512-639 21 8.79% 82.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 16 6.69% 88.70% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::512-639 20 8.37% 81.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 17 7.11% 88.70% # Bytes accessed per row activation
204,205c204,205
< system.physmem.totQLat 15283750 # Total ticks spent queuing
< system.physmem.totMemAccLat 40577500 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 15217250 # Total ticks spent queuing
> system.physmem.totMemAccLat 40511000 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 11329.69 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 11280.39 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 30079.69 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 319.53 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 30030.39 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 319.77 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 319.53 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 319.77 # Average system read bandwidth in MiByte/s
224c224
< system.physmem.avgGap 200117.87 # Average gap between requests
---
> system.physmem.avgGap 199968.12 # Average gap between requests
231,234c231,234
< system.physmem_0.actBackEnergy 13396710 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 455520 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 92913420 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 13776960 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actBackEnergy 13384170 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 450240 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 94080210 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 12732960 # Energy for precharge power-down per rank (pJ)
236,239c236,239
< system.physmem_0.totalEnergy 148257960 # Total energy per rank (pJ)
< system.physmem_0.averagePower 548.697113 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 238953500 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 216000 # Time in different power states
---
> system.physmem_0.totalEnergy 148362930 # Total energy per rank (pJ)
> system.physmem_0.averagePower 549.494877 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 238782750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 210000 # Time in different power states
242,244c242,244
< system.physmem_0.memoryStateTime::PRE_PDN 35871500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 21502750 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 203769750 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 33151500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 21477500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 206319000 # Time in different power states
250,253c250,253
< system.physmem_1.actBackEnergy 11664480 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 3533280 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 82867740 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 20352000 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actBackEnergy 11660490 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 3532800 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 84455190 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 18941760 # Energy for precharge power-down per rank (pJ)
255,257c255,257
< system.physmem_1.totalEnergy 146140035 # Total energy per rank (pJ)
< system.physmem_1.averagePower 540.858753 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 235236750 # Total Idle time Per DRAM Rank
---
> system.physmem_1.totalEnergy 146312775 # Total energy per rank (pJ)
> system.physmem_1.averagePower 541.901675 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 235034750 # Total Idle time Per DRAM Rank
261c261
< system.physmem_1.memoryStateTime::PRE_PDN 53009000 # Time in different power states
---
> system.physmem_1.memoryStateTime::PRE_PDN 49337750 # Time in different power states
263,269c263,269
< system.physmem_1.memoryStateTime::ACT_PDN 181741250 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 61485 # Number of BP lookups
< system.cpu.branchPred.condPredicted 39320 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 4384 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 51667 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 29457 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::ACT_PDN 185210500 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 61459 # Number of BP lookups
> system.cpu.branchPred.condPredicted 39303 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 4350 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 48024 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 29463 # Number of BTB hits
271c271
< system.cpu.branchPred.BTBHitPct 57.013181 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 61.350575 # BTB Hit Percentage
274,276c274,276
< system.cpu.branchPred.indirectLookups 10264 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 6105 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 4159 # Number of indirect misses.
---
> system.cpu.branchPred.indirectLookups 10253 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 6091 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 4162 # Number of indirect misses.
298,299c298,299
< system.cpu.pwrStateResidencyTicks::ON 270200000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 540400 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 269998000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 539996 # number of cpu cycles simulated
304c304
< system.cpu.discardedOps 10623 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 10605 # Number of ops (including micro ops) which were discarded before commit
306,307c306,307
< system.cpu.cpi 2.388244 # CPI: cycles per instruction
< system.cpu.ipc 0.418718 # IPC: instructions per cycle
---
> system.cpu.cpi 2.386459 # CPI: cycles per instruction
> system.cpu.ipc 0.419031 # IPC: instructions per cycle
347,349c347,349
< system.cpu.tickCycles 340080 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 200320 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 339832 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 200164 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
351,352c351,352
< system.cpu.dcache.tags.tagsinuse 242.026814 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 90015 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 242.012615 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 90016 # Total number of references to valid blocks.
354c354
< system.cpu.dcache.tags.avg_refs 298.062914 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 298.066225 # Average number of references to valid blocks.
356,358c356,358
< system.cpu.dcache.tags.occ_blocks::cpu.data 242.026814 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.059089 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.059089 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 242.012615 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.059085 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.059085 # Average percentage of cache occupancy
364,368c364,368
< system.cpu.dcache.tags.tag_accesses 181330 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 181330 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 53182 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 53182 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 181332 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 181332 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 53183 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 53183 # number of ReadReq hits
371,374c371,374
< system.cpu.dcache.demand_hits::cpu.data 90015 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 90015 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 90015 # number of overall hits
< system.cpu.dcache.overall_hits::total 90015 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 90016 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 90016 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 90016 # number of overall hits
> system.cpu.dcache.overall_hits::total 90016 # number of overall hits
383,384c383,384
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9494000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9494000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 9627000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 9627000 # number of ReadReq miss cycles
387,392c387,392
< system.cpu.dcache.demand_miss_latency::cpu.data 41172500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 41172500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 41172500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 41172500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 53285 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 53285 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 41305500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 41305500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 41305500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 41305500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 53286 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 53286 # number of ReadReq accesses(hits+misses)
395,398c395,398
< system.cpu.dcache.demand_accesses::cpu.data 90514 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 90514 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 90514 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 90514 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 90515 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 90515 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 90515 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 90515 # number of overall (read+write) accesses
407,408c407,408
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92174.757282 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 92174.757282 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93466.019417 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 93466.019417 # average ReadReq miss latency
411,414c411,414
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 82510.020040 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 82510.020040 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 82510.020040 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 82776.553106 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 82776.553106 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 82776.553106 # average overall miss latency
437,438c437,438
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8881000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8881000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9014000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 9014000 # number of ReadReq MSHR miss cycles
441,444c441,444
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25237000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 25237000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25237000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 25237000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25370000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 25370000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25370000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 25370000 # number of overall MSHR miss cycles
449,454c449,454
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.003337 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003337 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.003337 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91556.701031 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91556.701031 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.003336 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003336 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.003336 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92927.835052 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92927.835052 # average ReadReq mshr miss latency
457,461c457,461
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83566.225166 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 83566.225166 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84006.622517 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 84006.622517 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
463,464c463,464
< system.cpu.icache.tags.tagsinuse 555.532163 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 101722 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 555.459146 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 101640 # Total number of references to valid blocks.
466c466
< system.cpu.icache.tags.avg_refs 96.785918 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 96.707897 # Average number of references to valid blocks.
468,470c468,470
< system.cpu.icache.tags.occ_blocks::cpu.inst 555.532163 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.271256 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.271256 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 555.459146 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.271220 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.271220 # Average percentage of cache occupancy
476,484c476,484
< system.cpu.icache.tags.tag_accesses 206597 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 206597 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 101722 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 101722 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 101722 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 101722 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 101722 # number of overall hits
< system.cpu.icache.overall_hits::total 101722 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 206433 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 206433 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 101640 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 101640 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 101640 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 101640 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 101640 # number of overall hits
> system.cpu.icache.overall_hits::total 101640 # number of overall hits
491,514c491,514
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 87209500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 87209500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 87209500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 87209500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 87209500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 87209500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 102773 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 102773 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 102773 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 102773 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 102773 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 102773 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010226 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.010226 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.010226 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.010226 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.010226 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.010226 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82977.640343 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 82977.640343 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 82977.640343 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 82977.640343 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 82977.640343 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 87010500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 87010500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 87010500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 87010500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 87010500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 87010500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 102691 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 102691 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 102691 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 102691 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 102691 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 102691 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.010235 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.010235 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.010235 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.010235 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.010235 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.010235 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 82788.296860 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 82788.296860 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 82788.296860 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 82788.296860 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 82788.296860 # average overall miss latency
529,547c529,547
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 86158500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 86158500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 86158500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 86158500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 86158500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 86158500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010226 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.010226 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010226 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.010226 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81977.640343 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81977.640343 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81977.640343 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 81977.640343 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 85959500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 85959500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 85959500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 85959500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 85959500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 85959500 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.010235 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.010235 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.010235 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.010235 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81788.296860 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81788.296860 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81788.296860 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 81788.296860 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
549c549
< system.cpu.l2cache.tags.tagsinuse 827.037841 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 826.940635 # Cycle average of tags in use
554,556c554,556
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.656330 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 241.381510 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017873 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 585.573058 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 241.367577 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017870 # Average percentage of cache occupancy
558c558
< system.cpu.l2cache.tags.occ_percent::total 0.025239 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.025236 # Average percentage of cache occupancy
566c566
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
593,602c593,602
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84550500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 84550500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8723000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 8723000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 84550500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 24771500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 109322000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 84550500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 24771500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 109322000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 84351500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 84351500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8856000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 8856000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 84351500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 24904500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 109256000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 84351500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 24904500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 109256000 # number of overall miss cycles
631,640c631,640
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80677.958015 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80677.958015 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 90864.583333 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 90864.583333 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 81039.288362 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80677.958015 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82297.342193 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 81039.288362 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 80488.072519 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 80488.072519 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92250 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92250 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 80990.363232 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80488.072519 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82739.202658 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 80990.363232 # average overall miss latency
661,670c661,670
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 74070500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 74070500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7763000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7763000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 74070500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21761500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 95832000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 74070500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21761500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 95832000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 73871500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 73871500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7896000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7896000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 73871500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21894500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 95766000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 73871500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21894500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 95766000 # number of overall MSHR miss cycles
685,694c685,694
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70677.958015 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70677.958015 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80864.583333 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80864.583333 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70677.958015 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72297.342193 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71039.288362 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 70488.072519 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 70488.072519 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82250 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70488.072519 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72739.202658 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70990.363232 # average overall mshr miss latency
701c701
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
739c739
< system.membus.pwrStateResidencyTicks::UNDEFINED 270200000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 269998000 # Cumulative time (in ticks) in various power states
760c760
< system.membus.reqLayer0.occupancy 1554000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1553000 # Layer occupancy (ticks)
762c762
< system.membus.respLayer1.occupancy 7151000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 7152500 # Layer occupancy (ticks)