1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.000497 # Number of seconds simulated
4sim_ticks 497165500 # Number of ticks simulated
5final_tick 497165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 27513 # Simulator instruction rate (inst/s)
8host_op_rate 27513 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 45717681 # Simulator tick rate (ticks/s)
10host_mem_usage 243824 # Number of bytes of host memory used
11host_seconds 10.87 # Real time elapsed on the host
12sim_insts 299191 # Number of instructions simulated
13sim_ops 299191 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 20224 # Number of bytes read from this memory
19system.physmem.bytes_read::total 81984 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 61760 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 61760 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 965 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 316 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 1281 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 124224227 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 40678607 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 164902834 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 124224227 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 124224227 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 124224227 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 40678607 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 164902834 # Total bandwidth to/from this memory (bytes/s)
33system.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
34system.cpu_clk_domain.clock 500 # Clock period in ticks
35system.cpu.dtb.read_hits 0 # DTB read hits
36system.cpu.dtb.read_misses 0 # DTB read misses
37system.cpu.dtb.read_accesses 0 # DTB read accesses
38system.cpu.dtb.write_hits 0 # DTB write hits
39system.cpu.dtb.write_misses 0 # DTB write misses
40system.cpu.dtb.write_accesses 0 # DTB write accesses
41system.cpu.dtb.hits 0 # DTB hits
42system.cpu.dtb.misses 0 # DTB misses
43system.cpu.dtb.accesses 0 # DTB accesses
44system.cpu.itb.read_hits 0 # DTB read hits
45system.cpu.itb.read_misses 0 # DTB read misses
46system.cpu.itb.read_accesses 0 # DTB read accesses
47system.cpu.itb.write_hits 0 # DTB write hits
48system.cpu.itb.write_misses 0 # DTB write misses
49system.cpu.itb.write_accesses 0 # DTB write accesses
50system.cpu.itb.hits 0 # DTB hits
51system.cpu.itb.misses 0 # DTB misses
52system.cpu.itb.accesses 0 # DTB accesses
53system.cpu.workload.numSyscalls 162 # Number of system calls
54system.cpu.pwrStateResidencyTicks::ON 497165500 # Cumulative time (in ticks) in various power states
55system.cpu.numCycles 994331 # number of cpu cycles simulated
56system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
57system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
58system.cpu.committedInsts 299191 # Number of instructions committed
59system.cpu.committedOps 299191 # Number of ops (including micro ops) committed
60system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses
61system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses
62system.cpu.num_func_calls 21816 # number of times a function call or return occured
63system.cpu.num_conditional_control_insts 44561 # number of instructions that are conditional controls
64system.cpu.num_int_insts 299008 # number of integer instructions
65system.cpu.num_fp_insts 1025 # number of float instructions
66system.cpu.num_int_register_reads 394163 # number of times the integer registers were read
67system.cpu.num_int_register_writes 205779 # number of times the integer registers were written
68system.cpu.num_fp_register_reads 851 # number of times the floating registers were read
69system.cpu.num_fp_register_writes 688 # number of times the floating registers were written
70system.cpu.num_mem_refs 118390 # number of memory refs
71system.cpu.num_load_insts 69843 # Number of load instructions
72system.cpu.num_store_insts 48547 # Number of store instructions
73system.cpu.num_idle_cycles 0 # Number of idle cycles
74system.cpu.num_busy_cycles 994331 # Number of busy cycles
75system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
76system.cpu.idle_fraction 0 # Percentage of idle cycles
77system.cpu.Branches 66377 # Number of branches fetched
78system.cpu.op_class::No_OpClass 162 0.05% 0.05% # Class of executed instruction
79system.cpu.op_class::IntAlu 179913 60.10% 60.15% # Class of executed instruction
80system.cpu.op_class::IntMult 466 0.16% 60.31% # Class of executed instruction
81system.cpu.op_class::IntDiv 40 0.01% 60.32% # Class of executed instruction
82system.cpu.op_class::FloatAdd 120 0.04% 60.36% # Class of executed instruction
83system.cpu.op_class::FloatCmp 157 0.05% 60.42% # Class of executed instruction
84system.cpu.op_class::FloatCvt 60 0.02% 60.44% # Class of executed instruction
85system.cpu.op_class::FloatMult 30 0.01% 60.45% # Class of executed instruction
86system.cpu.op_class::FloatMultAcc 0 0.00% 60.45% # Class of executed instruction
87system.cpu.op_class::FloatDiv 11 0.00% 60.45% # Class of executed instruction
88system.cpu.op_class::FloatMisc 0 0.00% 60.45% # Class of executed instruction
89system.cpu.op_class::FloatSqrt 5 0.00% 60.45% # Class of executed instruction
90system.cpu.op_class::SimdAdd 0 0.00% 60.45% # Class of executed instruction
91system.cpu.op_class::SimdAddAcc 0 0.00% 60.45% # Class of executed instruction
92system.cpu.op_class::SimdAlu 0 0.00% 60.45% # Class of executed instruction
93system.cpu.op_class::SimdCmp 0 0.00% 60.45% # Class of executed instruction
94system.cpu.op_class::SimdCvt 0 0.00% 60.45% # Class of executed instruction
95system.cpu.op_class::SimdMisc 0 0.00% 60.45% # Class of executed instruction
96system.cpu.op_class::SimdMult 0 0.00% 60.45% # Class of executed instruction
97system.cpu.op_class::SimdMultAcc 0 0.00% 60.45% # Class of executed instruction
98system.cpu.op_class::SimdShift 0 0.00% 60.45% # Class of executed instruction
99system.cpu.op_class::SimdShiftAcc 0 0.00% 60.45% # Class of executed instruction
100system.cpu.op_class::SimdSqrt 0 0.00% 60.45% # Class of executed instruction
101system.cpu.op_class::SimdFloatAdd 0 0.00% 60.45% # Class of executed instruction
102system.cpu.op_class::SimdFloatAlu 0 0.00% 60.45% # Class of executed instruction
103system.cpu.op_class::SimdFloatCmp 0 0.00% 60.45% # Class of executed instruction
104system.cpu.op_class::SimdFloatCvt 0 0.00% 60.45% # Class of executed instruction
105system.cpu.op_class::SimdFloatDiv 0 0.00% 60.45% # Class of executed instruction
106system.cpu.op_class::SimdFloatMisc 0 0.00% 60.45% # Class of executed instruction
107system.cpu.op_class::SimdFloatMult 0 0.00% 60.45% # Class of executed instruction
108system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.45% # Class of executed instruction
109system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.45% # Class of executed instruction
110system.cpu.op_class::MemRead 69348 23.17% 83.62% # Class of executed instruction
111system.cpu.op_class::MemWrite 48400 16.17% 99.79% # Class of executed instruction
112system.cpu.op_class::FloatMemRead 495 0.17% 99.95% # Class of executed instruction
113system.cpu.op_class::FloatMemWrite 147 0.05% 100.00% # Class of executed instruction
114system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
115system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
116system.cpu.op_class::total 299354 # Class of executed instruction
117system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
118system.cpu.dcache.tags.replacements 0 # number of replacements
119system.cpu.dcache.tags.tagsinuse 258.453748 # Cycle average of tags in use
120system.cpu.dcache.tags.total_refs 118073 # Total number of references to valid blocks.
121system.cpu.dcache.tags.sampled_refs 316 # Sample count of references to valid blocks.
122system.cpu.dcache.tags.avg_refs 373.648734 # Average number of references to valid blocks.
123system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
124system.cpu.dcache.tags.occ_blocks::cpu.data 258.453748 # Average occupied blocks per requestor
125system.cpu.dcache.tags.occ_percent::cpu.data 0.063099 # Average percentage of cache occupancy
126system.cpu.dcache.tags.occ_percent::total 0.063099 # Average percentage of cache occupancy
127system.cpu.dcache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id
128system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
129system.cpu.dcache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
130system.cpu.dcache.tags.age_task_id_blocks_1024::2 296 # Occupied blocks per task id
131system.cpu.dcache.tags.occ_task_id_percent::1024 0.077148 # Percentage of cache occupancy per task id
132system.cpu.dcache.tags.tag_accesses 237094 # Number of tag accesses
133system.cpu.dcache.tags.data_accesses 237094 # Number of data accesses
134system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
135system.cpu.dcache.ReadReq_hits::cpu.data 69732 # number of ReadReq hits
136system.cpu.dcache.ReadReq_hits::total 69732 # number of ReadReq hits
137system.cpu.dcache.WriteReq_hits::cpu.data 48341 # number of WriteReq hits
138system.cpu.dcache.WriteReq_hits::total 48341 # number of WriteReq hits
139system.cpu.dcache.demand_hits::cpu.data 118073 # number of demand (read+write) hits
140system.cpu.dcache.demand_hits::total 118073 # number of demand (read+write) hits
141system.cpu.dcache.overall_hits::cpu.data 118073 # number of overall hits
142system.cpu.dcache.overall_hits::total 118073 # number of overall hits
143system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses
144system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses
145system.cpu.dcache.WriteReq_misses::cpu.data 205 # number of WriteReq misses
146system.cpu.dcache.WriteReq_misses::total 205 # number of WriteReq misses
147system.cpu.dcache.demand_misses::cpu.data 316 # number of demand (read+write) misses
148system.cpu.dcache.demand_misses::total 316 # number of demand (read+write) misses
149system.cpu.dcache.overall_misses::cpu.data 316 # number of overall misses
150system.cpu.dcache.overall_misses::total 316 # number of overall misses
151system.cpu.dcache.ReadReq_miss_latency::cpu.data 6993000 # number of ReadReq miss cycles
152system.cpu.dcache.ReadReq_miss_latency::total 6993000 # number of ReadReq miss cycles
153system.cpu.dcache.WriteReq_miss_latency::cpu.data 12915000 # number of WriteReq miss cycles
154system.cpu.dcache.WriteReq_miss_latency::total 12915000 # number of WriteReq miss cycles
155system.cpu.dcache.demand_miss_latency::cpu.data 19908000 # number of demand (read+write) miss cycles
156system.cpu.dcache.demand_miss_latency::total 19908000 # number of demand (read+write) miss cycles
157system.cpu.dcache.overall_miss_latency::cpu.data 19908000 # number of overall miss cycles
158system.cpu.dcache.overall_miss_latency::total 19908000 # number of overall miss cycles
159system.cpu.dcache.ReadReq_accesses::cpu.data 69843 # number of ReadReq accesses(hits+misses)
160system.cpu.dcache.ReadReq_accesses::total 69843 # number of ReadReq accesses(hits+misses)
161system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses)
162system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses)
163system.cpu.dcache.demand_accesses::cpu.data 118389 # number of demand (read+write) accesses
164system.cpu.dcache.demand_accesses::total 118389 # number of demand (read+write) accesses
165system.cpu.dcache.overall_accesses::cpu.data 118389 # number of overall (read+write) accesses
166system.cpu.dcache.overall_accesses::total 118389 # number of overall (read+write) accesses
167system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001589 # miss rate for ReadReq accesses
168system.cpu.dcache.ReadReq_miss_rate::total 0.001589 # miss rate for ReadReq accesses
169system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004223 # miss rate for WriteReq accesses
170system.cpu.dcache.WriteReq_miss_rate::total 0.004223 # miss rate for WriteReq accesses
171system.cpu.dcache.demand_miss_rate::cpu.data 0.002669 # miss rate for demand accesses
172system.cpu.dcache.demand_miss_rate::total 0.002669 # miss rate for demand accesses
173system.cpu.dcache.overall_miss_rate::cpu.data 0.002669 # miss rate for overall accesses
174system.cpu.dcache.overall_miss_rate::total 0.002669 # miss rate for overall accesses
175system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
176system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
177system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
178system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
179system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
180system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
181system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
182system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
183system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
184system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
185system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
186system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
187system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
188system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
189system.cpu.dcache.ReadReq_mshr_misses::cpu.data 111 # number of ReadReq MSHR misses
190system.cpu.dcache.ReadReq_mshr_misses::total 111 # number of ReadReq MSHR misses
191system.cpu.dcache.WriteReq_mshr_misses::cpu.data 205 # number of WriteReq MSHR misses
192system.cpu.dcache.WriteReq_mshr_misses::total 205 # number of WriteReq MSHR misses
193system.cpu.dcache.demand_mshr_misses::cpu.data 316 # number of demand (read+write) MSHR misses
194system.cpu.dcache.demand_mshr_misses::total 316 # number of demand (read+write) MSHR misses
195system.cpu.dcache.overall_mshr_misses::cpu.data 316 # number of overall MSHR misses
196system.cpu.dcache.overall_mshr_misses::total 316 # number of overall MSHR misses
197system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6882000 # number of ReadReq MSHR miss cycles
198system.cpu.dcache.ReadReq_mshr_miss_latency::total 6882000 # number of ReadReq MSHR miss cycles
199system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12710000 # number of WriteReq MSHR miss cycles
200system.cpu.dcache.WriteReq_mshr_miss_latency::total 12710000 # number of WriteReq MSHR miss cycles
201system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19592000 # number of demand (read+write) MSHR miss cycles
202system.cpu.dcache.demand_mshr_miss_latency::total 19592000 # number of demand (read+write) MSHR miss cycles
203system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19592000 # number of overall MSHR miss cycles
204system.cpu.dcache.overall_mshr_miss_latency::total 19592000 # number of overall MSHR miss cycles
205system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001589 # mshr miss rate for ReadReq accesses
206system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001589 # mshr miss rate for ReadReq accesses
207system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004223 # mshr miss rate for WriteReq accesses
208system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004223 # mshr miss rate for WriteReq accesses
209system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002669 # mshr miss rate for demand accesses
210system.cpu.dcache.demand_mshr_miss_rate::total 0.002669 # mshr miss rate for demand accesses
211system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002669 # mshr miss rate for overall accesses
212system.cpu.dcache.overall_mshr_miss_rate::total 0.002669 # mshr miss rate for overall accesses
213system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
214system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
215system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
216system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
217system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
218system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
219system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
220system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
221system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
222system.cpu.icache.tags.replacements 26 # number of replacements
223system.cpu.icache.tags.tagsinuse 551.353598 # Cycle average of tags in use
224system.cpu.icache.tags.total_refs 298390 # Total number of references to valid blocks.
225system.cpu.icache.tags.sampled_refs 965 # Sample count of references to valid blocks.
226system.cpu.icache.tags.avg_refs 309.212435 # Average number of references to valid blocks.
227system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
228system.cpu.icache.tags.occ_blocks::cpu.inst 551.353598 # Average occupied blocks per requestor
229system.cpu.icache.tags.occ_percent::cpu.inst 0.269216 # Average percentage of cache occupancy
230system.cpu.icache.tags.occ_percent::total 0.269216 # Average percentage of cache occupancy
231system.cpu.icache.tags.occ_task_id_blocks::1024 939 # Occupied blocks per task id
232system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
233system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
234system.cpu.icache.tags.age_task_id_blocks_1024::2 774 # Occupied blocks per task id
235system.cpu.icache.tags.occ_task_id_percent::1024 0.458496 # Percentage of cache occupancy per task id
236system.cpu.icache.tags.tag_accesses 599675 # Number of tag accesses
237system.cpu.icache.tags.data_accesses 599675 # Number of data accesses
238system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
239system.cpu.icache.ReadReq_hits::cpu.inst 298390 # number of ReadReq hits
240system.cpu.icache.ReadReq_hits::total 298390 # number of ReadReq hits
241system.cpu.icache.demand_hits::cpu.inst 298390 # number of demand (read+write) hits
242system.cpu.icache.demand_hits::total 298390 # number of demand (read+write) hits
243system.cpu.icache.overall_hits::cpu.inst 298390 # number of overall hits
244system.cpu.icache.overall_hits::total 298390 # number of overall hits
245system.cpu.icache.ReadReq_misses::cpu.inst 965 # number of ReadReq misses
246system.cpu.icache.ReadReq_misses::total 965 # number of ReadReq misses
247system.cpu.icache.demand_misses::cpu.inst 965 # number of demand (read+write) misses
248system.cpu.icache.demand_misses::total 965 # number of demand (read+write) misses
249system.cpu.icache.overall_misses::cpu.inst 965 # number of overall misses
250system.cpu.icache.overall_misses::total 965 # number of overall misses
251system.cpu.icache.ReadReq_miss_latency::cpu.inst 60795500 # number of ReadReq miss cycles
252system.cpu.icache.ReadReq_miss_latency::total 60795500 # number of ReadReq miss cycles
253system.cpu.icache.demand_miss_latency::cpu.inst 60795500 # number of demand (read+write) miss cycles
254system.cpu.icache.demand_miss_latency::total 60795500 # number of demand (read+write) miss cycles
255system.cpu.icache.overall_miss_latency::cpu.inst 60795500 # number of overall miss cycles
256system.cpu.icache.overall_miss_latency::total 60795500 # number of overall miss cycles
257system.cpu.icache.ReadReq_accesses::cpu.inst 299355 # number of ReadReq accesses(hits+misses)
258system.cpu.icache.ReadReq_accesses::total 299355 # number of ReadReq accesses(hits+misses)
259system.cpu.icache.demand_accesses::cpu.inst 299355 # number of demand (read+write) accesses
260system.cpu.icache.demand_accesses::total 299355 # number of demand (read+write) accesses
261system.cpu.icache.overall_accesses::cpu.inst 299355 # number of overall (read+write) accesses
262system.cpu.icache.overall_accesses::total 299355 # number of overall (read+write) accesses
263system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003224 # miss rate for ReadReq accesses
264system.cpu.icache.ReadReq_miss_rate::total 0.003224 # miss rate for ReadReq accesses
265system.cpu.icache.demand_miss_rate::cpu.inst 0.003224 # miss rate for demand accesses
266system.cpu.icache.demand_miss_rate::total 0.003224 # miss rate for demand accesses
267system.cpu.icache.overall_miss_rate::cpu.inst 0.003224 # miss rate for overall accesses
268system.cpu.icache.overall_miss_rate::total 0.003224 # miss rate for overall accesses
269system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63000.518135 # average ReadReq miss latency
270system.cpu.icache.ReadReq_avg_miss_latency::total 63000.518135 # average ReadReq miss latency
271system.cpu.icache.demand_avg_miss_latency::cpu.inst 63000.518135 # average overall miss latency
272system.cpu.icache.demand_avg_miss_latency::total 63000.518135 # average overall miss latency
273system.cpu.icache.overall_avg_miss_latency::cpu.inst 63000.518135 # average overall miss latency
274system.cpu.icache.overall_avg_miss_latency::total 63000.518135 # average overall miss latency
275system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
276system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
277system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
278system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
279system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
280system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
281system.cpu.icache.writebacks::writebacks 26 # number of writebacks
282system.cpu.icache.writebacks::total 26 # number of writebacks
283system.cpu.icache.ReadReq_mshr_misses::cpu.inst 965 # number of ReadReq MSHR misses
284system.cpu.icache.ReadReq_mshr_misses::total 965 # number of ReadReq MSHR misses
285system.cpu.icache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses
286system.cpu.icache.demand_mshr_misses::total 965 # number of demand (read+write) MSHR misses
287system.cpu.icache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses
288system.cpu.icache.overall_mshr_misses::total 965 # number of overall MSHR misses
289system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59830500 # number of ReadReq MSHR miss cycles
290system.cpu.icache.ReadReq_mshr_miss_latency::total 59830500 # number of ReadReq MSHR miss cycles
291system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59830500 # number of demand (read+write) MSHR miss cycles
292system.cpu.icache.demand_mshr_miss_latency::total 59830500 # number of demand (read+write) MSHR miss cycles
293system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59830500 # number of overall MSHR miss cycles
294system.cpu.icache.overall_mshr_miss_latency::total 59830500 # number of overall MSHR miss cycles
295system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for ReadReq accesses
296system.cpu.icache.ReadReq_mshr_miss_rate::total 0.003224 # mshr miss rate for ReadReq accesses
297system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for demand accesses
298system.cpu.icache.demand_mshr_miss_rate::total 0.003224 # mshr miss rate for demand accesses
299system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.003224 # mshr miss rate for overall accesses
300system.cpu.icache.overall_mshr_miss_rate::total 0.003224 # mshr miss rate for overall accesses
301system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62000.518135 # average ReadReq mshr miss latency
302system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62000.518135 # average ReadReq mshr miss latency
303system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62000.518135 # average overall mshr miss latency
304system.cpu.icache.demand_avg_mshr_miss_latency::total 62000.518135 # average overall mshr miss latency
305system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62000.518135 # average overall mshr miss latency
306system.cpu.icache.overall_avg_mshr_miss_latency::total 62000.518135 # average overall mshr miss latency
307system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
308system.cpu.l2cache.tags.replacements 0 # number of replacements
309system.cpu.l2cache.tags.tagsinuse 821.156872 # Cycle average of tags in use
310system.cpu.l2cache.tags.total_refs 26 # Total number of references to valid blocks.
311system.cpu.l2cache.tags.sampled_refs 1281 # Sample count of references to valid blocks.
312system.cpu.l2cache.tags.avg_refs 0.020297 # Average number of references to valid blocks.
313system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
314system.cpu.l2cache.tags.occ_blocks::cpu.inst 562.696450 # Average occupied blocks per requestor
315system.cpu.l2cache.tags.occ_blocks::cpu.data 258.460422 # Average occupied blocks per requestor
316system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017172 # Average percentage of cache occupancy
317system.cpu.l2cache.tags.occ_percent::cpu.data 0.007888 # Average percentage of cache occupancy
318system.cpu.l2cache.tags.occ_percent::total 0.025060 # Average percentage of cache occupancy
319system.cpu.l2cache.tags.occ_task_id_blocks::1024 1281 # Occupied blocks per task id
320system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
321system.cpu.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id
322system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1096 # Occupied blocks per task id
323system.cpu.l2cache.tags.occ_task_id_percent::1024 0.039093 # Percentage of cache occupancy per task id
324system.cpu.l2cache.tags.tag_accesses 11737 # Number of tag accesses
325system.cpu.l2cache.tags.data_accesses 11737 # Number of data accesses
326system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
327system.cpu.l2cache.WritebackClean_hits::writebacks 26 # number of WritebackClean hits
328system.cpu.l2cache.WritebackClean_hits::total 26 # number of WritebackClean hits
329system.cpu.l2cache.ReadExReq_misses::cpu.data 205 # number of ReadExReq misses
330system.cpu.l2cache.ReadExReq_misses::total 205 # number of ReadExReq misses
331system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 965 # number of ReadCleanReq misses
332system.cpu.l2cache.ReadCleanReq_misses::total 965 # number of ReadCleanReq misses
333system.cpu.l2cache.ReadSharedReq_misses::cpu.data 111 # number of ReadSharedReq misses
334system.cpu.l2cache.ReadSharedReq_misses::total 111 # number of ReadSharedReq misses
335system.cpu.l2cache.demand_misses::cpu.inst 965 # number of demand (read+write) misses
336system.cpu.l2cache.demand_misses::cpu.data 316 # number of demand (read+write) misses
337system.cpu.l2cache.demand_misses::total 1281 # number of demand (read+write) misses
338system.cpu.l2cache.overall_misses::cpu.inst 965 # number of overall misses
339system.cpu.l2cache.overall_misses::cpu.data 316 # number of overall misses
340system.cpu.l2cache.overall_misses::total 1281 # number of overall misses
341system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12402500 # number of ReadExReq miss cycles
342system.cpu.l2cache.ReadExReq_miss_latency::total 12402500 # number of ReadExReq miss cycles
343system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58383000 # number of ReadCleanReq miss cycles
344system.cpu.l2cache.ReadCleanReq_miss_latency::total 58383000 # number of ReadCleanReq miss cycles
345system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6715500 # number of ReadSharedReq miss cycles
346system.cpu.l2cache.ReadSharedReq_miss_latency::total 6715500 # number of ReadSharedReq miss cycles
347system.cpu.l2cache.demand_miss_latency::cpu.inst 58383000 # number of demand (read+write) miss cycles
348system.cpu.l2cache.demand_miss_latency::cpu.data 19118000 # number of demand (read+write) miss cycles
349system.cpu.l2cache.demand_miss_latency::total 77501000 # number of demand (read+write) miss cycles
350system.cpu.l2cache.overall_miss_latency::cpu.inst 58383000 # number of overall miss cycles
351system.cpu.l2cache.overall_miss_latency::cpu.data 19118000 # number of overall miss cycles
352system.cpu.l2cache.overall_miss_latency::total 77501000 # number of overall miss cycles
353system.cpu.l2cache.WritebackClean_accesses::writebacks 26 # number of WritebackClean accesses(hits+misses)
354system.cpu.l2cache.WritebackClean_accesses::total 26 # number of WritebackClean accesses(hits+misses)
355system.cpu.l2cache.ReadExReq_accesses::cpu.data 205 # number of ReadExReq accesses(hits+misses)
356system.cpu.l2cache.ReadExReq_accesses::total 205 # number of ReadExReq accesses(hits+misses)
357system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 965 # number of ReadCleanReq accesses(hits+misses)
358system.cpu.l2cache.ReadCleanReq_accesses::total 965 # number of ReadCleanReq accesses(hits+misses)
359system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 111 # number of ReadSharedReq accesses(hits+misses)
360system.cpu.l2cache.ReadSharedReq_accesses::total 111 # number of ReadSharedReq accesses(hits+misses)
361system.cpu.l2cache.demand_accesses::cpu.inst 965 # number of demand (read+write) accesses
362system.cpu.l2cache.demand_accesses::cpu.data 316 # number of demand (read+write) accesses
363system.cpu.l2cache.demand_accesses::total 1281 # number of demand (read+write) accesses
364system.cpu.l2cache.overall_accesses::cpu.inst 965 # number of overall (read+write) accesses
365system.cpu.l2cache.overall_accesses::cpu.data 316 # number of overall (read+write) accesses
366system.cpu.l2cache.overall_accesses::total 1281 # number of overall (read+write) accesses
367system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
368system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
369system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
370system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
371system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
372system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
373system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
374system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
375system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
376system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
377system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
378system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
379system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
380system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
381system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60500.518135 # average ReadCleanReq miss latency
382system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60500.518135 # average ReadCleanReq miss latency
383system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
384system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
385system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60500.518135 # average overall miss latency
386system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
387system.cpu.l2cache.demand_avg_miss_latency::total 60500.390320 # average overall miss latency
388system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60500.518135 # average overall miss latency
389system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
390system.cpu.l2cache.overall_avg_miss_latency::total 60500.390320 # average overall miss latency
391system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
392system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
393system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
394system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
395system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
396system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
397system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 205 # number of ReadExReq MSHR misses
398system.cpu.l2cache.ReadExReq_mshr_misses::total 205 # number of ReadExReq MSHR misses
399system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 965 # number of ReadCleanReq MSHR misses
400system.cpu.l2cache.ReadCleanReq_mshr_misses::total 965 # number of ReadCleanReq MSHR misses
401system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 111 # number of ReadSharedReq MSHR misses
402system.cpu.l2cache.ReadSharedReq_mshr_misses::total 111 # number of ReadSharedReq MSHR misses
403system.cpu.l2cache.demand_mshr_misses::cpu.inst 965 # number of demand (read+write) MSHR misses
404system.cpu.l2cache.demand_mshr_misses::cpu.data 316 # number of demand (read+write) MSHR misses
405system.cpu.l2cache.demand_mshr_misses::total 1281 # number of demand (read+write) MSHR misses
406system.cpu.l2cache.overall_mshr_misses::cpu.inst 965 # number of overall MSHR misses
407system.cpu.l2cache.overall_mshr_misses::cpu.data 316 # number of overall MSHR misses
408system.cpu.l2cache.overall_mshr_misses::total 1281 # number of overall MSHR misses
409system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10352500 # number of ReadExReq MSHR miss cycles
410system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10352500 # number of ReadExReq MSHR miss cycles
411system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 48733000 # number of ReadCleanReq MSHR miss cycles
412system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 48733000 # number of ReadCleanReq MSHR miss cycles
413system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5605500 # number of ReadSharedReq MSHR miss cycles
414system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5605500 # number of ReadSharedReq MSHR miss cycles
415system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48733000 # number of demand (read+write) MSHR miss cycles
416system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15958000 # number of demand (read+write) MSHR miss cycles
417system.cpu.l2cache.demand_mshr_miss_latency::total 64691000 # number of demand (read+write) MSHR miss cycles
418system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48733000 # number of overall MSHR miss cycles
419system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15958000 # number of overall MSHR miss cycles
420system.cpu.l2cache.overall_mshr_miss_latency::total 64691000 # number of overall MSHR miss cycles
421system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
422system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
423system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
424system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
425system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
426system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
427system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
428system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
429system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
430system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
431system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
432system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
433system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
434system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
435system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.518135 # average ReadCleanReq mshr miss latency
436system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.518135 # average ReadCleanReq mshr miss latency
437system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
438system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
439system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.518135 # average overall mshr miss latency
440system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
441system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.390320 # average overall mshr miss latency
442system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.518135 # average overall mshr miss latency
443system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
444system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.390320 # average overall mshr miss latency
445system.cpu.toL2Bus.snoop_filter.tot_requests 1307 # Total number of requests made to the snoop filter.
446system.cpu.toL2Bus.snoop_filter.hit_single_requests 26 # Number of requests hitting in the snoop filter with a single holder of the requested data.
447system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
448system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
449system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
450system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
451system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
452system.cpu.toL2Bus.trans_dist::ReadResp 1076 # Transaction distribution
453system.cpu.toL2Bus.trans_dist::WritebackClean 26 # Transaction distribution
454system.cpu.toL2Bus.trans_dist::ReadExReq 205 # Transaction distribution
455system.cpu.toL2Bus.trans_dist::ReadExResp 205 # Transaction distribution
456system.cpu.toL2Bus.trans_dist::ReadCleanReq 965 # Transaction distribution
457system.cpu.toL2Bus.trans_dist::ReadSharedReq 111 # Transaction distribution
458system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1956 # Packet count per connected master and slave (bytes)
459system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 632 # Packet count per connected master and slave (bytes)
460system.cpu.toL2Bus.pkt_count::total 2588 # Packet count per connected master and slave (bytes)
461system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63424 # Cumulative packet size per connected master and slave (bytes)
462system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 20224 # Cumulative packet size per connected master and slave (bytes)
463system.cpu.toL2Bus.pkt_size::total 83648 # Cumulative packet size per connected master and slave (bytes)
464system.cpu.toL2Bus.snoops 0 # Total snoops (count)
465system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
466system.cpu.toL2Bus.snoop_fanout::samples 1281 # Request fanout histogram
467system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
468system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
469system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
470system.cpu.toL2Bus.snoop_fanout::0 1281 100.00% 100.00% # Request fanout histogram
471system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
472system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
475system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::total 1281 # Request fanout histogram
477system.cpu.toL2Bus.reqLayer0.occupancy 679500 # Layer occupancy (ticks)
478system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
479system.cpu.toL2Bus.respLayer0.occupancy 1447500 # Layer occupancy (ticks)
480system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
481system.cpu.toL2Bus.respLayer1.occupancy 474000 # Layer occupancy (ticks)
482system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
483system.membus.snoop_filter.tot_requests 1281 # Total number of requests made to the snoop filter.
484system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
485system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
486system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
487system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
488system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
489system.membus.pwrStateResidencyTicks::UNDEFINED 497165500 # Cumulative time (in ticks) in various power states
490system.membus.trans_dist::ReadResp 1076 # Transaction distribution
491system.membus.trans_dist::ReadExReq 205 # Transaction distribution
492system.membus.trans_dist::ReadExResp 205 # Transaction distribution
493system.membus.trans_dist::ReadSharedReq 1076 # Transaction distribution
494system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2562 # Packet count per connected master and slave (bytes)
495system.membus.pkt_count::total 2562 # Packet count per connected master and slave (bytes)
496system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 81984 # Cumulative packet size per connected master and slave (bytes)
497system.membus.pkt_size::total 81984 # Cumulative packet size per connected master and slave (bytes)
498system.membus.snoops 0 # Total snoops (count)
499system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
500system.membus.snoop_fanout::samples 1281 # Request fanout histogram
501system.membus.snoop_fanout::mean 0 # Request fanout histogram
502system.membus.snoop_fanout::stdev 0 # Request fanout histogram
503system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
504system.membus.snoop_fanout::0 1281 100.00% 100.00% # Request fanout histogram
505system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
506system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
507system.membus.snoop_fanout::min_value 0 # Request fanout histogram
508system.membus.snoop_fanout::max_value 0 # Request fanout histogram
509system.membus.snoop_fanout::total 1281 # Request fanout histogram
510system.membus.reqLayer0.occupancy 1281500 # Layer occupancy (ticks)
511system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
512system.membus.respLayer1.occupancy 6405000 # Layer occupancy (ticks)
513system.membus.respLayer1.utilization 1.3 # Layer utilization (%)
| 3sim_seconds 0.000787
4sim_ticks 787032500
5final_tick 787032500
6sim_freq 1000000000000
7host_inst_rate 4249
8host_op_rate 4261
9host_tick_rate 7692847
10host_mem_usage 270044
11host_seconds 102.30
12sim_insts 434729
13sim_ops 436032
14system.voltage_domain.voltage 1
15system.clk_domain.clock 1000
16system.physmem.pwrStateResidencyTicks::UNDEFINED 787032500
17system.physmem.bytes_read::cpu.inst 68608
18system.physmem.bytes_read::cpu.data 34048
19system.physmem.bytes_read::total 102656
20system.physmem.bytes_inst_read::cpu.inst 68608
21system.physmem.bytes_inst_read::total 68608
22system.physmem.num_reads::cpu.inst 1072
23system.physmem.num_reads::cpu.data 532
24system.physmem.num_reads::total 1604
25system.physmem.bw_read::cpu.inst 87173020
26system.physmem.bw_read::cpu.data 43261237
27system.physmem.bw_read::total 130434257
28system.physmem.bw_inst_read::cpu.inst 87173020
29system.physmem.bw_inst_read::total 87173020
30system.physmem.bw_total::cpu.inst 87173020
31system.physmem.bw_total::cpu.data 43261237
32system.physmem.bw_total::total 130434257
33system.pwrStateResidencyTicks::UNDEFINED 787032500
34system.cpu_clk_domain.clock 500
35system.cpu.dtb.read_hits 0
36system.cpu.dtb.read_misses 0
37system.cpu.dtb.read_accesses 0
38system.cpu.dtb.write_hits 0
39system.cpu.dtb.write_misses 0
40system.cpu.dtb.write_accesses 0
41system.cpu.dtb.hits 0
42system.cpu.dtb.misses 0
43system.cpu.dtb.accesses 0
44system.cpu.itb.read_hits 0
45system.cpu.itb.read_misses 0
46system.cpu.itb.read_accesses 0
47system.cpu.itb.write_hits 0
48system.cpu.itb.write_misses 0
49system.cpu.itb.write_accesses 0
50system.cpu.itb.hits 0
51system.cpu.itb.misses 0
52system.cpu.itb.accesses 0
53system.cpu.workload.numSyscalls 220
54system.cpu.pwrStateResidencyTicks::ON 787032500
55system.cpu.numCycles 1574065
56system.cpu.numWorkItemsStarted 0
57system.cpu.numWorkItemsCompleted 0
58system.cpu.committedInsts 434729
59system.cpu.committedOps 436032
60system.cpu.num_int_alu_accesses 433908
61system.cpu.num_fp_alu_accesses 1229
62system.cpu.num_vec_alu_accesses 0
63system.cpu.num_func_calls 23870
64system.cpu.num_conditional_control_insts 71049
65system.cpu.num_int_insts 433908
66system.cpu.num_fp_insts 1229
67system.cpu.num_vec_insts 0
68system.cpu.num_int_register_reads 549660
69system.cpu.num_int_register_writes 288600
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430system.cpu.l2cache.overall_avg_miss_latency::total 60500.311720
431system.cpu.l2cache.blocked_cycles::no_mshrs 0
432system.cpu.l2cache.blocked_cycles::no_targets 0
433system.cpu.l2cache.blocked::no_mshrs 0
434system.cpu.l2cache.blocked::no_targets 0
435system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
436system.cpu.l2cache.avg_blocked_cycles::no_targets nan
437system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 228
438system.cpu.l2cache.ReadExReq_mshr_misses::total 228
439system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1072
440system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1072
441system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 304
442system.cpu.l2cache.ReadSharedReq_mshr_misses::total 304
443system.cpu.l2cache.demand_mshr_misses::cpu.inst 1072
444system.cpu.l2cache.demand_mshr_misses::cpu.data 532
445system.cpu.l2cache.demand_mshr_misses::total 1604
446system.cpu.l2cache.overall_mshr_misses::cpu.inst 1072
447system.cpu.l2cache.overall_mshr_misses::cpu.data 532
448system.cpu.l2cache.overall_mshr_misses::total 1604
449system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11514000
450system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11514000
451system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 54136500
452system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 54136500
453system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15352000
454system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15352000
455system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 54136500
456system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26866000
457system.cpu.l2cache.demand_mshr_miss_latency::total 81002500
458system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 54136500
459system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26866000
460system.cpu.l2cache.overall_mshr_miss_latency::total 81002500
461system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
462system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
463system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.999068
464system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.999068
465system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1
466system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1
467system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.999068
468system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1
469system.cpu.l2cache.demand_mshr_miss_rate::total 0.999376
470system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.999068
471system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
472system.cpu.l2cache.overall_mshr_miss_rate::total 0.999376
473system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500
474system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500
475system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50500.466417
476system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50500.466417
477system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500
478system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500
479system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50500.466417
480system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500
481system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.311720
482system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50500.466417
483system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500
484system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.311720
485system.cpu.toL2Bus.snoop_filter.tot_requests 1658
486system.cpu.toL2Bus.snoop_filter.hit_single_requests 53
487system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
488system.cpu.toL2Bus.snoop_filter.tot_snoops 0
489system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
490system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
491system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787032500
492system.cpu.toL2Bus.trans_dist::ReadResp 1377
493system.cpu.toL2Bus.trans_dist::WritebackDirty 1
494system.cpu.toL2Bus.trans_dist::WritebackClean 52
495system.cpu.toL2Bus.trans_dist::ReadExReq 228
496system.cpu.toL2Bus.trans_dist::ReadExResp 228
497system.cpu.toL2Bus.trans_dist::ReadCleanReq 1073
498system.cpu.toL2Bus.trans_dist::ReadSharedReq 304
499system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2198
500system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1065
501system.cpu.toL2Bus.pkt_count::total 3263
502system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72000
503system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 34112
504system.cpu.toL2Bus.pkt_size::total 106112
505system.cpu.toL2Bus.snoops 0
506system.cpu.toL2Bus.snoopTraffic 0
507system.cpu.toL2Bus.snoop_fanout::samples 1605
508system.cpu.toL2Bus.snoop_fanout::mean 0
509system.cpu.toL2Bus.snoop_fanout::stdev -0
510system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
511system.cpu.toL2Bus.snoop_fanout::0 1605 100.00% 100.00%
512system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
513system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
514system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
515system.cpu.toL2Bus.snoop_fanout::min_value 0
516system.cpu.toL2Bus.snoop_fanout::max_value 0
517system.cpu.toL2Bus.snoop_fanout::total 1605
518system.cpu.toL2Bus.reqLayer0.occupancy 882000
519system.cpu.toL2Bus.reqLayer0.utilization 0.1
520system.cpu.toL2Bus.respLayer0.occupancy 1609500
521system.cpu.toL2Bus.respLayer0.utilization 0.2
522system.cpu.toL2Bus.respLayer1.occupancy 798000
523system.cpu.toL2Bus.respLayer1.utilization 0.1
524system.membus.snoop_filter.tot_requests 1604
525system.membus.snoop_filter.hit_single_requests 0
526system.membus.snoop_filter.hit_multi_requests 0
527system.membus.snoop_filter.tot_snoops 0
528system.membus.snoop_filter.hit_single_snoops 0
529system.membus.snoop_filter.hit_multi_snoops 0
530system.membus.pwrStateResidencyTicks::UNDEFINED 787032500
531system.membus.trans_dist::ReadResp 1376
532system.membus.trans_dist::ReadExReq 228
533system.membus.trans_dist::ReadExResp 228
534system.membus.trans_dist::ReadSharedReq 1376
535system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3208
536system.membus.pkt_count::total 3208
537system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 102656
538system.membus.pkt_size::total 102656
539system.membus.snoops 0
540system.membus.snoopTraffic 0
541system.membus.snoop_fanout::samples 1604
542system.membus.snoop_fanout::mean 0
543system.membus.snoop_fanout::stdev -0
544system.membus.snoop_fanout::underflows 0 0.00% 0.00%
545system.membus.snoop_fanout::0 1604 100.00% 100.00%
546system.membus.snoop_fanout::1 0 0.00% 100.00%
547system.membus.snoop_fanout::overflows 0 0.00% 100.00%
548system.membus.snoop_fanout::min_value 0
549system.membus.snoop_fanout::max_value 0
550system.membus.snoop_fanout::total 1604
551system.membus.reqLayer0.occupancy 1604500
552system.membus.reqLayer0.utilization 0.2
553system.membus.respLayer1.occupancy 8020000
554system.membus.respLayer1.utilization 1.0
|
514
515---------- End Simulation Statistics ----------
| 555
556---------- End Simulation Statistics ----------
|