1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000497 # Number of seconds simulated 4sim_ticks 497165500 # Number of ticks simulated 5final_tick 497165500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 27513 # Simulator instruction rate (inst/s) 8host_op_rate 27513 # Simulator op (including micro ops) rate (op/s) --- 36 unchanged lines hidden (view full) --- 45system.cpu.itb.read_misses 0 # DTB read misses 46system.cpu.itb.read_accesses 0 # DTB read accesses 47system.cpu.itb.write_hits 0 # DTB write hits 48system.cpu.itb.write_misses 0 # DTB write misses 49system.cpu.itb.write_accesses 0 # DTB write accesses 50system.cpu.itb.hits 0 # DTB hits 51system.cpu.itb.misses 0 # DTB misses 52system.cpu.itb.accesses 0 # DTB accesses |
53system.cpu.workload.numSyscalls 162 # Number of system calls |
54system.cpu.pwrStateResidencyTicks::ON 497165500 # Cumulative time (in ticks) in various power states 55system.cpu.numCycles 994331 # number of cpu cycles simulated 56system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 57system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 58system.cpu.committedInsts 299191 # Number of instructions committed 59system.cpu.committedOps 299191 # Number of ops (including micro ops) committed 60system.cpu.num_int_alu_accesses 299008 # Number of integer alu accesses 61system.cpu.num_fp_alu_accesses 1025 # Number of float alu accesses --- 454 unchanged lines hidden --- |