| stats.txt (11731:c473ca7cc650) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000339 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000339 # Number of seconds simulated |
| 4sim_ticks 339160000 # Number of ticks simulated 5final_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 339173000 # Number of ticks simulated 5final_tick 339173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 25032 # Simulator instruction rate (inst/s) 8host_op_rate 25032 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 28360795 # Simulator tick rate (ticks/s) 10host_mem_usage 244952 # Number of bytes of host memory used 11host_seconds 11.96 # Real time elapsed on the host | 7host_inst_rate 215547 # Simulator instruction rate (inst/s) 8host_op_rate 215545 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 244214530 # Simulator tick rate (ticks/s) 10host_mem_usage 263004 # Number of bytes of host memory used 11host_seconds 1.39 # Real time elapsed on the host |
| 12sim_insts 299354 # Number of instructions simulated 13sim_ops 299354 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 299354 # Number of instructions simulated 13sim_ops 299354 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory 19system.physmem.bytes_read::total 95040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 74688 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 74688 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 74688 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 20352 # Number of bytes read from this memory 19system.physmem.bytes_read::total 95040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 74688 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 74688 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 1167 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 318 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 1485 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 220206207 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 60004776 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 280210984 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 220206207 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 220206207 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 220206207 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 60004776 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 280210984 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 1485 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 95040 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 95040 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 1485 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 1485 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 95040 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 95040 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 338943500 # Total gap between requests | 79system.physmem.totGap 338956500 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 1485 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 96 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 1485 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) --- 96 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 285 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 327.859649 # Bytes accessed per row activation |
| 192system.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation | 192system.physmem.bytesPerActivate::gmean 221.082687 # Bytes accessed per row activation |
| 193system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation | 193system.physmem.bytesPerActivate::stdev 283.652997 # Bytes accessed per row activation |
| 194system.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation | 194system.physmem.bytesPerActivate::0-127 68 23.86% 23.86% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 71 24.91% 48.77% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 38 13.33% 62.11% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 36 12.63% 74.74% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 28 9.82% 84.56% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 14 4.91% 89.47% # Bytes accessed per row activation |
| 200system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation | 200system.physmem.bytesPerActivate::768-895 7 2.46% 91.93% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 2 0.70% 92.63% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 21 7.37% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 285 # Bytes accessed per row activation |
| 204system.physmem.totQLat 19805250 # Total ticks spent queuing 205system.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM | 204system.physmem.totQLat 20061750 # Total ticks spent queuing 205system.physmem.totMemAccLat 47905500 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 7425000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 13509.60 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 32259.60 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 280.21 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 280.21 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 2.19 # Data bus utilization in percentage 216system.physmem.busUtilRead 2.19 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 1195 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 2.19 # Data bus utilization in percentage 216system.physmem.busUtilRead 2.19 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 1195 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 80.47 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 228244.78 # Average gap between requests | 224system.physmem.avgGap 228253.54 # Average gap between requests |
| 225system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) | 225system.physmem.pageHitRate 80.47 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 1106700 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 576840 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 6368880 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ) | 231system.physmem_0.actBackEnergy 16018710 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 699840 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 123298980 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 12114720 # Energy for precharge power-down per rank (pJ) |
| 235system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ) | 235system.physmem_0.selfRefreshEnergy 619740.000000 # Energy for self refresh per rank (pJ) |
| 236system.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ) 237system.physmem_0.averagePower 553.629673 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states | 236system.physmem_0.totalEnergy 187848570 # Total energy per rank (pJ) 237system.physmem_0.averagePower 553.841711 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 301380500 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 552000 # Time in different power states |
| 240system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states | 240system.physmem_0.memoryStateTime::REF 11446000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 280750 # Time in different power states |
| 242system.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states | 242system.physmem_0.memoryStateTime::PRE_PDN 31555500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 24953750 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 270385000 # Time in different power states |
| 245system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) | 245system.physmem_1.actEnergy 963900 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 504735 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 4234020 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 27044160.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ) | 250system.physmem_1.actBackEnergy 12906510 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 3648480 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 105703080 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 26147040 # Energy for precharge power-down per rank (pJ) |
| 254system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ) | 254system.physmem_1.selfRefreshEnergy 905640.000000 # Energy for self refresh per rank (pJ) |
| 255system.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ) 256system.physmem_1.averagePower 537.082660 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states | 255system.physmem_1.totalEnergy 182057565 # Total energy per rank (pJ) 256system.physmem_1.averagePower 536.767851 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 301140750 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 8284250 # Time in different power states |
| 259system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states | 259system.physmem_1.memoryStateTime::REF 11446000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 1471750 # Time in different power states |
| 261system.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 80709 # Number of BP lookups 266system.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 38294 # Number of BTB hits | 261system.physmem_1.memoryStateTime::PRE_PDN 68075000 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 18122250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 231773750 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 80662 # Number of BP lookups 266system.cpu.branchPred.condPredicted 51937 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 5790 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 60622 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 38260 # Number of BTB hits |
| 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 271system.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage | 271system.cpu.branchPred.BTBHitPct 63.112401 # BTB Hit Percentage |
| 272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. | 272system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. |
| 274system.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 7506 # Number of indirect target hits. | 274system.cpu.branchPred.indirectLookups 13147 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 7489 # Number of indirect target hits. |
| 276system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses --- 6 unchanged lines hidden (view full) --- 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 162 # Number of system calls | 276system.cpu.branchPred.indirectMisses 5658 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 3210 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses --- 6 unchanged lines hidden (view full) --- 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 162 # Number of system calls |
| 298system.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 678320 # number of cpu cycles simulated | 298system.cpu.pwrStateResidencyTicks::ON 339173000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 678346 # number of cpu cycles simulated |
| 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.committedInsts 299354 # Number of instructions committed 303system.cpu.committedOps 299354 # Number of ops (including micro ops) committed | 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 302system.cpu.committedInsts 299354 # Number of instructions committed 303system.cpu.committedOps 299354 # Number of ops (including micro ops) committed |
| 304system.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit | 304system.cpu.discardedOps 13899 # Number of ops (including micro ops) which were discarded before commit |
| 305system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 305system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 306system.cpu.cpi 2.265946 # CPI: cycles per instruction 307system.cpu.ipc 0.441317 # IPC: instructions per cycle | 306system.cpu.cpi 2.266033 # CPI: cycles per instruction 307system.cpu.ipc 0.441300 # IPC: instructions per cycle |
| 308system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction 309system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction 310system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction 311system.cpu.op_class_0::IntDiv 40 0.01% 60.32% # Class of committed instruction 312system.cpu.op_class_0::FloatAdd 120 0.04% 60.36% # Class of committed instruction 313system.cpu.op_class_0::FloatCmp 157 0.05% 60.42% # Class of committed instruction 314system.cpu.op_class_0::FloatCvt 60 0.02% 60.44% # Class of committed instruction 315system.cpu.op_class_0::FloatMult 30 0.01% 60.45% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.45% # Class of committed instruction 340system.cpu.op_class_0::MemRead 69348 23.17% 83.62% # Class of committed instruction 341system.cpu.op_class_0::MemWrite 48400 16.17% 99.79% # Class of committed instruction 342system.cpu.op_class_0::FloatMemRead 495 0.17% 99.95% # Class of committed instruction 343system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 299354 # Class of committed instruction | 308system.cpu.op_class_0::No_OpClass 162 0.05% 0.05% # Class of committed instruction 309system.cpu.op_class_0::IntAlu 179913 60.10% 60.15% # Class of committed instruction 310system.cpu.op_class_0::IntMult 466 0.16% 60.31% # Class of committed instruction 311system.cpu.op_class_0::IntDiv 40 0.01% 60.32% # Class of committed instruction 312system.cpu.op_class_0::FloatAdd 120 0.04% 60.36% # Class of committed instruction 313system.cpu.op_class_0::FloatCmp 157 0.05% 60.42% # Class of committed instruction 314system.cpu.op_class_0::FloatCvt 60 0.02% 60.44% # Class of committed instruction 315system.cpu.op_class_0::FloatMult 30 0.01% 60.45% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 339system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 60.45% # Class of committed instruction 340system.cpu.op_class_0::MemRead 69348 23.17% 83.62% # Class of committed instruction 341system.cpu.op_class_0::MemWrite 48400 16.17% 99.79% # Class of committed instruction 342system.cpu.op_class_0::FloatMemRead 495 0.17% 99.95% # Class of committed instruction 343system.cpu.op_class_0::FloatMemWrite 147 0.05% 100.00% # Class of committed instruction 344system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 345system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 346system.cpu.op_class_0::total 299354 # Class of committed instruction |
| 347system.cpu.tickCycles 449536 # Number of cycles that the object actually ticked 348system.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states | 347system.cpu.tickCycles 449143 # Number of cycles that the object actually ticked 348system.cpu.idleCycles 229203 # Total number of cycles that the object has spent stopped 349system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states |
| 350system.cpu.dcache.tags.replacements 0 # number of replacements | 350system.cpu.dcache.tags.replacements 0 # number of replacements |
| 351system.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks. | 351system.cpu.dcache.tags.tagsinuse 254.242270 # Cycle average of tags in use 352system.cpu.dcache.tags.total_refs 119892 # Total number of references to valid blocks. |
| 353system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks. | 353system.cpu.dcache.tags.sampled_refs 320 # Sample count of references to valid blocks. |
| 354system.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks. | 354system.cpu.dcache.tags.avg_refs 374.662500 # Average number of references to valid blocks. |
| 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 355system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 356system.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy | 356system.cpu.dcache.tags.occ_blocks::cpu.data 254.242270 # Average occupied blocks per requestor 357system.cpu.dcache.tags.occ_percent::cpu.data 0.062071 # Average percentage of cache occupancy 358system.cpu.dcache.tags.occ_percent::total 0.062071 # Average percentage of cache occupancy |
| 359system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 362system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 363system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id | 359system.cpu.dcache.tags.occ_task_id_blocks::1024 320 # Occupied blocks per task id 360system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 361system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id 362system.cpu.dcache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 363system.cpu.dcache.tags.occ_task_id_percent::1024 0.078125 # Percentage of cache occupancy per task id |
| 364system.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses 365system.cpu.dcache.tags.data_accesses 241156 # Number of data accesses 366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 367system.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits 368system.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits | 364system.cpu.dcache.tags.tag_accesses 241126 # Number of tag accesses 365system.cpu.dcache.tags.data_accesses 241126 # Number of data accesses 366system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states 367system.cpu.dcache.ReadReq_hits::cpu.data 71739 # number of ReadReq hits 368system.cpu.dcache.ReadReq_hits::total 71739 # number of ReadReq hits |
| 369system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits 370system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits | 369system.cpu.dcache.WriteReq_hits::cpu.data 48153 # number of WriteReq hits 370system.cpu.dcache.WriteReq_hits::total 48153 # number of WriteReq hits |
| 371system.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits 372system.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits 373system.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits 374system.cpu.dcache.overall_hits::total 119907 # number of overall hits | 371system.cpu.dcache.demand_hits::cpu.data 119892 # number of demand (read+write) hits 372system.cpu.dcache.demand_hits::total 119892 # number of demand (read+write) hits 373system.cpu.dcache.overall_hits::cpu.data 119892 # number of overall hits 374system.cpu.dcache.overall_hits::total 119892 # number of overall hits |
| 375system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses 376system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses 377system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses 378system.cpu.dcache.WriteReq_misses::total 393 # number of WriteReq misses 379system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses 380system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses 381system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses 382system.cpu.dcache.overall_misses::total 511 # number of overall misses | 375system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses 376system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses 377system.cpu.dcache.WriteReq_misses::cpu.data 393 # number of WriteReq misses 378system.cpu.dcache.WriteReq_misses::total 393 # number of WriteReq misses 379system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses 380system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses 381system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses 382system.cpu.dcache.overall_misses::total 511 # number of overall misses |
| 383system.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles 384system.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles | 383system.cpu.dcache.ReadReq_miss_latency::cpu.data 10980000 # number of ReadReq miss cycles 384system.cpu.dcache.ReadReq_miss_latency::total 10980000 # number of ReadReq miss cycles |
| 385system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles 386system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles | 385system.cpu.dcache.WriteReq_miss_latency::cpu.data 31520500 # number of WriteReq miss cycles 386system.cpu.dcache.WriteReq_miss_latency::total 31520500 # number of WriteReq miss cycles |
| 387system.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles 388system.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles 389system.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles 390system.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles 391system.cpu.dcache.ReadReq_accesses::cpu.data 71872 # number of ReadReq accesses(hits+misses) 392system.cpu.dcache.ReadReq_accesses::total 71872 # number of ReadReq accesses(hits+misses) | 387system.cpu.dcache.demand_miss_latency::cpu.data 42500500 # number of demand (read+write) miss cycles 388system.cpu.dcache.demand_miss_latency::total 42500500 # number of demand (read+write) miss cycles 389system.cpu.dcache.overall_miss_latency::cpu.data 42500500 # number of overall miss cycles 390system.cpu.dcache.overall_miss_latency::total 42500500 # number of overall miss cycles 391system.cpu.dcache.ReadReq_accesses::cpu.data 71857 # number of ReadReq accesses(hits+misses) 392system.cpu.dcache.ReadReq_accesses::total 71857 # number of ReadReq accesses(hits+misses) |
| 393system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) 394system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) | 393system.cpu.dcache.WriteReq_accesses::cpu.data 48546 # number of WriteReq accesses(hits+misses) 394system.cpu.dcache.WriteReq_accesses::total 48546 # number of WriteReq accesses(hits+misses) |
| 395system.cpu.dcache.demand_accesses::cpu.data 120418 # number of demand (read+write) accesses 396system.cpu.dcache.demand_accesses::total 120418 # number of demand (read+write) accesses 397system.cpu.dcache.overall_accesses::cpu.data 120418 # number of overall (read+write) accesses 398system.cpu.dcache.overall_accesses::total 120418 # number of overall (read+write) accesses | 395system.cpu.dcache.demand_accesses::cpu.data 120403 # number of demand (read+write) accesses 396system.cpu.dcache.demand_accesses::total 120403 # number of demand (read+write) accesses 397system.cpu.dcache.overall_accesses::cpu.data 120403 # number of overall (read+write) accesses 398system.cpu.dcache.overall_accesses::total 120403 # number of overall (read+write) accesses |
| 399system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses 400system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses 401system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses 402system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses 403system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 # miss rate for demand accesses 404system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses 405system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses 406system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses | 399system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001642 # miss rate for ReadReq accesses 400system.cpu.dcache.ReadReq_miss_rate::total 0.001642 # miss rate for ReadReq accesses 401system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008095 # miss rate for WriteReq accesses 402system.cpu.dcache.WriteReq_miss_rate::total 0.008095 # miss rate for WriteReq accesses 403system.cpu.dcache.demand_miss_rate::cpu.data 0.004244 # miss rate for demand accesses 404system.cpu.dcache.demand_miss_rate::total 0.004244 # miss rate for demand accesses 405system.cpu.dcache.overall_miss_rate::cpu.data 0.004244 # miss rate for overall accesses 406system.cpu.dcache.overall_miss_rate::total 0.004244 # miss rate for overall accesses |
| 407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency 408system.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency | 407system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93050.847458 # average ReadReq miss latency 408system.cpu.dcache.ReadReq_avg_miss_latency::total 93050.847458 # average ReadReq miss latency |
| 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency 410system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency | 409system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80204.834606 # average WriteReq miss latency 410system.cpu.dcache.WriteReq_avg_miss_latency::total 80204.834606 # average WriteReq miss latency |
| 411system.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency 412system.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency 414system.cpu.dcache.overall_avg_miss_latency::total 83137.964775 # average overall miss latency | 411system.cpu.dcache.demand_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency 412system.cpu.dcache.demand_avg_miss_latency::total 83171.232877 # average overall miss latency 413system.cpu.dcache.overall_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency 414system.cpu.dcache.overall_avg_miss_latency::total 83171.232877 # average overall miss latency |
| 415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits 422system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits --- 4 unchanged lines hidden (view full) --- 427system.cpu.dcache.ReadReq_mshr_misses::cpu.data 118 # number of ReadReq MSHR misses 428system.cpu.dcache.ReadReq_mshr_misses::total 118 # number of ReadReq MSHR misses 429system.cpu.dcache.WriteReq_mshr_misses::cpu.data 202 # number of WriteReq MSHR misses 430system.cpu.dcache.WriteReq_mshr_misses::total 202 # number of WriteReq MSHR misses 431system.cpu.dcache.demand_mshr_misses::cpu.data 320 # number of demand (read+write) MSHR misses 432system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses 433system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses 434system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses | 415system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 416system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 418system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 420system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.cpu.dcache.WriteReq_mshr_hits::cpu.data 191 # number of WriteReq MSHR hits 422system.cpu.dcache.WriteReq_mshr_hits::total 191 # number of WriteReq MSHR hits --- 4 unchanged lines hidden (view full) --- 427system.cpu.dcache.ReadReq_mshr_misses::cpu.data 118 # number of ReadReq MSHR misses 428system.cpu.dcache.ReadReq_mshr_misses::total 118 # number of ReadReq MSHR misses 429system.cpu.dcache.WriteReq_mshr_misses::cpu.data 202 # number of WriteReq MSHR misses 430system.cpu.dcache.WriteReq_mshr_misses::total 202 # number of WriteReq MSHR misses 431system.cpu.dcache.demand_mshr_misses::cpu.data 320 # number of demand (read+write) MSHR misses 432system.cpu.dcache.demand_mshr_misses::total 320 # number of demand (read+write) MSHR misses 433system.cpu.dcache.overall_mshr_misses::cpu.data 320 # number of overall MSHR misses 434system.cpu.dcache.overall_mshr_misses::total 320 # number of overall MSHR misses |
| 435system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10845000 # number of ReadReq MSHR miss cycles 436system.cpu.dcache.ReadReq_mshr_miss_latency::total 10845000 # number of ReadReq MSHR miss cycles | 435system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862000 # number of ReadReq MSHR miss cycles 436system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862000 # number of ReadReq MSHR miss cycles |
| 437system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles 438system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles | 437system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 16122000 # number of WriteReq MSHR miss cycles 438system.cpu.dcache.WriteReq_mshr_miss_latency::total 16122000 # number of WriteReq MSHR miss cycles |
| 439system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26967000 # number of demand (read+write) MSHR miss cycles 440system.cpu.dcache.demand_mshr_miss_latency::total 26967000 # number of demand (read+write) MSHR miss cycles 441system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26967000 # number of overall MSHR miss cycles 442system.cpu.dcache.overall_mshr_miss_latency::total 26967000 # number of overall MSHR miss cycles | 439system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26984000 # number of demand (read+write) MSHR miss cycles 440system.cpu.dcache.demand_mshr_miss_latency::total 26984000 # number of demand (read+write) MSHR miss cycles 441system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26984000 # number of overall MSHR miss cycles 442system.cpu.dcache.overall_mshr_miss_latency::total 26984000 # number of overall MSHR miss cycles |
| 443system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses 444system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses 445system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses 446system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses | 443system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001642 # mshr miss rate for ReadReq accesses 444system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001642 # mshr miss rate for ReadReq accesses 445system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004161 # mshr miss rate for WriteReq accesses 446system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004161 # mshr miss rate for WriteReq accesses |
| 447system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for demand accesses 448system.cpu.dcache.demand_mshr_miss_rate::total 0.002657 # mshr miss rate for demand accesses 449system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for overall accesses 450system.cpu.dcache.overall_mshr_miss_rate::total 0.002657 # mshr miss rate for overall accesses 451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91906.779661 # average ReadReq mshr miss latency 452system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91906.779661 # average ReadReq mshr miss latency | 447system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for demand accesses 448system.cpu.dcache.demand_mshr_miss_rate::total 0.002658 # mshr miss rate for demand accesses 449system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for overall accesses 450system.cpu.dcache.overall_mshr_miss_rate::total 0.002658 # mshr miss rate for overall accesses 451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92050.847458 # average ReadReq mshr miss latency 452system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92050.847458 # average ReadReq mshr miss latency |
| 453system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency 454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency | 453system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79811.881188 # average WriteReq mshr miss latency 454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79811.881188 # average WriteReq mshr miss latency |
| 455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency 456system.cpu.dcache.demand_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency 457system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency 458system.cpu.dcache.overall_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency 459system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states | 455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency 456system.cpu.dcache.demand_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency 457system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency 458system.cpu.dcache.overall_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency 459system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states |
| 460system.cpu.icache.tags.replacements 80 # number of replacements | 460system.cpu.icache.tags.replacements 80 # number of replacements |
| 461system.cpu.icache.tags.tagsinuse 640.869470 # Cycle average of tags in use 462system.cpu.icache.tags.total_refs 135081 # Total number of references to valid blocks. | 461system.cpu.icache.tags.tagsinuse 641.197715 # Cycle average of tags in use 462system.cpu.icache.tags.total_refs 134928 # Total number of references to valid blocks. |
| 463system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks. | 463system.cpu.icache.tags.sampled_refs 1178 # Sample count of references to valid blocks. |
| 464system.cpu.icache.tags.avg_refs 114.669779 # Average number of references to valid blocks. | 464system.cpu.icache.tags.avg_refs 114.539898 # Average number of references to valid blocks. |
| 465system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 465system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 466system.cpu.icache.tags.occ_blocks::cpu.inst 640.869470 # Average occupied blocks per requestor 467system.cpu.icache.tags.occ_percent::cpu.inst 0.312925 # Average percentage of cache occupancy 468system.cpu.icache.tags.occ_percent::total 0.312925 # Average percentage of cache occupancy | 466system.cpu.icache.tags.occ_blocks::cpu.inst 641.197715 # Average occupied blocks per requestor 467system.cpu.icache.tags.occ_percent::cpu.inst 0.313085 # Average percentage of cache occupancy 468system.cpu.icache.tags.occ_percent::total 0.313085 # Average percentage of cache occupancy |
| 469system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id 470system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 471system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 472system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id 473system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id | 469system.cpu.icache.tags.occ_task_id_blocks::1024 1098 # Occupied blocks per task id 470system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id 471system.cpu.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id 472system.cpu.icache.tags.age_task_id_blocks_1024::2 846 # Occupied blocks per task id 473system.cpu.icache.tags.occ_task_id_percent::1024 0.536133 # Percentage of cache occupancy per task id |
| 474system.cpu.icache.tags.tag_accesses 273696 # Number of tag accesses 475system.cpu.icache.tags.data_accesses 273696 # Number of data accesses 476system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states 477system.cpu.icache.ReadReq_hits::cpu.inst 135081 # number of ReadReq hits 478system.cpu.icache.ReadReq_hits::total 135081 # number of ReadReq hits 479system.cpu.icache.demand_hits::cpu.inst 135081 # number of demand (read+write) hits 480system.cpu.icache.demand_hits::total 135081 # number of demand (read+write) hits 481system.cpu.icache.overall_hits::cpu.inst 135081 # number of overall hits 482system.cpu.icache.overall_hits::total 135081 # number of overall hits | 474system.cpu.icache.tags.tag_accesses 273390 # Number of tag accesses 475system.cpu.icache.tags.data_accesses 273390 # Number of data accesses 476system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states 477system.cpu.icache.ReadReq_hits::cpu.inst 134928 # number of ReadReq hits 478system.cpu.icache.ReadReq_hits::total 134928 # number of ReadReq hits 479system.cpu.icache.demand_hits::cpu.inst 134928 # number of demand (read+write) hits 480system.cpu.icache.demand_hits::total 134928 # number of demand (read+write) hits 481system.cpu.icache.overall_hits::cpu.inst 134928 # number of overall hits 482system.cpu.icache.overall_hits::total 134928 # number of overall hits |
| 483system.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses 484system.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses 485system.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses 486system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses 487system.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses 488system.cpu.icache.overall_misses::total 1178 # number of overall misses | 483system.cpu.icache.ReadReq_misses::cpu.inst 1178 # number of ReadReq misses 484system.cpu.icache.ReadReq_misses::total 1178 # number of ReadReq misses 485system.cpu.icache.demand_misses::cpu.inst 1178 # number of demand (read+write) misses 486system.cpu.icache.demand_misses::total 1178 # number of demand (read+write) misses 487system.cpu.icache.overall_misses::cpu.inst 1178 # number of overall misses 488system.cpu.icache.overall_misses::total 1178 # number of overall misses |
| 489system.cpu.icache.ReadReq_miss_latency::cpu.inst 99945500 # number of ReadReq miss cycles 490system.cpu.icache.ReadReq_miss_latency::total 99945500 # number of ReadReq miss cycles 491system.cpu.icache.demand_miss_latency::cpu.inst 99945500 # number of demand (read+write) miss cycles 492system.cpu.icache.demand_miss_latency::total 99945500 # number of demand (read+write) miss cycles 493system.cpu.icache.overall_miss_latency::cpu.inst 99945500 # number of overall miss cycles 494system.cpu.icache.overall_miss_latency::total 99945500 # number of overall miss cycles 495system.cpu.icache.ReadReq_accesses::cpu.inst 136259 # number of ReadReq accesses(hits+misses) 496system.cpu.icache.ReadReq_accesses::total 136259 # number of ReadReq accesses(hits+misses) 497system.cpu.icache.demand_accesses::cpu.inst 136259 # number of demand (read+write) accesses 498system.cpu.icache.demand_accesses::total 136259 # number of demand (read+write) accesses 499system.cpu.icache.overall_accesses::cpu.inst 136259 # number of overall (read+write) accesses 500system.cpu.icache.overall_accesses::total 136259 # number of overall (read+write) accesses 501system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008645 # miss rate for ReadReq accesses 502system.cpu.icache.ReadReq_miss_rate::total 0.008645 # miss rate for ReadReq accesses 503system.cpu.icache.demand_miss_rate::cpu.inst 0.008645 # miss rate for demand accesses 504system.cpu.icache.demand_miss_rate::total 0.008645 # miss rate for demand accesses 505system.cpu.icache.overall_miss_rate::cpu.inst 0.008645 # miss rate for overall accesses 506system.cpu.icache.overall_miss_rate::total 0.008645 # miss rate for overall accesses 507system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84843.378608 # average ReadReq miss latency 508system.cpu.icache.ReadReq_avg_miss_latency::total 84843.378608 # average ReadReq miss latency 509system.cpu.icache.demand_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency 510system.cpu.icache.demand_avg_miss_latency::total 84843.378608 # average overall miss latency 511system.cpu.icache.overall_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency 512system.cpu.icache.overall_avg_miss_latency::total 84843.378608 # average overall miss latency | 489system.cpu.icache.ReadReq_miss_latency::cpu.inst 100185000 # number of ReadReq miss cycles 490system.cpu.icache.ReadReq_miss_latency::total 100185000 # number of ReadReq miss cycles 491system.cpu.icache.demand_miss_latency::cpu.inst 100185000 # number of demand (read+write) miss cycles 492system.cpu.icache.demand_miss_latency::total 100185000 # number of demand (read+write) miss cycles 493system.cpu.icache.overall_miss_latency::cpu.inst 100185000 # number of overall miss cycles 494system.cpu.icache.overall_miss_latency::total 100185000 # number of overall miss cycles 495system.cpu.icache.ReadReq_accesses::cpu.inst 136106 # number of ReadReq accesses(hits+misses) 496system.cpu.icache.ReadReq_accesses::total 136106 # number of ReadReq accesses(hits+misses) 497system.cpu.icache.demand_accesses::cpu.inst 136106 # number of demand (read+write) accesses 498system.cpu.icache.demand_accesses::total 136106 # number of demand (read+write) accesses 499system.cpu.icache.overall_accesses::cpu.inst 136106 # number of overall (read+write) accesses 500system.cpu.icache.overall_accesses::total 136106 # number of overall (read+write) accesses 501system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008655 # miss rate for ReadReq accesses 502system.cpu.icache.ReadReq_miss_rate::total 0.008655 # miss rate for ReadReq accesses 503system.cpu.icache.demand_miss_rate::cpu.inst 0.008655 # miss rate for demand accesses 504system.cpu.icache.demand_miss_rate::total 0.008655 # miss rate for demand accesses 505system.cpu.icache.overall_miss_rate::cpu.inst 0.008655 # miss rate for overall accesses 506system.cpu.icache.overall_miss_rate::total 0.008655 # miss rate for overall accesses 507system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85046.689304 # average ReadReq miss latency 508system.cpu.icache.ReadReq_avg_miss_latency::total 85046.689304 # average ReadReq miss latency 509system.cpu.icache.demand_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency 510system.cpu.icache.demand_avg_miss_latency::total 85046.689304 # average overall miss latency 511system.cpu.icache.overall_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency 512system.cpu.icache.overall_avg_miss_latency::total 85046.689304 # average overall miss latency |
| 513system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 517system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 518system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 519system.cpu.icache.writebacks::writebacks 80 # number of writebacks 520system.cpu.icache.writebacks::total 80 # number of writebacks 521system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1178 # number of ReadReq MSHR misses 522system.cpu.icache.ReadReq_mshr_misses::total 1178 # number of ReadReq MSHR misses 523system.cpu.icache.demand_mshr_misses::cpu.inst 1178 # number of demand (read+write) MSHR misses 524system.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses 525system.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses 526system.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses | 513system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 517system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 518system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 519system.cpu.icache.writebacks::writebacks 80 # number of writebacks 520system.cpu.icache.writebacks::total 80 # number of writebacks 521system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1178 # number of ReadReq MSHR misses 522system.cpu.icache.ReadReq_mshr_misses::total 1178 # number of ReadReq MSHR misses 523system.cpu.icache.demand_mshr_misses::cpu.inst 1178 # number of demand (read+write) MSHR misses 524system.cpu.icache.demand_mshr_misses::total 1178 # number of demand (read+write) MSHR misses 525system.cpu.icache.overall_mshr_misses::cpu.inst 1178 # number of overall MSHR misses 526system.cpu.icache.overall_mshr_misses::total 1178 # number of overall MSHR misses |
| 527system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 98767500 # number of ReadReq MSHR miss cycles 528system.cpu.icache.ReadReq_mshr_miss_latency::total 98767500 # number of ReadReq MSHR miss cycles 529system.cpu.icache.demand_mshr_miss_latency::cpu.inst 98767500 # number of demand (read+write) MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::total 98767500 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.overall_mshr_miss_latency::cpu.inst 98767500 # number of overall MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::total 98767500 # number of overall MSHR miss cycles 533system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for ReadReq accesses 534system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008645 # mshr miss rate for ReadReq accesses 535system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for demand accesses 536system.cpu.icache.demand_mshr_miss_rate::total 0.008645 # mshr miss rate for demand accesses 537system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for overall accesses 538system.cpu.icache.overall_mshr_miss_rate::total 0.008645 # mshr miss rate for overall accesses 539system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.378608 # average ReadReq mshr miss latency 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.378608 # average ReadReq mshr miss latency 541system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency 543system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency 545system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states | 527system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 99007000 # number of ReadReq MSHR miss cycles 528system.cpu.icache.ReadReq_mshr_miss_latency::total 99007000 # number of ReadReq MSHR miss cycles 529system.cpu.icache.demand_mshr_miss_latency::cpu.inst 99007000 # number of demand (read+write) MSHR miss cycles 530system.cpu.icache.demand_mshr_miss_latency::total 99007000 # number of demand (read+write) MSHR miss cycles 531system.cpu.icache.overall_mshr_miss_latency::cpu.inst 99007000 # number of overall MSHR miss cycles 532system.cpu.icache.overall_mshr_miss_latency::total 99007000 # number of overall MSHR miss cycles 533system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for ReadReq accesses 534system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008655 # mshr miss rate for ReadReq accesses 535system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for demand accesses 536system.cpu.icache.demand_mshr_miss_rate::total 0.008655 # mshr miss rate for demand accesses 537system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for overall accesses 538system.cpu.icache.overall_mshr_miss_rate::total 0.008655 # mshr miss rate for overall accesses 539system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84046.689304 # average ReadReq mshr miss latency 540system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84046.689304 # average ReadReq mshr miss latency 541system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency 542system.cpu.icache.demand_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency 543system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency 544system.cpu.icache.overall_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency 545system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states |
| 546system.cpu.l2cache.tags.replacements 0 # number of replacements | 546system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 547system.cpu.l2cache.tags.tagsinuse 923.863116 # Cycle average of tags in use | 547system.cpu.l2cache.tags.tagsinuse 924.252410 # Cycle average of tags in use |
| 548system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks. 549system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks. 550system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks. 551system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 548system.cpu.l2cache.tags.total_refs 93 # Total number of references to valid blocks. 549system.cpu.l2cache.tags.sampled_refs 1485 # Sample count of references to valid blocks. 550system.cpu.l2cache.tags.avg_refs 0.062626 # Average number of references to valid blocks. 551system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 552system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.109849 # Average occupied blocks per requestor 553system.cpu.l2cache.tags.occ_blocks::cpu.data 252.753267 # Average occupied blocks per requestor 554system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020481 # Average percentage of cache occupancy 555system.cpu.l2cache.tags.occ_percent::cpu.data 0.007713 # Average percentage of cache occupancy 556system.cpu.l2cache.tags.occ_percent::total 0.028194 # Average percentage of cache occupancy | 552system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.453398 # Average occupied blocks per requestor 553system.cpu.l2cache.tags.occ_blocks::cpu.data 252.799011 # Average occupied blocks per requestor 554system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020491 # Average percentage of cache occupancy 555system.cpu.l2cache.tags.occ_percent::cpu.data 0.007715 # Average percentage of cache occupancy 556system.cpu.l2cache.tags.occ_percent::total 0.028206 # Average percentage of cache occupancy |
| 557system.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id 558system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 559system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id 560system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201 # Occupied blocks per task id 561system.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id 562system.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses 563system.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses | 557system.cpu.l2cache.tags.occ_task_id_blocks::1024 1485 # Occupied blocks per task id 558system.cpu.l2cache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 559system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id 560system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1201 # Occupied blocks per task id 561system.cpu.l2cache.tags.occ_task_id_percent::1024 0.045319 # Percentage of cache occupancy per task id 562system.cpu.l2cache.tags.tag_accesses 14109 # Number of tag accesses 563system.cpu.l2cache.tags.data_accesses 14109 # Number of data accesses |
| 564system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states | 564system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states |
| 565system.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits 566system.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits 567system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits 568system.cpu.l2cache.ReadCleanReq_hits::total 11 # number of ReadCleanReq hits 569system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 570system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 571system.cpu.l2cache.demand_hits::cpu.inst 11 # number of demand (read+write) hits 572system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits --- 10 unchanged lines hidden (view full) --- 583system.cpu.l2cache.demand_misses::cpu.inst 1167 # number of demand (read+write) misses 584system.cpu.l2cache.demand_misses::cpu.data 318 # number of demand (read+write) misses 585system.cpu.l2cache.demand_misses::total 1485 # number of demand (read+write) misses 586system.cpu.l2cache.overall_misses::cpu.inst 1167 # number of overall misses 587system.cpu.l2cache.overall_misses::cpu.data 318 # number of overall misses 588system.cpu.l2cache.overall_misses::total 1485 # number of overall misses 589system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles 590system.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles | 565system.cpu.l2cache.WritebackClean_hits::writebacks 80 # number of WritebackClean hits 566system.cpu.l2cache.WritebackClean_hits::total 80 # number of WritebackClean hits 567system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 11 # number of ReadCleanReq hits 568system.cpu.l2cache.ReadCleanReq_hits::total 11 # number of ReadCleanReq hits 569system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 570system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits 571system.cpu.l2cache.demand_hits::cpu.inst 11 # number of demand (read+write) hits 572system.cpu.l2cache.demand_hits::cpu.data 2 # number of demand (read+write) hits --- 10 unchanged lines hidden (view full) --- 583system.cpu.l2cache.demand_misses::cpu.inst 1167 # number of demand (read+write) misses 584system.cpu.l2cache.demand_misses::cpu.data 318 # number of demand (read+write) misses 585system.cpu.l2cache.demand_misses::total 1485 # number of demand (read+write) misses 586system.cpu.l2cache.overall_misses::cpu.inst 1167 # number of overall misses 587system.cpu.l2cache.overall_misses::cpu.data 318 # number of overall misses 588system.cpu.l2cache.overall_misses::total 1485 # number of overall misses 589system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15818500 # number of ReadExReq miss cycles 590system.cpu.l2cache.ReadExReq_miss_latency::total 15818500 # number of ReadExReq miss cycles |
| 591system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 96885000 # number of ReadCleanReq miss cycles 592system.cpu.l2cache.ReadCleanReq_miss_latency::total 96885000 # number of ReadCleanReq miss cycles 593system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10642000 # number of ReadSharedReq miss cycles 594system.cpu.l2cache.ReadSharedReq_miss_latency::total 10642000 # number of ReadSharedReq miss cycles 595system.cpu.l2cache.demand_miss_latency::cpu.inst 96885000 # number of demand (read+write) miss cycles 596system.cpu.l2cache.demand_miss_latency::cpu.data 26460500 # number of demand (read+write) miss cycles 597system.cpu.l2cache.demand_miss_latency::total 123345500 # number of demand (read+write) miss cycles 598system.cpu.l2cache.overall_miss_latency::cpu.inst 96885000 # number of overall miss cycles 599system.cpu.l2cache.overall_miss_latency::cpu.data 26460500 # number of overall miss cycles 600system.cpu.l2cache.overall_miss_latency::total 123345500 # number of overall miss cycles | 591system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 97124500 # number of ReadCleanReq miss cycles 592system.cpu.l2cache.ReadCleanReq_miss_latency::total 97124500 # number of ReadCleanReq miss cycles 593system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10659000 # number of ReadSharedReq miss cycles 594system.cpu.l2cache.ReadSharedReq_miss_latency::total 10659000 # number of ReadSharedReq miss cycles 595system.cpu.l2cache.demand_miss_latency::cpu.inst 97124500 # number of demand (read+write) miss cycles 596system.cpu.l2cache.demand_miss_latency::cpu.data 26477500 # number of demand (read+write) miss cycles 597system.cpu.l2cache.demand_miss_latency::total 123602000 # number of demand (read+write) miss cycles 598system.cpu.l2cache.overall_miss_latency::cpu.inst 97124500 # number of overall miss cycles 599system.cpu.l2cache.overall_miss_latency::cpu.data 26477500 # number of overall miss cycles 600system.cpu.l2cache.overall_miss_latency::total 123602000 # number of overall miss cycles |
| 601system.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses) 602system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses) 603system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses) 604system.cpu.l2cache.ReadExReq_accesses::total 202 # number of ReadExReq accesses(hits+misses) 605system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1178 # number of ReadCleanReq accesses(hits+misses) 606system.cpu.l2cache.ReadCleanReq_accesses::total 1178 # number of ReadCleanReq accesses(hits+misses) 607system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 118 # number of ReadSharedReq accesses(hits+misses) 608system.cpu.l2cache.ReadSharedReq_accesses::total 118 # number of ReadSharedReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 621system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990662 # miss rate for demand accesses 622system.cpu.l2cache.demand_miss_rate::cpu.data 0.993750 # miss rate for demand accesses 623system.cpu.l2cache.demand_miss_rate::total 0.991322 # miss rate for demand accesses 624system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990662 # miss rate for overall accesses 625system.cpu.l2cache.overall_miss_rate::cpu.data 0.993750 # miss rate for overall accesses 626system.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses 627system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency | 601system.cpu.l2cache.WritebackClean_accesses::writebacks 80 # number of WritebackClean accesses(hits+misses) 602system.cpu.l2cache.WritebackClean_accesses::total 80 # number of WritebackClean accesses(hits+misses) 603system.cpu.l2cache.ReadExReq_accesses::cpu.data 202 # number of ReadExReq accesses(hits+misses) 604system.cpu.l2cache.ReadExReq_accesses::total 202 # number of ReadExReq accesses(hits+misses) 605system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1178 # number of ReadCleanReq accesses(hits+misses) 606system.cpu.l2cache.ReadCleanReq_accesses::total 1178 # number of ReadCleanReq accesses(hits+misses) 607system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 118 # number of ReadSharedReq accesses(hits+misses) 608system.cpu.l2cache.ReadSharedReq_accesses::total 118 # number of ReadSharedReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 621system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990662 # miss rate for demand accesses 622system.cpu.l2cache.demand_miss_rate::cpu.data 0.993750 # miss rate for demand accesses 623system.cpu.l2cache.demand_miss_rate::total 0.991322 # miss rate for demand accesses 624system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990662 # miss rate for overall accesses 625system.cpu.l2cache.overall_miss_rate::cpu.data 0.993750 # miss rate for overall accesses 626system.cpu.l2cache.overall_miss_rate::total 0.991322 # miss rate for overall accesses 627system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78309.405941 # average ReadExReq miss latency 628system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78309.405941 # average ReadExReq miss latency |
| 629system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83020.565553 # average ReadCleanReq miss latency 630system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83020.565553 # average ReadCleanReq miss latency 631system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91741.379310 # average ReadSharedReq miss latency 632system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91741.379310 # average ReadSharedReq miss latency 633system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency 634system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency 635system.cpu.l2cache.demand_avg_miss_latency::total 83060.942761 # average overall miss latency 636system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency 637system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency 638system.cpu.l2cache.overall_avg_miss_latency::total 83060.942761 # average overall miss latency | 629system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83225.792631 # average ReadCleanReq miss latency 630system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83225.792631 # average ReadCleanReq miss latency 631system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91887.931034 # average ReadSharedReq miss latency 632system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91887.931034 # average ReadSharedReq miss latency 633system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency 634system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency 635system.cpu.l2cache.demand_avg_miss_latency::total 83233.670034 # average overall miss latency 636system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency 637system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency 638system.cpu.l2cache.overall_avg_miss_latency::total 83233.670034 # average overall miss latency |
| 639system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 640system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 641system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 642system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 643system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 644system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 645system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses 646system.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 651system.cpu.l2cache.demand_mshr_misses::cpu.inst 1167 # number of demand (read+write) MSHR misses 652system.cpu.l2cache.demand_mshr_misses::cpu.data 318 # number of demand (read+write) MSHR misses 653system.cpu.l2cache.demand_mshr_misses::total 1485 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.overall_mshr_misses::cpu.inst 1167 # number of overall MSHR misses 655system.cpu.l2cache.overall_mshr_misses::cpu.data 318 # number of overall MSHR misses 656system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses 657system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles 658system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles | 639system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 640system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 641system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 642system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 643system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 644system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 645system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 202 # number of ReadExReq MSHR misses 646system.cpu.l2cache.ReadExReq_mshr_misses::total 202 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 651system.cpu.l2cache.demand_mshr_misses::cpu.inst 1167 # number of demand (read+write) MSHR misses 652system.cpu.l2cache.demand_mshr_misses::cpu.data 318 # number of demand (read+write) MSHR misses 653system.cpu.l2cache.demand_mshr_misses::total 1485 # number of demand (read+write) MSHR misses 654system.cpu.l2cache.overall_mshr_misses::cpu.inst 1167 # number of overall MSHR misses 655system.cpu.l2cache.overall_mshr_misses::cpu.data 318 # number of overall MSHR misses 656system.cpu.l2cache.overall_mshr_misses::total 1485 # number of overall MSHR misses 657system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13798500 # number of ReadExReq MSHR miss cycles 658system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13798500 # number of ReadExReq MSHR miss cycles |
| 659system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles 660system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles 661system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles 662system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles 663system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles 664system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles 665system.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles 666system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles 667system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles 668system.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles | 659system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85454500 # number of ReadCleanReq MSHR miss cycles 660system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85454500 # number of ReadCleanReq MSHR miss cycles 661system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9499000 # number of ReadSharedReq MSHR miss cycles 662system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9499000 # number of ReadSharedReq MSHR miss cycles 663system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85454500 # number of demand (read+write) MSHR miss cycles 664system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23297500 # number of demand (read+write) MSHR miss cycles 665system.cpu.l2cache.demand_mshr_miss_latency::total 108752000 # number of demand (read+write) MSHR miss cycles 666system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85454500 # number of overall MSHR miss cycles 667system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23297500 # number of overall MSHR miss cycles 668system.cpu.l2cache.overall_mshr_miss_latency::total 108752000 # number of overall MSHR miss cycles |
| 669system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 670system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 671system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses 672system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990662 # mshr miss rate for ReadCleanReq accesses 673system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.983051 # mshr miss rate for ReadSharedReq accesses 674system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.983051 # mshr miss rate for ReadSharedReq accesses 675system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for demand accesses 676system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for demand accesses 677system.cpu.l2cache.demand_mshr_miss_rate::total 0.991322 # mshr miss rate for demand accesses 678system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for overall accesses 679system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for overall accesses 680system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses 681system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency 682system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency | 669system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 670system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 671system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for ReadCleanReq accesses 672system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990662 # mshr miss rate for ReadCleanReq accesses 673system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.983051 # mshr miss rate for ReadSharedReq accesses 674system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.983051 # mshr miss rate for ReadSharedReq accesses 675system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for demand accesses 676system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for demand accesses 677system.cpu.l2cache.demand_mshr_miss_rate::total 0.991322 # mshr miss rate for demand accesses 678system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990662 # mshr miss rate for overall accesses 679system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.993750 # mshr miss rate for overall accesses 680system.cpu.l2cache.overall_mshr_miss_rate::total 0.991322 # mshr miss rate for overall accesses 681system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68309.405941 # average ReadExReq mshr miss latency 682system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68309.405941 # average ReadExReq mshr miss latency |
| 683system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency 684system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency 685system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency 686system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency 687system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency 688system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency 689system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency 690system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency 691system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency 692system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency | 683system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73225.792631 # average ReadCleanReq mshr miss latency 684system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73225.792631 # average ReadCleanReq mshr miss latency 685system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81887.931034 # average ReadSharedReq mshr miss latency 686system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81887.931034 # average ReadSharedReq mshr miss latency 687system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency 688system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency 689system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency 690system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency 691system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency 692system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency |
| 693system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter. 694system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data. 695system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 696system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 697system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 698system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 693system.cpu.toL2Bus.snoop_filter.tot_requests 1578 # Total number of requests made to the snoop filter. 694system.cpu.toL2Bus.snoop_filter.hit_single_requests 82 # Number of requests hitting in the snoop filter with a single holder of the requested data. 695system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 696system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 697system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 698system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 699system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states | 699system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states |
| 700system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution 701system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution 702system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution 703system.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution 704system.cpu.toL2Bus.trans_dist::ReadCleanReq 1178 # Transaction distribution 705system.cpu.toL2Bus.trans_dist::ReadSharedReq 118 # Transaction distribution 706system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2436 # Packet count per connected master and slave (bytes) 707system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes) --- 21 unchanged lines hidden (view full) --- 729system.cpu.toL2Bus.respLayer1.occupancy 480000 # Layer occupancy (ticks) 730system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 731system.membus.snoop_filter.tot_requests 1485 # Total number of requests made to the snoop filter. 732system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 733system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 734system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 735system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 736system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 700system.cpu.toL2Bus.trans_dist::ReadResp 1296 # Transaction distribution 701system.cpu.toL2Bus.trans_dist::WritebackClean 80 # Transaction distribution 702system.cpu.toL2Bus.trans_dist::ReadExReq 202 # Transaction distribution 703system.cpu.toL2Bus.trans_dist::ReadExResp 202 # Transaction distribution 704system.cpu.toL2Bus.trans_dist::ReadCleanReq 1178 # Transaction distribution 705system.cpu.toL2Bus.trans_dist::ReadSharedReq 118 # Transaction distribution 706system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2436 # Packet count per connected master and slave (bytes) 707system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 640 # Packet count per connected master and slave (bytes) --- 21 unchanged lines hidden (view full) --- 729system.cpu.toL2Bus.respLayer1.occupancy 480000 # Layer occupancy (ticks) 730system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 731system.membus.snoop_filter.tot_requests 1485 # Total number of requests made to the snoop filter. 732system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 733system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 734system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 735system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 736system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 737system.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states | 737system.membus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states |
| 738system.membus.trans_dist::ReadResp 1283 # Transaction distribution 739system.membus.trans_dist::ReadExReq 202 # Transaction distribution 740system.membus.trans_dist::ReadExResp 202 # Transaction distribution 741system.membus.trans_dist::ReadSharedReq 1283 # Transaction distribution 742system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2970 # Packet count per connected master and slave (bytes) 743system.membus.pkt_count::total 2970 # Packet count per connected master and slave (bytes) 744system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 95040 # Cumulative packet size per connected master and slave (bytes) 745system.membus.pkt_size::total 95040 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 750system.membus.snoop_fanout::stdev 0 # Request fanout histogram 751system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 752system.membus.snoop_fanout::0 1485 100.00% 100.00% # Request fanout histogram 753system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 754system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 755system.membus.snoop_fanout::min_value 0 # Request fanout histogram 756system.membus.snoop_fanout::max_value 0 # Request fanout histogram 757system.membus.snoop_fanout::total 1485 # Request fanout histogram | 738system.membus.trans_dist::ReadResp 1283 # Transaction distribution 739system.membus.trans_dist::ReadExReq 202 # Transaction distribution 740system.membus.trans_dist::ReadExResp 202 # Transaction distribution 741system.membus.trans_dist::ReadSharedReq 1283 # Transaction distribution 742system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2970 # Packet count per connected master and slave (bytes) 743system.membus.pkt_count::total 2970 # Packet count per connected master and slave (bytes) 744system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 95040 # Cumulative packet size per connected master and slave (bytes) 745system.membus.pkt_size::total 95040 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 750system.membus.snoop_fanout::stdev 0 # Request fanout histogram 751system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 752system.membus.snoop_fanout::0 1485 100.00% 100.00% # Request fanout histogram 753system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 754system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 755system.membus.snoop_fanout::min_value 0 # Request fanout histogram 756system.membus.snoop_fanout::max_value 0 # Request fanout histogram 757system.membus.snoop_fanout::total 1485 # Request fanout histogram |
| 758system.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks) | 758system.membus.reqLayer0.occupancy 1721500 # Layer occupancy (ticks) |
| 759system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) | 759system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) |
| 760system.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks) | 760system.membus.respLayer1.occupancy 7876000 # Layer occupancy (ticks) |
| 761system.membus.respLayer1.utilization 2.3 # Layer utilization (%) 762 763---------- End Simulation Statistics ---------- | 761system.membus.respLayer1.utilization 2.3 # Layer utilization (%) 762 763---------- End Simulation Statistics ---------- |