4,5c4,5
< sim_ticks 339160000 # Number of ticks simulated
< final_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 339173000 # Number of ticks simulated
> final_tick 339173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 25032 # Simulator instruction rate (inst/s)
< host_op_rate 25032 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 28360795 # Simulator tick rate (ticks/s)
< host_mem_usage 244952 # Number of bytes of host memory used
< host_seconds 11.96 # Real time elapsed on the host
---
> host_inst_rate 215547 # Simulator instruction rate (inst/s)
> host_op_rate 215545 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 244214530 # Simulator tick rate (ticks/s)
> host_mem_usage 263004 # Number of bytes of host memory used
> host_seconds 1.39 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 220206207 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 60004776 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 280210984 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 220206207 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 220206207 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 220206207 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 60004776 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 280210984 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 338943500 # Total gap between requests
---
> system.physmem.totGap 338956500 # Total gap between requests
192c192
< system.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 221.082687 # Bytes accessed per row activation
194,199c194,199
< system.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::0-127 68 23.86% 23.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 71 24.91% 48.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 38 13.33% 62.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 36 12.63% 74.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 28 9.82% 84.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 14 4.91% 89.47% # Bytes accessed per row activation
204,205c204,205
< system.physmem.totQLat 19805250 # Total ticks spent queuing
< system.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 20061750 # Total ticks spent queuing
> system.physmem.totMemAccLat 47905500 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13509.60 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 32259.60 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 280.21 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 280.21 # Average system read bandwidth in MiByte/s
224c224
< system.physmem.avgGap 228244.78 # Average gap between requests
---
> system.physmem.avgGap 228253.54 # Average gap between requests
231,234c231,234
< system.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actBackEnergy 16018710 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 699840 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 123298980 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 12114720 # Energy for precharge power-down per rank (pJ)
236,239c236,239
< system.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ)
< system.physmem_0.averagePower 553.629673 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states
---
> system.physmem_0.totalEnergy 187848570 # Total energy per rank (pJ)
> system.physmem_0.averagePower 553.841711 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 301380500 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 552000 # Time in different power states
242,244c242,244
< system.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 31555500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 24953750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 270385000 # Time in different power states
250,253c250,253
< system.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actBackEnergy 12906510 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 3648480 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 105703080 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 26147040 # Energy for precharge power-down per rank (pJ)
255,258c255,258
< system.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ)
< system.physmem_1.averagePower 537.082660 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states
---
> system.physmem_1.totalEnergy 182057565 # Total energy per rank (pJ)
> system.physmem_1.averagePower 536.767851 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 301140750 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 8284250 # Time in different power states
261,269c261,269
< system.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 80709 # Number of BP lookups
< system.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 38294 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::PRE_PDN 68075000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 18122250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 231773750 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 80662 # Number of BP lookups
> system.cpu.branchPred.condPredicted 51937 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 5790 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 60622 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 38260 # Number of BTB hits
271c271
< system.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 63.112401 # BTB Hit Percentage
274,275c274,275
< system.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 7506 # Number of indirect target hits.
---
> system.cpu.branchPred.indirectLookups 13147 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 7489 # Number of indirect target hits.
298,299c298,299
< system.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 678320 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 339173000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 678346 # number of cpu cycles simulated
304c304
< system.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 13899 # Number of ops (including micro ops) which were discarded before commit
306,307c306,307
< system.cpu.cpi 2.265946 # CPI: cycles per instruction
< system.cpu.ipc 0.441317 # IPC: instructions per cycle
---
> system.cpu.cpi 2.266033 # CPI: cycles per instruction
> system.cpu.ipc 0.441300 # IPC: instructions per cycle
347,349c347,349
< system.cpu.tickCycles 449536 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 449143 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 229203 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
351,352c351,352
< system.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 254.242270 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 119892 # Total number of references to valid blocks.
354c354
< system.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 374.662500 # Average number of references to valid blocks.
356,358c356,358
< system.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 254.242270 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.062071 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.062071 # Average percentage of cache occupancy
364,368c364,368
< system.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 241156 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 241126 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 241126 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 71739 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 71739 # number of ReadReq hits
371,374c371,374
< system.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits
< system.cpu.dcache.overall_hits::total 119907 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 119892 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 119892 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 119892 # number of overall hits
> system.cpu.dcache.overall_hits::total 119892 # number of overall hits
383,384c383,384
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10980000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10980000 # number of ReadReq miss cycles
387,392c387,392
< system.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 71872 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 71872 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 42500500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 42500500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 42500500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 42500500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 71857 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 71857 # number of ReadReq accesses(hits+misses)
395,398c395,398
< system.cpu.dcache.demand_accesses::cpu.data 120418 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 120418 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 120418 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 120418 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 120403 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 120403 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 120403 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 120403 # number of overall (read+write) accesses
407,408c407,408
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93050.847458 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 93050.847458 # average ReadReq miss latency
411,414c411,414
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 83137.964775 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 83171.232877 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 83171.232877 # average overall miss latency
435,436c435,436
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10845000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10845000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862000 # number of ReadReq MSHR miss cycles
439,442c439,442
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26967000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26967000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26967000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26967000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26984000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 26984000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26984000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26984000 # number of overall MSHR miss cycles
447,452c447,452
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.002657 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.002657 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91906.779661 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91906.779661 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.002658 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.002658 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92050.847458 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92050.847458 # average ReadReq mshr miss latency
455,459c455,459
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
461,462c461,462
< system.cpu.icache.tags.tagsinuse 640.869470 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 135081 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 641.197715 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 134928 # Total number of references to valid blocks.
464c464
< system.cpu.icache.tags.avg_refs 114.669779 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 114.539898 # Average number of references to valid blocks.
466,468c466,468
< system.cpu.icache.tags.occ_blocks::cpu.inst 640.869470 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.312925 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.312925 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 641.197715 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.313085 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.313085 # Average percentage of cache occupancy
474,482c474,482
< system.cpu.icache.tags.tag_accesses 273696 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 273696 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 135081 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 135081 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 135081 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 135081 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 135081 # number of overall hits
< system.cpu.icache.overall_hits::total 135081 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 273390 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 273390 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 134928 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 134928 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 134928 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 134928 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 134928 # number of overall hits
> system.cpu.icache.overall_hits::total 134928 # number of overall hits
489,512c489,512
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 99945500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 99945500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 99945500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 99945500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 99945500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 99945500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 136259 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 136259 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 136259 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 136259 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 136259 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 136259 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008645 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.008645 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.008645 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.008645 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.008645 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.008645 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84843.378608 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 84843.378608 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 84843.378608 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 84843.378608 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 100185000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 100185000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 100185000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 100185000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 100185000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 100185000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 136106 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 136106 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 136106 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 136106 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 136106 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 136106 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008655 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.008655 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.008655 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.008655 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.008655 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.008655 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85046.689304 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 85046.689304 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 85046.689304 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 85046.689304 # average overall miss latency
527,545c527,545
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 98767500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 98767500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 98767500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 98767500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 98767500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 98767500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008645 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.008645 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.008645 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.378608 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.378608 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 99007000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 99007000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 99007000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 99007000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 99007000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 99007000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008655 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.008655 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.008655 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84046.689304 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84046.689304 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
547c547
< system.cpu.l2cache.tags.tagsinuse 923.863116 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 924.252410 # Cycle average of tags in use
552,556c552,556
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.109849 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 252.753267 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020481 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.007713 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.028194 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.453398 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 252.799011 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020491 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.007715 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.028206 # Average percentage of cache occupancy
564c564
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
591,600c591,600
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 96885000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 96885000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10642000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 10642000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 96885000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 26460500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 123345500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 96885000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 26460500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 123345500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 97124500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 97124500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10659000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 10659000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 97124500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 26477500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 123602000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 97124500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 26477500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 123602000 # number of overall miss cycles
629,638c629,638
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83020.565553 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83020.565553 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91741.379310 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91741.379310 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 83060.942761 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 83060.942761 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83225.792631 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83225.792631 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91887.931034 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91887.931034 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 83233.670034 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 83233.670034 # average overall miss latency
659,668c659,668
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85454500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85454500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9499000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9499000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85454500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23297500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 108752000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85454500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23297500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 108752000 # number of overall MSHR miss cycles
683,692c683,692
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73225.792631 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73225.792631 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81887.931034 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81887.931034 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency
699c699
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
737c737
< system.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
758c758
< system.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1721500 # Layer occupancy (ticks)
760c760
< system.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 7876000 # Layer occupancy (ticks)
< sim_ticks 339160000 # Number of ticks simulated
< final_tick 339160000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 339173000 # Number of ticks simulated
> final_tick 339173000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 25032 # Simulator instruction rate (inst/s)
< host_op_rate 25032 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 28360795 # Simulator tick rate (ticks/s)
< host_mem_usage 244952 # Number of bytes of host memory used
< host_seconds 11.96 # Real time elapsed on the host
---
> host_inst_rate 215547 # Simulator instruction rate (inst/s)
> host_op_rate 215545 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 244214530 # Simulator tick rate (ticks/s)
> host_mem_usage 263004 # Number of bytes of host memory used
> host_seconds 1.39 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 220214648 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 60007076 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 280221724 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 220214648 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 220214648 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 220214648 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 60007076 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 280221724 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 220206207 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 60004776 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 280210984 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 220206207 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 220206207 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 220206207 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 60004776 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 280210984 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 338943500 # Total gap between requests
---
> system.physmem.totGap 338956500 # Total gap between requests
192c192
< system.physmem.bytesPerActivate::gmean 221.469651 # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::gmean 221.082687 # Bytes accessed per row activation
194,199c194,199
< system.physmem.bytesPerActivate::0-127 67 23.51% 23.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 73 25.61% 49.12% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 39 13.68% 62.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 33 11.58% 74.39% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 28 9.82% 84.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 15 5.26% 89.47% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::0-127 68 23.86% 23.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 71 24.91% 48.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 38 13.33% 62.11% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 36 12.63% 74.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 28 9.82% 84.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 14 4.91% 89.47% # Bytes accessed per row activation
204,205c204,205
< system.physmem.totQLat 19805250 # Total ticks spent queuing
< system.physmem.totMemAccLat 47649000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 20061750 # Total ticks spent queuing
> system.physmem.totMemAccLat 47905500 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 13336.87 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13509.60 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 32086.87 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 280.22 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 32259.60 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 280.21 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 280.22 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 280.21 # Average system read bandwidth in MiByte/s
224c224
< system.physmem.avgGap 228244.78 # Average gap between requests
---
> system.physmem.avgGap 228253.54 # Average gap between requests
231,234c231,234
< system.physmem_0.actBackEnergy 16006740 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 700320 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 122840700 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 12504960 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.actBackEnergy 16018710 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 699840 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 123298980 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 12114720 # Energy for precharge power-down per rank (pJ)
236,239c236,239
< system.physmem_0.totalEnergy 187769040 # Total energy per rank (pJ)
< system.physmem_0.averagePower 553.629673 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 301401000 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 546000 # Time in different power states
---
> system.physmem_0.totalEnergy 187848570 # Total energy per rank (pJ)
> system.physmem_0.averagePower 553.841711 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 301380500 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 552000 # Time in different power states
242,244c242,244
< system.physmem_0.memoryStateTime::PRE_PDN 32576500 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 24926250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 269384500 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 31555500 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 24953750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 270385000 # Time in different power states
250,253c250,253
< system.physmem_1.actBackEnergy 12901950 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 3644640 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 106370550 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 25587360 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_1.actBackEnergy 12906510 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 3648480 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 105703080 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 26147040 # Energy for precharge power-down per rank (pJ)
255,258c255,258
< system.physmem_1.totalEnergy 182156955 # Total energy per rank (pJ)
< system.physmem_1.averagePower 537.082660 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 301148500 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 8278250 # Time in different power states
---
> system.physmem_1.totalEnergy 182057565 # Total energy per rank (pJ)
> system.physmem_1.averagePower 536.767851 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 301140750 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 8284250 # Time in different power states
261,269c261,269
< system.physmem_1.memoryStateTime::PRE_PDN 66617000 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 18107500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 233239500 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 80709 # Number of BP lookups
< system.cpu.branchPred.condPredicted 51944 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 5835 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 64346 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 38294 # Number of BTB hits
---
> system.physmem_1.memoryStateTime::PRE_PDN 68075000 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 18122250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 231773750 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 80662 # Number of BP lookups
> system.cpu.branchPred.condPredicted 51937 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 5790 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 60622 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 38260 # Number of BTB hits
271c271
< system.cpu.branchPred.BTBHitPct 59.512635 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 63.112401 # BTB Hit Percentage
274,275c274,275
< system.cpu.branchPred.indirectLookups 13164 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 7506 # Number of indirect target hits.
---
> system.cpu.branchPred.indirectLookups 13147 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 7489 # Number of indirect target hits.
298,299c298,299
< system.cpu.pwrStateResidencyTicks::ON 339160000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 678320 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 339173000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 678346 # number of cpu cycles simulated
304c304
< system.cpu.discardedOps 13959 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 13899 # Number of ops (including micro ops) which were discarded before commit
306,307c306,307
< system.cpu.cpi 2.265946 # CPI: cycles per instruction
< system.cpu.ipc 0.441317 # IPC: instructions per cycle
---
> system.cpu.cpi 2.266033 # CPI: cycles per instruction
> system.cpu.ipc 0.441300 # IPC: instructions per cycle
347,349c347,349
< system.cpu.tickCycles 449536 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 228784 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 449143 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 229203 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
351,352c351,352
< system.cpu.dcache.tags.tagsinuse 254.196505 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 119907 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 254.242270 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 119892 # Total number of references to valid blocks.
354c354
< system.cpu.dcache.tags.avg_refs 374.709375 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 374.662500 # Average number of references to valid blocks.
356,358c356,358
< system.cpu.dcache.tags.occ_blocks::cpu.data 254.196505 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.062060 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.062060 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 254.242270 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.062071 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.062071 # Average percentage of cache occupancy
364,368c364,368
< system.cpu.dcache.tags.tag_accesses 241156 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 241156 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 71754 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 71754 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 241126 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 241126 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 71739 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 71739 # number of ReadReq hits
371,374c371,374
< system.cpu.dcache.demand_hits::cpu.data 119907 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 119907 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 119907 # number of overall hits
< system.cpu.dcache.overall_hits::total 119907 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 119892 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 119892 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 119892 # number of overall hits
> system.cpu.dcache.overall_hits::total 119892 # number of overall hits
383,384c383,384
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 10963000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 10963000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10980000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10980000 # number of ReadReq miss cycles
387,392c387,392
< system.cpu.dcache.demand_miss_latency::cpu.data 42483500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 42483500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 42483500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 42483500 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 71872 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 71872 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 42500500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 42500500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 42500500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 42500500 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 71857 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 71857 # number of ReadReq accesses(hits+misses)
395,398c395,398
< system.cpu.dcache.demand_accesses::cpu.data 120418 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 120418 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 120418 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 120418 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 120403 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 120403 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 120403 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 120403 # number of overall (read+write) accesses
407,408c407,408
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 92906.779661 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 92906.779661 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 93050.847458 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 93050.847458 # average ReadReq miss latency
411,414c411,414
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 83137.964775 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 83137.964775 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 83137.964775 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 83171.232877 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 83171.232877 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 83171.232877 # average overall miss latency
435,436c435,436
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10845000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10845000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10862000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10862000 # number of ReadReq MSHR miss cycles
439,442c439,442
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26967000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26967000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26967000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26967000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26984000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 26984000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26984000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26984000 # number of overall MSHR miss cycles
447,452c447,452
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.002657 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002657 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.002657 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 91906.779661 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 91906.779661 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.002658 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002658 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.002658 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 92050.847458 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 92050.847458 # average ReadReq mshr miss latency
455,459c455,459
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84271.875000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 84271.875000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84325 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 84325 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
461,462c461,462
< system.cpu.icache.tags.tagsinuse 640.869470 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 135081 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 641.197715 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 134928 # Total number of references to valid blocks.
464c464
< system.cpu.icache.tags.avg_refs 114.669779 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 114.539898 # Average number of references to valid blocks.
466,468c466,468
< system.cpu.icache.tags.occ_blocks::cpu.inst 640.869470 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.312925 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.312925 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 641.197715 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.313085 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.313085 # Average percentage of cache occupancy
474,482c474,482
< system.cpu.icache.tags.tag_accesses 273696 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 273696 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 135081 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 135081 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 135081 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 135081 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 135081 # number of overall hits
< system.cpu.icache.overall_hits::total 135081 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 273390 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 273390 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 134928 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 134928 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 134928 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 134928 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 134928 # number of overall hits
> system.cpu.icache.overall_hits::total 134928 # number of overall hits
489,512c489,512
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 99945500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 99945500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 99945500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 99945500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 99945500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 99945500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 136259 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 136259 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 136259 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 136259 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 136259 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 136259 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008645 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.008645 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.008645 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.008645 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.008645 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.008645 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 84843.378608 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 84843.378608 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 84843.378608 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 84843.378608 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 84843.378608 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 100185000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 100185000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 100185000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 100185000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 100185000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 100185000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 136106 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 136106 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 136106 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 136106 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 136106 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 136106 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008655 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.008655 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.008655 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.008655 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.008655 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.008655 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 85046.689304 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 85046.689304 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 85046.689304 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 85046.689304 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 85046.689304 # average overall miss latency
527,545c527,545
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 98767500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 98767500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 98767500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 98767500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 98767500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 98767500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008645 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.008645 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008645 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.008645 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83843.378608 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83843.378608 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83843.378608 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 83843.378608 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 99007000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 99007000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 99007000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 99007000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 99007000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 99007000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008655 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.008655 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008655 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.008655 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84046.689304 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84046.689304 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84046.689304 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 84046.689304 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
547c547
< system.cpu.l2cache.tags.tagsinuse 923.863116 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 924.252410 # Cycle average of tags in use
552,556c552,556
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.109849 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 252.753267 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020481 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.007713 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.028194 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 671.453398 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 252.799011 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020491 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.007715 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.028206 # Average percentage of cache occupancy
564c564
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
591,600c591,600
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 96885000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 96885000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10642000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 10642000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 96885000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 26460500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 123345500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 96885000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 26460500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 123345500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 97124500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 97124500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10659000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 10659000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 97124500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 26477500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 123602000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 97124500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 26477500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 123602000 # number of overall miss cycles
629,638c629,638
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83020.565553 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83020.565553 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91741.379310 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91741.379310 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 83060.942761 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83020.565553 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83209.119497 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 83060.942761 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83225.792631 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83225.792631 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91887.931034 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91887.931034 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 83233.670034 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83225.792631 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83262.578616 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 83233.670034 # average overall miss latency
659,668c659,668
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85215000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85215000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9482000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9482000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85215000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23280500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 108495500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85215000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23280500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 108495500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85454500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85454500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9499000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9499000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85454500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23297500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 108752000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85454500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23297500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 108752000 # number of overall MSHR miss cycles
683,692c683,692
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73020.565553 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73020.565553 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81741.379310 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81741.379310 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73020.565553 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73209.119497 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73060.942761 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73225.792631 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73225.792631 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81887.931034 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81887.931034 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73225.792631 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73262.578616 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73233.670034 # average overall mshr miss latency
699c699
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
737c737
< system.membus.pwrStateResidencyTicks::UNDEFINED 339160000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 339173000 # Cumulative time (in ticks) in various power states
758c758
< system.membus.reqLayer0.occupancy 1720000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 1721500 # Layer occupancy (ticks)
760c760
< system.membus.respLayer1.occupancy 7877750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 7876000 # Layer occupancy (ticks)