1
2---------- Begin Simulation Statistics ----------
| 1
2---------- Begin Simulation Statistics ----------
|
3sim_seconds 0.000139 # Number of seconds simulated
4sim_ticks 138549500 # Number of ticks simulated
5final_tick 138549500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 338688 # Simulator instruction rate (inst/s)
8host_op_rate 338651 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 708977788 # Simulator tick rate (ticks/s)
10host_mem_usage 242940 # Number of bytes of host memory used
11host_seconds 0.20 # Real time elapsed on the host
12sim_insts 66173 # Number of instructions simulated
13sim_ops 66173 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 33600 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 16064 # Number of bytes read from this memory
19system.physmem.bytes_read::total 49664 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 33600 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 33600 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 525 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 251 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 776 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 242512604 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 115944121 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 358456725 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 242512604 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 242512604 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 242512604 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 115944121 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 358456725 # Total bandwidth to/from this memory (bytes/s)
33system.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
34system.cpu_clk_domain.clock 500 # Clock period in ticks
35system.cpu.dtb.read_hits 0 # DTB read hits
36system.cpu.dtb.read_misses 0 # DTB read misses
37system.cpu.dtb.read_accesses 0 # DTB read accesses
38system.cpu.dtb.write_hits 0 # DTB write hits
39system.cpu.dtb.write_misses 0 # DTB write misses
40system.cpu.dtb.write_accesses 0 # DTB write accesses
41system.cpu.dtb.hits 0 # DTB hits
42system.cpu.dtb.misses 0 # DTB misses
43system.cpu.dtb.accesses 0 # DTB accesses
44system.cpu.itb.read_hits 0 # DTB read hits
45system.cpu.itb.read_misses 0 # DTB read misses
46system.cpu.itb.read_accesses 0 # DTB read accesses
47system.cpu.itb.write_hits 0 # DTB write hits
48system.cpu.itb.write_misses 0 # DTB write misses
49system.cpu.itb.write_accesses 0 # DTB write accesses
50system.cpu.itb.hits 0 # DTB hits
51system.cpu.itb.misses 0 # DTB misses
52system.cpu.itb.accesses 0 # DTB accesses
53system.cpu.workload.numSyscalls 9 # Number of system calls
54system.cpu.pwrStateResidencyTicks::ON 138549500 # Cumulative time (in ticks) in various power states
55system.cpu.numCycles 277099 # number of cpu cycles simulated
56system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
57system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
58system.cpu.committedInsts 66173 # Number of instructions committed
59system.cpu.committedOps 66173 # Number of ops (including micro ops) committed
60system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses
61system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
62system.cpu.num_func_calls 5169 # number of times a function call or return occured
63system.cpu.num_conditional_control_insts 10311 # number of instructions that are conditional controls
64system.cpu.num_int_insts 66174 # number of integer instructions
65system.cpu.num_fp_insts 0 # number of float instructions
66system.cpu.num_int_register_reads 89437 # number of times the integer registers were read
67system.cpu.num_int_register_writes 43419 # number of times the integer registers were written
68system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
69system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
70system.cpu.num_mem_refs 24255 # number of memory refs
71system.cpu.num_load_insts 11810 # Number of load instructions
72system.cpu.num_store_insts 12445 # Number of store instructions
73system.cpu.num_idle_cycles 0 # Number of idle cycles
74system.cpu.num_busy_cycles 277099 # Number of busy cycles
75system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
76system.cpu.idle_fraction 0 # Percentage of idle cycles
77system.cpu.Branches 15480 # Number of branches fetched
78system.cpu.op_class::No_OpClass 9 0.01% 0.01% # Class of executed instruction
79system.cpu.op_class::IntAlu 41896 63.30% 63.32% # Class of executed instruction
80system.cpu.op_class::IntMult 15 0.02% 63.34% # Class of executed instruction
81system.cpu.op_class::IntDiv 8 0.01% 63.35% # Class of executed instruction
82system.cpu.op_class::FloatAdd 0 0.00% 63.35% # Class of executed instruction
83system.cpu.op_class::FloatCmp 0 0.00% 63.35% # Class of executed instruction
84system.cpu.op_class::FloatCvt 0 0.00% 63.35% # Class of executed instruction
85system.cpu.op_class::FloatMult 0 0.00% 63.35% # Class of executed instruction
86system.cpu.op_class::FloatMultAcc 0 0.00% 63.35% # Class of executed instruction
87system.cpu.op_class::FloatDiv 0 0.00% 63.35% # Class of executed instruction
88system.cpu.op_class::FloatMisc 0 0.00% 63.35% # Class of executed instruction
89system.cpu.op_class::FloatSqrt 0 0.00% 63.35% # Class of executed instruction
90system.cpu.op_class::SimdAdd 0 0.00% 63.35% # Class of executed instruction
91system.cpu.op_class::SimdAddAcc 0 0.00% 63.35% # Class of executed instruction
92system.cpu.op_class::SimdAlu 0 0.00% 63.35% # Class of executed instruction
93system.cpu.op_class::SimdCmp 0 0.00% 63.35% # Class of executed instruction
94system.cpu.op_class::SimdCvt 0 0.00% 63.35% # Class of executed instruction
95system.cpu.op_class::SimdMisc 0 0.00% 63.35% # Class of executed instruction
96system.cpu.op_class::SimdMult 0 0.00% 63.35% # Class of executed instruction
97system.cpu.op_class::SimdMultAcc 0 0.00% 63.35% # Class of executed instruction
98system.cpu.op_class::SimdShift 0 0.00% 63.35% # Class of executed instruction
99system.cpu.op_class::SimdShiftAcc 0 0.00% 63.35% # Class of executed instruction
100system.cpu.op_class::SimdSqrt 0 0.00% 63.35% # Class of executed instruction
101system.cpu.op_class::SimdFloatAdd 0 0.00% 63.35% # Class of executed instruction
102system.cpu.op_class::SimdFloatAlu 0 0.00% 63.35% # Class of executed instruction
103system.cpu.op_class::SimdFloatCmp 0 0.00% 63.35% # Class of executed instruction
104system.cpu.op_class::SimdFloatCvt 0 0.00% 63.35% # Class of executed instruction
105system.cpu.op_class::SimdFloatDiv 0 0.00% 63.35% # Class of executed instruction
106system.cpu.op_class::SimdFloatMisc 0 0.00% 63.35% # Class of executed instruction
107system.cpu.op_class::SimdFloatMult 0 0.00% 63.35% # Class of executed instruction
108system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.35% # Class of executed instruction
109system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.35% # Class of executed instruction
110system.cpu.op_class::MemRead 11810 17.84% 81.20% # Class of executed instruction
111system.cpu.op_class::MemWrite 12445 18.80% 100.00% # Class of executed instruction
112system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
113system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
114system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
115system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
116system.cpu.op_class::total 66183 # Class of executed instruction
117system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
118system.cpu.dcache.tags.replacements 0 # number of replacements
119system.cpu.dcache.tags.tagsinuse 195.060322 # Cycle average of tags in use
120system.cpu.dcache.tags.total_refs 24002 # Total number of references to valid blocks.
121system.cpu.dcache.tags.sampled_refs 251 # Sample count of references to valid blocks.
122system.cpu.dcache.tags.avg_refs 95.625498 # Average number of references to valid blocks.
123system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
124system.cpu.dcache.tags.occ_blocks::cpu.data 195.060322 # Average occupied blocks per requestor
125system.cpu.dcache.tags.occ_percent::cpu.data 0.047622 # Average percentage of cache occupancy
126system.cpu.dcache.tags.occ_percent::total 0.047622 # Average percentage of cache occupancy
127system.cpu.dcache.tags.occ_task_id_blocks::1024 251 # Occupied blocks per task id
128system.cpu.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
129system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
130system.cpu.dcache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id
131system.cpu.dcache.tags.occ_task_id_percent::1024 0.061279 # Percentage of cache occupancy per task id
132system.cpu.dcache.tags.tag_accesses 48757 # Number of tag accesses
133system.cpu.dcache.tags.data_accesses 48757 # Number of data accesses
134system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
135system.cpu.dcache.ReadReq_hits::cpu.data 11758 # number of ReadReq hits
136system.cpu.dcache.ReadReq_hits::total 11758 # number of ReadReq hits
137system.cpu.dcache.WriteReq_hits::cpu.data 12243 # number of WriteReq hits
138system.cpu.dcache.WriteReq_hits::total 12243 # number of WriteReq hits
139system.cpu.dcache.LoadLockedReq_hits::cpu.data 1 # number of LoadLockedReq hits
140system.cpu.dcache.LoadLockedReq_hits::total 1 # number of LoadLockedReq hits
141system.cpu.dcache.demand_hits::cpu.data 24001 # number of demand (read+write) hits
142system.cpu.dcache.demand_hits::total 24001 # number of demand (read+write) hits
143system.cpu.dcache.overall_hits::cpu.data 24001 # number of overall hits
144system.cpu.dcache.overall_hits::total 24001 # number of overall hits
145system.cpu.dcache.ReadReq_misses::cpu.data 51 # number of ReadReq misses
146system.cpu.dcache.ReadReq_misses::total 51 # number of ReadReq misses
147system.cpu.dcache.WriteReq_misses::cpu.data 200 # number of WriteReq misses
148system.cpu.dcache.WriteReq_misses::total 200 # number of WriteReq misses
149system.cpu.dcache.demand_misses::cpu.data 251 # number of demand (read+write) misses
150system.cpu.dcache.demand_misses::total 251 # number of demand (read+write) misses
151system.cpu.dcache.overall_misses::cpu.data 251 # number of overall misses
152system.cpu.dcache.overall_misses::total 251 # number of overall misses
153system.cpu.dcache.ReadReq_miss_latency::cpu.data 3213000 # number of ReadReq miss cycles
154system.cpu.dcache.ReadReq_miss_latency::total 3213000 # number of ReadReq miss cycles
155system.cpu.dcache.WriteReq_miss_latency::cpu.data 12600000 # number of WriteReq miss cycles
156system.cpu.dcache.WriteReq_miss_latency::total 12600000 # number of WriteReq miss cycles
157system.cpu.dcache.demand_miss_latency::cpu.data 15813000 # number of demand (read+write) miss cycles
158system.cpu.dcache.demand_miss_latency::total 15813000 # number of demand (read+write) miss cycles
159system.cpu.dcache.overall_miss_latency::cpu.data 15813000 # number of overall miss cycles
160system.cpu.dcache.overall_miss_latency::total 15813000 # number of overall miss cycles
161system.cpu.dcache.ReadReq_accesses::cpu.data 11809 # number of ReadReq accesses(hits+misses)
162system.cpu.dcache.ReadReq_accesses::total 11809 # number of ReadReq accesses(hits+misses)
163system.cpu.dcache.WriteReq_accesses::cpu.data 12443 # number of WriteReq accesses(hits+misses)
164system.cpu.dcache.WriteReq_accesses::total 12443 # number of WriteReq accesses(hits+misses)
165system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1 # number of LoadLockedReq accesses(hits+misses)
166system.cpu.dcache.LoadLockedReq_accesses::total 1 # number of LoadLockedReq accesses(hits+misses)
167system.cpu.dcache.demand_accesses::cpu.data 24252 # number of demand (read+write) accesses
168system.cpu.dcache.demand_accesses::total 24252 # number of demand (read+write) accesses
169system.cpu.dcache.overall_accesses::cpu.data 24252 # number of overall (read+write) accesses
170system.cpu.dcache.overall_accesses::total 24252 # number of overall (read+write) accesses
171system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004319 # miss rate for ReadReq accesses
172system.cpu.dcache.ReadReq_miss_rate::total 0.004319 # miss rate for ReadReq accesses
173system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.016073 # miss rate for WriteReq accesses
174system.cpu.dcache.WriteReq_miss_rate::total 0.016073 # miss rate for WriteReq accesses
175system.cpu.dcache.demand_miss_rate::cpu.data 0.010350 # miss rate for demand accesses
176system.cpu.dcache.demand_miss_rate::total 0.010350 # miss rate for demand accesses
177system.cpu.dcache.overall_miss_rate::cpu.data 0.010350 # miss rate for overall accesses
178system.cpu.dcache.overall_miss_rate::total 0.010350 # miss rate for overall accesses
179system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
180system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
181system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
182system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
183system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
184system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
185system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
186system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
187system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
188system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
189system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
190system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
191system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
192system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
193system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses
194system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses
195system.cpu.dcache.WriteReq_mshr_misses::cpu.data 200 # number of WriteReq MSHR misses
196system.cpu.dcache.WriteReq_mshr_misses::total 200 # number of WriteReq MSHR misses
197system.cpu.dcache.demand_mshr_misses::cpu.data 251 # number of demand (read+write) MSHR misses
198system.cpu.dcache.demand_mshr_misses::total 251 # number of demand (read+write) MSHR misses
199system.cpu.dcache.overall_mshr_misses::cpu.data 251 # number of overall MSHR misses
200system.cpu.dcache.overall_mshr_misses::total 251 # number of overall MSHR misses
201system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3162000 # number of ReadReq MSHR miss cycles
202system.cpu.dcache.ReadReq_mshr_miss_latency::total 3162000 # number of ReadReq MSHR miss cycles
203system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12400000 # number of WriteReq MSHR miss cycles
204system.cpu.dcache.WriteReq_mshr_miss_latency::total 12400000 # number of WriteReq MSHR miss cycles
205system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15562000 # number of demand (read+write) MSHR miss cycles
206system.cpu.dcache.demand_mshr_miss_latency::total 15562000 # number of demand (read+write) MSHR miss cycles
207system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15562000 # number of overall MSHR miss cycles
208system.cpu.dcache.overall_mshr_miss_latency::total 15562000 # number of overall MSHR miss cycles
209system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004319 # mshr miss rate for ReadReq accesses
210system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004319 # mshr miss rate for ReadReq accesses
211system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.016073 # mshr miss rate for WriteReq accesses
212system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.016073 # mshr miss rate for WriteReq accesses
213system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010350 # mshr miss rate for demand accesses
214system.cpu.dcache.demand_mshr_miss_rate::total 0.010350 # mshr miss rate for demand accesses
215system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.010350 # mshr miss rate for overall accesses
216system.cpu.dcache.overall_mshr_miss_rate::total 0.010350 # mshr miss rate for overall accesses
217system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
218system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
219system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
220system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
221system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
222system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
223system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
224system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
225system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
226system.cpu.icache.tags.replacements 10 # number of replacements
227system.cpu.icache.tags.tagsinuse 190.684855 # Cycle average of tags in use
228system.cpu.icache.tags.total_refs 65659 # Total number of references to valid blocks.
229system.cpu.icache.tags.sampled_refs 525 # Sample count of references to valid blocks.
230system.cpu.icache.tags.avg_refs 125.064762 # Average number of references to valid blocks.
231system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
232system.cpu.icache.tags.occ_blocks::cpu.inst 190.684855 # Average occupied blocks per requestor
233system.cpu.icache.tags.occ_percent::cpu.inst 0.093108 # Average percentage of cache occupancy
234system.cpu.icache.tags.occ_percent::total 0.093108 # Average percentage of cache occupancy
235system.cpu.icache.tags.occ_task_id_blocks::1024 515 # Occupied blocks per task id
236system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id
237system.cpu.icache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id
238system.cpu.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id
239system.cpu.icache.tags.occ_task_id_percent::1024 0.251465 # Percentage of cache occupancy per task id
240system.cpu.icache.tags.tag_accesses 132893 # Number of tag accesses
241system.cpu.icache.tags.data_accesses 132893 # Number of data accesses
242system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
243system.cpu.icache.ReadReq_hits::cpu.inst 65659 # number of ReadReq hits
244system.cpu.icache.ReadReq_hits::total 65659 # number of ReadReq hits
245system.cpu.icache.demand_hits::cpu.inst 65659 # number of demand (read+write) hits
246system.cpu.icache.demand_hits::total 65659 # number of demand (read+write) hits
247system.cpu.icache.overall_hits::cpu.inst 65659 # number of overall hits
248system.cpu.icache.overall_hits::total 65659 # number of overall hits
249system.cpu.icache.ReadReq_misses::cpu.inst 525 # number of ReadReq misses
250system.cpu.icache.ReadReq_misses::total 525 # number of ReadReq misses
251system.cpu.icache.demand_misses::cpu.inst 525 # number of demand (read+write) misses
252system.cpu.icache.demand_misses::total 525 # number of demand (read+write) misses
253system.cpu.icache.overall_misses::cpu.inst 525 # number of overall misses
254system.cpu.icache.overall_misses::total 525 # number of overall misses
255system.cpu.icache.ReadReq_miss_latency::cpu.inst 33076500 # number of ReadReq miss cycles
256system.cpu.icache.ReadReq_miss_latency::total 33076500 # number of ReadReq miss cycles
257system.cpu.icache.demand_miss_latency::cpu.inst 33076500 # number of demand (read+write) miss cycles
258system.cpu.icache.demand_miss_latency::total 33076500 # number of demand (read+write) miss cycles
259system.cpu.icache.overall_miss_latency::cpu.inst 33076500 # number of overall miss cycles
260system.cpu.icache.overall_miss_latency::total 33076500 # number of overall miss cycles
261system.cpu.icache.ReadReq_accesses::cpu.inst 66184 # number of ReadReq accesses(hits+misses)
262system.cpu.icache.ReadReq_accesses::total 66184 # number of ReadReq accesses(hits+misses)
263system.cpu.icache.demand_accesses::cpu.inst 66184 # number of demand (read+write) accesses
264system.cpu.icache.demand_accesses::total 66184 # number of demand (read+write) accesses
265system.cpu.icache.overall_accesses::cpu.inst 66184 # number of overall (read+write) accesses
266system.cpu.icache.overall_accesses::total 66184 # number of overall (read+write) accesses
267system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007932 # miss rate for ReadReq accesses
268system.cpu.icache.ReadReq_miss_rate::total 0.007932 # miss rate for ReadReq accesses
269system.cpu.icache.demand_miss_rate::cpu.inst 0.007932 # miss rate for demand accesses
270system.cpu.icache.demand_miss_rate::total 0.007932 # miss rate for demand accesses
271system.cpu.icache.overall_miss_rate::cpu.inst 0.007932 # miss rate for overall accesses
272system.cpu.icache.overall_miss_rate::total 0.007932 # miss rate for overall accesses
273system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63002.857143 # average ReadReq miss latency
274system.cpu.icache.ReadReq_avg_miss_latency::total 63002.857143 # average ReadReq miss latency
275system.cpu.icache.demand_avg_miss_latency::cpu.inst 63002.857143 # average overall miss latency
276system.cpu.icache.demand_avg_miss_latency::total 63002.857143 # average overall miss latency
277system.cpu.icache.overall_avg_miss_latency::cpu.inst 63002.857143 # average overall miss latency
278system.cpu.icache.overall_avg_miss_latency::total 63002.857143 # average overall miss latency
279system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
280system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
281system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
282system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
283system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
284system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
285system.cpu.icache.writebacks::writebacks 10 # number of writebacks
286system.cpu.icache.writebacks::total 10 # number of writebacks
287system.cpu.icache.ReadReq_mshr_misses::cpu.inst 525 # number of ReadReq MSHR misses
288system.cpu.icache.ReadReq_mshr_misses::total 525 # number of ReadReq MSHR misses
289system.cpu.icache.demand_mshr_misses::cpu.inst 525 # number of demand (read+write) MSHR misses
290system.cpu.icache.demand_mshr_misses::total 525 # number of demand (read+write) MSHR misses
291system.cpu.icache.overall_mshr_misses::cpu.inst 525 # number of overall MSHR misses
292system.cpu.icache.overall_mshr_misses::total 525 # number of overall MSHR misses
293system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32551500 # number of ReadReq MSHR miss cycles
294system.cpu.icache.ReadReq_mshr_miss_latency::total 32551500 # number of ReadReq MSHR miss cycles
295system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32551500 # number of demand (read+write) MSHR miss cycles
296system.cpu.icache.demand_mshr_miss_latency::total 32551500 # number of demand (read+write) MSHR miss cycles
297system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32551500 # number of overall MSHR miss cycles
298system.cpu.icache.overall_mshr_miss_latency::total 32551500 # number of overall MSHR miss cycles
299system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.007932 # mshr miss rate for ReadReq accesses
300system.cpu.icache.ReadReq_mshr_miss_rate::total 0.007932 # mshr miss rate for ReadReq accesses
301system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.007932 # mshr miss rate for demand accesses
302system.cpu.icache.demand_mshr_miss_rate::total 0.007932 # mshr miss rate for demand accesses
303system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.007932 # mshr miss rate for overall accesses
304system.cpu.icache.overall_mshr_miss_rate::total 0.007932 # mshr miss rate for overall accesses
305system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62002.857143 # average ReadReq mshr miss latency
306system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62002.857143 # average ReadReq mshr miss latency
307system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62002.857143 # average overall mshr miss latency
308system.cpu.icache.demand_avg_mshr_miss_latency::total 62002.857143 # average overall mshr miss latency
309system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62002.857143 # average overall mshr miss latency
310system.cpu.icache.overall_avg_mshr_miss_latency::total 62002.857143 # average overall mshr miss latency
311system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
312system.cpu.l2cache.tags.replacements 0 # number of replacements
313system.cpu.l2cache.tags.tagsinuse 386.887852 # Cycle average of tags in use
314system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
315system.cpu.l2cache.tags.sampled_refs 776 # Sample count of references to valid blocks.
316system.cpu.l2cache.tags.avg_refs 0.012887 # Average number of references to valid blocks.
317system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
318system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.808508 # Average occupied blocks per requestor
319system.cpu.l2cache.tags.occ_blocks::cpu.data 195.079344 # Average occupied blocks per requestor
320system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005854 # Average percentage of cache occupancy
321system.cpu.l2cache.tags.occ_percent::cpu.data 0.005953 # Average percentage of cache occupancy
322system.cpu.l2cache.tags.occ_percent::total 0.011807 # Average percentage of cache occupancy
323system.cpu.l2cache.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id
324system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id
325system.cpu.l2cache.tags.age_task_id_blocks_1024::1 405 # Occupied blocks per task id
326system.cpu.l2cache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id
327system.cpu.l2cache.tags.occ_task_id_percent::1024 0.023682 # Percentage of cache occupancy per task id
328system.cpu.l2cache.tags.tag_accesses 7064 # Number of tag accesses
329system.cpu.l2cache.tags.data_accesses 7064 # Number of data accesses
330system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
331system.cpu.l2cache.WritebackClean_hits::writebacks 10 # number of WritebackClean hits
332system.cpu.l2cache.WritebackClean_hits::total 10 # number of WritebackClean hits
333system.cpu.l2cache.ReadExReq_misses::cpu.data 200 # number of ReadExReq misses
334system.cpu.l2cache.ReadExReq_misses::total 200 # number of ReadExReq misses
335system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 525 # number of ReadCleanReq misses
336system.cpu.l2cache.ReadCleanReq_misses::total 525 # number of ReadCleanReq misses
337system.cpu.l2cache.ReadSharedReq_misses::cpu.data 51 # number of ReadSharedReq misses
338system.cpu.l2cache.ReadSharedReq_misses::total 51 # number of ReadSharedReq misses
339system.cpu.l2cache.demand_misses::cpu.inst 525 # number of demand (read+write) misses
340system.cpu.l2cache.demand_misses::cpu.data 251 # number of demand (read+write) misses
341system.cpu.l2cache.demand_misses::total 776 # number of demand (read+write) misses
342system.cpu.l2cache.overall_misses::cpu.inst 525 # number of overall misses
343system.cpu.l2cache.overall_misses::cpu.data 251 # number of overall misses
344system.cpu.l2cache.overall_misses::total 776 # number of overall misses
345system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12100000 # number of ReadExReq miss cycles
346system.cpu.l2cache.ReadExReq_miss_latency::total 12100000 # number of ReadExReq miss cycles
347system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 31763500 # number of ReadCleanReq miss cycles
348system.cpu.l2cache.ReadCleanReq_miss_latency::total 31763500 # number of ReadCleanReq miss cycles
349system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3085500 # number of ReadSharedReq miss cycles
350system.cpu.l2cache.ReadSharedReq_miss_latency::total 3085500 # number of ReadSharedReq miss cycles
351system.cpu.l2cache.demand_miss_latency::cpu.inst 31763500 # number of demand (read+write) miss cycles
352system.cpu.l2cache.demand_miss_latency::cpu.data 15185500 # number of demand (read+write) miss cycles
353system.cpu.l2cache.demand_miss_latency::total 46949000 # number of demand (read+write) miss cycles
354system.cpu.l2cache.overall_miss_latency::cpu.inst 31763500 # number of overall miss cycles
355system.cpu.l2cache.overall_miss_latency::cpu.data 15185500 # number of overall miss cycles
356system.cpu.l2cache.overall_miss_latency::total 46949000 # number of overall miss cycles
357system.cpu.l2cache.WritebackClean_accesses::writebacks 10 # number of WritebackClean accesses(hits+misses)
358system.cpu.l2cache.WritebackClean_accesses::total 10 # number of WritebackClean accesses(hits+misses)
359system.cpu.l2cache.ReadExReq_accesses::cpu.data 200 # number of ReadExReq accesses(hits+misses)
360system.cpu.l2cache.ReadExReq_accesses::total 200 # number of ReadExReq accesses(hits+misses)
361system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 525 # number of ReadCleanReq accesses(hits+misses)
362system.cpu.l2cache.ReadCleanReq_accesses::total 525 # number of ReadCleanReq accesses(hits+misses)
363system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 51 # number of ReadSharedReq accesses(hits+misses)
364system.cpu.l2cache.ReadSharedReq_accesses::total 51 # number of ReadSharedReq accesses(hits+misses)
365system.cpu.l2cache.demand_accesses::cpu.inst 525 # number of demand (read+write) accesses
366system.cpu.l2cache.demand_accesses::cpu.data 251 # number of demand (read+write) accesses
367system.cpu.l2cache.demand_accesses::total 776 # number of demand (read+write) accesses
368system.cpu.l2cache.overall_accesses::cpu.inst 525 # number of overall (read+write) accesses
369system.cpu.l2cache.overall_accesses::cpu.data 251 # number of overall (read+write) accesses
370system.cpu.l2cache.overall_accesses::total 776 # number of overall (read+write) accesses
371system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
372system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
373system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses
374system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses
375system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
376system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
377system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
378system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
379system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses
380system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
381system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
382system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses
383system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
384system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
385system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.904762 # average ReadCleanReq miss latency
386system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.904762 # average ReadCleanReq miss latency
387system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
388system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
389system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.904762 # average overall miss latency
390system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
391system.cpu.l2cache.demand_avg_miss_latency::total 60501.288660 # average overall miss latency
392system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.904762 # average overall miss latency
393system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
394system.cpu.l2cache.overall_avg_miss_latency::total 60501.288660 # average overall miss latency
395system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
396system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
397system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
398system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
399system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
400system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
401system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 200 # number of ReadExReq MSHR misses
402system.cpu.l2cache.ReadExReq_mshr_misses::total 200 # number of ReadExReq MSHR misses
403system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 525 # number of ReadCleanReq MSHR misses
404system.cpu.l2cache.ReadCleanReq_mshr_misses::total 525 # number of ReadCleanReq MSHR misses
405system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 51 # number of ReadSharedReq MSHR misses
406system.cpu.l2cache.ReadSharedReq_mshr_misses::total 51 # number of ReadSharedReq MSHR misses
407system.cpu.l2cache.demand_mshr_misses::cpu.inst 525 # number of demand (read+write) MSHR misses
408system.cpu.l2cache.demand_mshr_misses::cpu.data 251 # number of demand (read+write) MSHR misses
409system.cpu.l2cache.demand_mshr_misses::total 776 # number of demand (read+write) MSHR misses
410system.cpu.l2cache.overall_mshr_misses::cpu.inst 525 # number of overall MSHR misses
411system.cpu.l2cache.overall_mshr_misses::cpu.data 251 # number of overall MSHR misses
412system.cpu.l2cache.overall_mshr_misses::total 776 # number of overall MSHR misses
413system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10100000 # number of ReadExReq MSHR miss cycles
414system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10100000 # number of ReadExReq MSHR miss cycles
415system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 26513500 # number of ReadCleanReq MSHR miss cycles
416system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 26513500 # number of ReadCleanReq MSHR miss cycles
417system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2575500 # number of ReadSharedReq MSHR miss cycles
418system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2575500 # number of ReadSharedReq MSHR miss cycles
419system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26513500 # number of demand (read+write) MSHR miss cycles
420system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12675500 # number of demand (read+write) MSHR miss cycles
421system.cpu.l2cache.demand_mshr_miss_latency::total 39189000 # number of demand (read+write) MSHR miss cycles
422system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26513500 # number of overall MSHR miss cycles
423system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12675500 # number of overall MSHR miss cycles
424system.cpu.l2cache.overall_mshr_miss_latency::total 39189000 # number of overall MSHR miss cycles
425system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
426system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
427system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
428system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
429system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
430system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
431system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
432system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
433system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
434system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
435system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
436system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
437system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
438system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
439system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.904762 # average ReadCleanReq mshr miss latency
440system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.904762 # average ReadCleanReq mshr miss latency
441system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
442system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
443system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency
444system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
445system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency
446system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.904762 # average overall mshr miss latency
447system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
448system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.288660 # average overall mshr miss latency
449system.cpu.toL2Bus.snoop_filter.tot_requests 786 # Total number of requests made to the snoop filter.
450system.cpu.toL2Bus.snoop_filter.hit_single_requests 10 # Number of requests hitting in the snoop filter with a single holder of the requested data.
451system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
452system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
453system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
454system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
455system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
456system.cpu.toL2Bus.trans_dist::ReadResp 576 # Transaction distribution
457system.cpu.toL2Bus.trans_dist::WritebackClean 10 # Transaction distribution
458system.cpu.toL2Bus.trans_dist::ReadExReq 200 # Transaction distribution
459system.cpu.toL2Bus.trans_dist::ReadExResp 200 # Transaction distribution
460system.cpu.toL2Bus.trans_dist::ReadCleanReq 525 # Transaction distribution
461system.cpu.toL2Bus.trans_dist::ReadSharedReq 51 # Transaction distribution
462system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1060 # Packet count per connected master and slave (bytes)
463system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 502 # Packet count per connected master and slave (bytes)
464system.cpu.toL2Bus.pkt_count::total 1562 # Packet count per connected master and slave (bytes)
465system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34240 # Cumulative packet size per connected master and slave (bytes)
466system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16064 # Cumulative packet size per connected master and slave (bytes)
467system.cpu.toL2Bus.pkt_size::total 50304 # Cumulative packet size per connected master and slave (bytes)
468system.cpu.toL2Bus.snoops 0 # Total snoops (count)
469system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
470system.cpu.toL2Bus.snoop_fanout::samples 776 # Request fanout histogram
471system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
472system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
473system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
474system.cpu.toL2Bus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram
475system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
477system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
478system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
479system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::total 776 # Request fanout histogram
481system.cpu.toL2Bus.reqLayer0.occupancy 403000 # Layer occupancy (ticks)
482system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
483system.cpu.toL2Bus.respLayer0.occupancy 787500 # Layer occupancy (ticks)
484system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%)
485system.cpu.toL2Bus.respLayer1.occupancy 376500 # Layer occupancy (ticks)
486system.cpu.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%)
487system.membus.snoop_filter.tot_requests 776 # Total number of requests made to the snoop filter.
488system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
489system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
490system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
491system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
492system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
493system.membus.pwrStateResidencyTicks::UNDEFINED 138549500 # Cumulative time (in ticks) in various power states
494system.membus.trans_dist::ReadResp 576 # Transaction distribution
495system.membus.trans_dist::ReadExReq 200 # Transaction distribution
496system.membus.trans_dist::ReadExResp 200 # Transaction distribution
497system.membus.trans_dist::ReadSharedReq 576 # Transaction distribution
498system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1552 # Packet count per connected master and slave (bytes)
499system.membus.pkt_count::total 1552 # Packet count per connected master and slave (bytes)
500system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 49664 # Cumulative packet size per connected master and slave (bytes)
501system.membus.pkt_size::total 49664 # Cumulative packet size per connected master and slave (bytes)
502system.membus.snoops 0 # Total snoops (count)
503system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
504system.membus.snoop_fanout::samples 776 # Request fanout histogram
505system.membus.snoop_fanout::mean 0 # Request fanout histogram
506system.membus.snoop_fanout::stdev 0 # Request fanout histogram
507system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
508system.membus.snoop_fanout::0 776 100.00% 100.00% # Request fanout histogram
509system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
510system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
511system.membus.snoop_fanout::min_value 0 # Request fanout histogram
512system.membus.snoop_fanout::max_value 0 # Request fanout histogram
513system.membus.snoop_fanout::total 776 # Request fanout histogram
514system.membus.reqLayer0.occupancy 777000 # Layer occupancy (ticks)
515system.membus.reqLayer0.utilization 0.6 # Layer utilization (%)
516system.membus.respLayer1.occupancy 3880000 # Layer occupancy (ticks)
517system.membus.respLayer1.utilization 2.8 # Layer utilization (%)
| 3sim_seconds 0.000250
4sim_ticks 250490500
5final_tick 250490500
6sim_freq 1000000000000
7host_inst_rate 3805
8host_op_rate 3814
9host_tick_rate 8705712
10host_mem_usage 268924
11host_seconds 28.77
12sim_insts 109485
13sim_ops 109730
14system.voltage_domain.voltage 1
15system.clk_domain.clock 1000
16system.physmem.pwrStateResidencyTicks::UNDEFINED 250490500
17system.physmem.bytes_read::cpu.inst 44032
18system.physmem.bytes_read::cpu.data 29568
19system.physmem.bytes_read::total 73600
20system.physmem.bytes_inst_read::cpu.inst 44032
21system.physmem.bytes_inst_read::total 44032
22system.physmem.num_reads::cpu.inst 688
23system.physmem.num_reads::cpu.data 462
24system.physmem.num_reads::total 1150
25system.physmem.bw_read::cpu.inst 175783114
26system.physmem.bw_read::cpu.data 118040405
27system.physmem.bw_read::total 293823518
28system.physmem.bw_inst_read::cpu.inst 175783114
29system.physmem.bw_inst_read::total 175783114
30system.physmem.bw_total::cpu.inst 175783114
31system.physmem.bw_total::cpu.data 118040405
32system.physmem.bw_total::total 293823518
33system.pwrStateResidencyTicks::UNDEFINED 250490500
34system.cpu_clk_domain.clock 500
35system.cpu.dtb.read_hits 0
36system.cpu.dtb.read_misses 0
37system.cpu.dtb.read_accesses 0
38system.cpu.dtb.write_hits 0
39system.cpu.dtb.write_misses 0
40system.cpu.dtb.write_accesses 0
41system.cpu.dtb.hits 0
42system.cpu.dtb.misses 0
43system.cpu.dtb.accesses 0
44system.cpu.itb.read_hits 0
45system.cpu.itb.read_misses 0
46system.cpu.itb.read_accesses 0
47system.cpu.itb.write_hits 0
48system.cpu.itb.write_misses 0
49system.cpu.itb.write_accesses 0
50system.cpu.itb.hits 0
51system.cpu.itb.misses 0
52system.cpu.itb.accesses 0
53system.cpu.workload.numSyscalls 43
54system.cpu.pwrStateResidencyTicks::ON 250490500
55system.cpu.numCycles 500981
56system.cpu.numWorkItemsStarted 0
57system.cpu.numWorkItemsCompleted 0
58system.cpu.committedInsts 109485
59system.cpu.committedOps 109730
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61system.cpu.num_fp_alu_accesses 12
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425system.cpu.l2cache.blocked_cycles::no_mshrs 0
426system.cpu.l2cache.blocked_cycles::no_targets 0
427system.cpu.l2cache.blocked::no_mshrs 0
428system.cpu.l2cache.blocked::no_targets 0
429system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
430system.cpu.l2cache.avg_blocked_cycles::no_targets nan
431system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 227
432system.cpu.l2cache.ReadExReq_mshr_misses::total 227
433system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 688
434system.cpu.l2cache.ReadCleanReq_mshr_misses::total 688
435system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 235
436system.cpu.l2cache.ReadSharedReq_mshr_misses::total 235
437system.cpu.l2cache.demand_mshr_misses::cpu.inst 688
438system.cpu.l2cache.demand_mshr_misses::cpu.data 462
439system.cpu.l2cache.demand_mshr_misses::total 1150
440system.cpu.l2cache.overall_mshr_misses::cpu.inst 688
441system.cpu.l2cache.overall_mshr_misses::cpu.data 462
442system.cpu.l2cache.overall_mshr_misses::total 1150
443system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11463500
444system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11463500
445system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 34745000
446system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 34745000
447system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11867500
448system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11867500
449system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34745000
450system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23331000
451system.cpu.l2cache.demand_mshr_miss_latency::total 58076000
452system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34745000
453system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23331000
454system.cpu.l2cache.overall_mshr_miss_latency::total 58076000
455system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1
456system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1
457system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.998549
458system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.998549
459system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1
460system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1
461system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.998549
462system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1
463system.cpu.l2cache.demand_mshr_miss_rate::total 0.999131
464system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.998549
465system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1
466system.cpu.l2cache.overall_mshr_miss_rate::total 0.999131
467system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500
468system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500
469system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.453488
470system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.453488
471system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500
472system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500
473system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.453488
474system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500
475system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.869565
476system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.453488
477system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500
478system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.869565
479system.cpu.toL2Bus.snoop_filter.tot_requests 1189
480system.cpu.toL2Bus.snoop_filter.hit_single_requests 38
481system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
482system.cpu.toL2Bus.snoop_filter.tot_snoops 0
483system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
484system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
485system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250490500
486system.cpu.toL2Bus.trans_dist::ReadResp 924
487system.cpu.toL2Bus.trans_dist::WritebackClean 38
488system.cpu.toL2Bus.trans_dist::ReadExReq 227
489system.cpu.toL2Bus.trans_dist::ReadExResp 227
490system.cpu.toL2Bus.trans_dist::ReadCleanReq 689
491system.cpu.toL2Bus.trans_dist::ReadSharedReq 235
492system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1416
493system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 924
494system.cpu.toL2Bus.pkt_count::total 2340
495system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 46528
496system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29568
497system.cpu.toL2Bus.pkt_size::total 76096
498system.cpu.toL2Bus.snoops 0
499system.cpu.toL2Bus.snoopTraffic 0
500system.cpu.toL2Bus.snoop_fanout::samples 1151
501system.cpu.toL2Bus.snoop_fanout::mean 0
502system.cpu.toL2Bus.snoop_fanout::stdev 0
503system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
504system.cpu.toL2Bus.snoop_fanout::0 1151 100.00% 100.00%
505system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00%
506system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
507system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
508system.cpu.toL2Bus.snoop_fanout::min_value 0
509system.cpu.toL2Bus.snoop_fanout::max_value 0
510system.cpu.toL2Bus.snoop_fanout::total 1151
511system.cpu.toL2Bus.reqLayer0.occupancy 632500
512system.cpu.toL2Bus.reqLayer0.utilization 0.3
513system.cpu.toL2Bus.respLayer0.occupancy 1033500
514system.cpu.toL2Bus.respLayer0.utilization 0.4
515system.cpu.toL2Bus.respLayer1.occupancy 693000
516system.cpu.toL2Bus.respLayer1.utilization 0.3
517system.membus.snoop_filter.tot_requests 1150
518system.membus.snoop_filter.hit_single_requests 0
519system.membus.snoop_filter.hit_multi_requests 0
520system.membus.snoop_filter.tot_snoops 0
521system.membus.snoop_filter.hit_single_snoops 0
522system.membus.snoop_filter.hit_multi_snoops 0
523system.membus.pwrStateResidencyTicks::UNDEFINED 250490500
524system.membus.trans_dist::ReadResp 923
525system.membus.trans_dist::ReadExReq 227
526system.membus.trans_dist::ReadExResp 227
527system.membus.trans_dist::ReadSharedReq 923
528system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2300
529system.membus.pkt_count::total 2300
530system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 73600
531system.membus.pkt_size::total 73600
532system.membus.snoops 0
533system.membus.snoopTraffic 0
534system.membus.snoop_fanout::samples 1150
535system.membus.snoop_fanout::mean 0
536system.membus.snoop_fanout::stdev 0
537system.membus.snoop_fanout::underflows 0 0.00% 0.00%
538system.membus.snoop_fanout::0 1150 100.00% 100.00%
539system.membus.snoop_fanout::1 0 0.00% 100.00%
540system.membus.snoop_fanout::overflows 0 0.00% 100.00%
541system.membus.snoop_fanout::min_value 0
542system.membus.snoop_fanout::max_value 0
543system.membus.snoop_fanout::total 1150
544system.membus.reqLayer0.occupancy 1151000
545system.membus.reqLayer0.utilization 0.5
546system.membus.respLayer1.occupancy 5750000
547system.membus.respLayer1.utilization 2.3
|
518
519---------- End Simulation Statistics ----------
| 548
549---------- End Simulation Statistics ----------
|