1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000796 # Number of seconds simulated 4sim_ticks 796036 # Number of ticks simulated 5final_tick 796036 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000 # Frequency of simulated ticks 7host_inst_rate 163786 # Simulator instruction rate (inst/s) 8host_op_rate 163781 # Simulator op (including micro ops) rate (op/s) --- 285 unchanged lines hidden (view full) --- 294system.cpu.itb.read_misses 0 # DTB read misses 295system.cpu.itb.read_accesses 0 # DTB read accesses 296system.cpu.itb.write_hits 0 # DTB write hits 297system.cpu.itb.write_misses 0 # DTB write misses 298system.cpu.itb.write_accesses 0 # DTB write accesses 299system.cpu.itb.hits 0 # DTB hits 300system.cpu.itb.misses 0 # DTB misses 301system.cpu.itb.accesses 0 # DTB accesses |
302system.cpu.workload.numSyscalls 9 # Number of system calls |
303system.cpu.pwrStateResidencyTicks::ON 796036 # Cumulative time (in ticks) in various power states 304system.cpu.numCycles 796036 # number of cpu cycles simulated 305system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 306system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 307system.cpu.committedInsts 66173 # Number of instructions committed 308system.cpu.committedOps 66173 # Number of ops (including micro ops) committed 309system.cpu.num_int_alu_accesses 66174 # Number of integer alu accesses 310system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses --- 395 unchanged lines hidden --- |